CN103220000A - Serializer and data serializing method - Google Patents
Serializer and data serializing method Download PDFInfo
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- CN103220000A CN103220000A CN2012100498906A CN201210049890A CN103220000A CN 103220000 A CN103220000 A CN 103220000A CN 2012100498906 A CN2012100498906 A CN 2012100498906A CN 201210049890 A CN201210049890 A CN 201210049890A CN 103220000 A CN103220000 A CN 103220000A
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Abstract
The invention provides a serializer. In one embodiment, the serializer converts a parallel input data into a serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-in serial-out shift registers, a plurality of current-mode logic D-type flip-flops, and at least one multiplexer. The parallel-in serial-out shift registers respectively receive partial input bits from a plurality of input bits of the parallel input data, and serialize the partial input bits according to the full-swing clock to generate a plurality of first intermediate data. The current-mode logic D-type flip-flops respectively lock and store the first intermediate data according to the noiseless differential clock to generate a plurality of second intermediate data. The at least one multiplexer interleaves the second intermediate data according to the noiseless differential clock to generate the serial output data.
Description
Technical field
The present invention is relevant for data processing, particularly relevant for the tandemization of data.
Background technology
Serializer (serializer) is converted to the tandem dateout in order to will import data side by side.Therefore, serializer extensively applies in the data processing.When serializer was used in the application of high speed data transfer, the internal circuit unit of serializer must adopt current mode logic (current mode logic, structure CML) at a high speed.Yet the power that the power ratio standard cell that the current mode logic unit is consumed (standard cell) is consumed is many greatly, can increase the power consumption of entire system; And the occupied chip area in the current mode logic unit area more occupied than standard cell is many greatly, can increase the production cost of entire system.Therefore, in order to take into account data transmission bauds and production cost, general serializer inside can comprise current mode logic unit and standard cell simultaneously.
The running of serializer needs the driving according to clock signal.Generally speaking, when serializer comprises current mode logic unit and standard cell simultaneously, the standard cell of tool lower data transmission speed is according to the driving of full swing clock pulse (full swing clock), and the current mode logic unit of tool higher data transmission rate can be according to the driving of differential clock pulse (differential clock).Generally speaking, differential clock pulse is by voltage control oscillator (voltage controlled oscillator, VCO) the directly generation of institute of phase-locked loop (phase locked loop).The full swing clock pulse then needs to be obtained by differential commentaries on classics single-end circuit (differential to single circuit) the differential clock pulse of conversion.Yet, when differential commentaries on classics single-end circuit is changed differential clock pulse and is the full swing clock pulse, can attach in the full swing clock pulse and produce extra noise (noise) and process drift (corner variation).When the current mode logic unit of serializer and standard cell during respectively according to differential clock pulse and the running of full swing clock pulse, current mode logic unit and standard cell just can be because of the process drift between differential clock pulse and the full swing clock pulse can't synchronous operation, thereby cause the mistake of dateout, or the additional noise that the full swing clock pulse caused and cause the shake of tandem device dateout.Therefore, must provide a kind of serializer, can operate according to differential clock pulse and full swing clock pulse, and error in data can not take place.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of serializer (serializer), to solve the problem that known techniques exists.In an embodiment, it is a tandem dateout that this serializer is imported data side by side according to a full swing clock pulse (full swing clock) and muting one differential clock pulse (differential clock) conversion one, comprise and a plurality of incorporating into go here and there out shift registor (Parallel-input-serial-output shift register, PISO), a plurality of current mode logic (current mode logic, CML) D type flip-flop (D fllp-flop) and at least one multiplexer (multiplexer).These are incorporated into and go here and there out shift registor and receive partly respectively in a plurality of input bits of arranged side by side input data and import bit, and these partly import bit according to this full swing clock pulse tandemization, to produce a plurality of first intermediate data.These current mode logic D type flip-flop locks these first intermediate data of storage (latch) respectively according to muting this differential clock pulse, to produce a plurality of second intermediate data.This at least one multiplexer receives these second intermediate data, and interlocks these second intermediate data to produce this tandem dateout according to muting this differential clock pulse.
The present invention more provides a kind of serial data method, is a tandem dateout in order to change input data arranged side by side.In an embodiment, one serializer (serializer) comprises goes here and there out shift registor (Parallel-input-serial-output shift register a plurality of incorporating into, PISO), a plurality of current mode logic (current mode logic, CML) D type flip-flop (D fllp-flop) and at least one multiplexer (multiplexer).At first, incorporate into these and go here and there out shift registor and in a plurality of input bits of arranged side by side input data, receive respectively and partly import bit.Then, incorporate into these and to go here and there out shift registor these partly import bit according to a full swing clock pulse (full swing clock) tandemization, to produce a plurality of first intermediate data.Then, lock storage (latch) these first intermediate data with these current mode logic D type flip-flop respectively according to muting one differential clock pulse (differential clock), to produce a plurality of second intermediate data.At last, interlock these second intermediate data to produce this tandem dateout with this at least one multiplexer according to muting this differential clock pulse.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 is the block diagram of general serializer;
Fig. 2 A is the block diagram of clock pulse generator;
Fig. 2 B is the differential clock pulse that clock pulse generator produced of Fig. 2 A and the schematic diagram of full swing clock pulse;
Fig. 3 A is the block diagram of serializer that combines the clock pulse generator of Fig. 2 A;
Fig. 3 B is the schematic diagram of the error in data that serializer produced of Fig. 3 A;
Fig. 4 A is a block diagram of having removed the serializer of the phase difference that exists between full swing clock pulse and differential clock pulse;
Fig. 4 B is the schematic diagram of data sampling process of the serializer of Fig. 4 A;
Fig. 5 is for preventing the block diagram of the serializer of the shake of tandem dateout and error in data according to the present invention; And
Fig. 6 is the schematic diagram of data sampling process of the serializer of Fig. 5.
The main element symbol description:
(Fig. 1)
100～serializer;
101,102,103,104～5-to-1 incorporates into and goes here and there out shift registor;
111,112,121～2-to-1 multiplexer;
(Fig. 2 A)
200～clock pulse generator;
210～phase-locked loop voltage control oscillator;
220～differential commentaries on classics single-end circuit;
(Fig. 3 A)
300～serializer;
301,302,303,304～5-to-1 incorporates into and goes here and there out shift registor;
311,312,321～2-to-1 multiplexer;
350～phase-locked loop voltage control oscillator;
352～differential commentaries on classics single-end circuit;
(Fig. 4 A)
400～serializer;
401,402,403,404～5-to-1 incorporates into and goes here and there out shift registor;
411,412,421～2-to-1 multiplexer;
450～phase-locked loop voltage control oscillator;
452～differential commentaries on classics single-end circuit;
454～current mode logic buffer;
(Fig. 5)
500～serializer;
501,502,503,504～5-to-1 incorporates into and goes here and there out shift registor;
531,532,533,534～current mode logic D type flip-flop;
511,512,521～2-to-1 multiplexer;
550～phase-locked loop voltage control oscillator;
552～differential commentaries on classics single-end circuit.
Embodiment
Fig. 1 is the block diagram of general serializer 100.Serializer 100 receives and comprises the dateout arranged side by side of 20 bits, and will import data side by side and be converted to the tandem dateout.Serializer 100 is according to a differential clock pulse (differential clock) and a full swing clock pulse (full swing clock) running.In an embodiment, serializer 100 comprises goes here and there out (parallel input serial output, PISO) shift registor (shift register) 101～104 and a plurality of multiplexer 111,112,121 a plurality of incorporating into.In an embodiment, incorporate into and go here and there out shift registor 101,102,103,104 and go here and there out shift registor for 5-to-1 incorporates into.Incorporate into and go here and there out shift registor 101,102,103,104 and in 20 bits of arranged side by side input data, receive 5 bits respectively, and according to a full swing clock pulse with these 5 bit tandemizations to obtain first serial data.In an embodiment, multiplexer 111,112,121 is all the 2-to-1 multiplexer.Multiplexer 111 is gone here and there out shift registor 101,102 and is received first serial data from incorporating into, and arranges in regular turn to incorporate into according to differential clock pulse and go here and there out first serial data that shift registor 101,102 produced, to produce second serial data.Multiplexer 112 is gone here and there out shift registor 103,104 and is received first serial data from incorporating into, and arranges in regular turn to incorporate into according to differential clock pulse and go here and there out first serial data that shift registor 103,104 produced, to produce second serial data.Multiplexer 121 receives second serial data from multiplexer 111,112, and arranges second serial data that multiplexer 111,112 is produced in regular turn according to differential clock pulse, to produce the tandem dateout.
Fig. 2 A is the block diagram of clock pulse generator 200.Clock pulse generator 200 can produce a differential clock pulse and a full swing clock pulse to drive serializer.In an embodiment, clock pulse generator 200 comprises a phase-locked loop (phase locked loop, PLL) voltage control oscillator (voltage controlled oscillator, VCO) 210 and one differential commentaries on classics single-end circuit (differential to single circuit) 220.Phase-locked loop voltage control oscillator 210 produces differential clock pulse, and differential commentaries on classics single-end circuit 220 produces the full swing clock pulse according to differential clock pulse.Fig. 2 B is the differential clock pulse that clock pulse generator produced of Fig. 2 A and the schematic diagram of full swing clock pulse.When differential commentaries on classics single-end circuit 220 produces the full swing clock pulse according to differential clock pulse, may in the full swing clock pulse, bring two kinds of process drift the most extreme into.When differential commentaries on classics single-end circuit 220 caused slow process drift (S corner variaion) 251, the time that the full swing clock pulse is delayed was longer.When differential commentaries on classics single-end circuit 220 caused fast process drift (F corner variaion) 252, the time that the full swing clock pulse is delayed was shorter.Yet, no matter be S process drift or F process drift, all can make full swing clock pulse and differential clock pulse that one phase difference is arranged, and it is inconsistent to cause going here and there out incorporating into of serializer the running of shift registor and multiplexer, further causes error in data in the tandem dateout.
Fig. 3 A is the block diagram of serializer 300 that combines the clock pulse generator of Fig. 2 A.In an embodiment, serializer 300 comprises goes here and there out shift registor 301～304, a plurality of multiplexer 311,312,321, phase-locked loop voltage control oscillator 350 and differential commentaries on classics single-end circuit 352 a plurality of incorporating into.Incorporate into and go here and there out the function of shift registor 301～304, and the function of multiplexer 311,312,321 is identical with the function of the multiplexer 111,112,121 of Fig. 1 with to go here and there out the function of shift registor 101～104 incorporating into of Fig. 1 identical.Phase-locked loop voltage control oscillator 350 produces muting differential clock pulse to drive the running of multiplexer 311,312,321.Differential commentaries on classics single-end circuit 352 produces the full swing clock pulse according to differential clock pulse, and this full swing clock pulse is incorporated in order to driving and gone here and there out the running of shift registor 301～304.Because differential commentaries on classics single-end circuit 352 makes and produces S process drift or F process drift between full swing clock pulse and the differential clock pulse, make full swing clock pulse and differential clock pulse that one phase difference be arranged, and it is inconsistent with the running of multiplexer 311,312,321 to cause going here and there out incorporating into of serializer 300 shift registor 301～304, further causes error in data in the tandem dateout.
The schematic diagram of the error in data that Fig. 3 B is produced for the serializer 300 of Fig. 3 A.Phase-locked loop voltage control oscillator 350 produces muting one differential clock pulse.Then, differential commentaries on classics single-end circuit 352 produces the full swing clock pulse according to differential clock pulse, has S process drift 361 or F process drift 371 between full swing clock pulse and the differential clock pulse.If when between full swing clock pulse and the differential clock pulse S process drift 361 being arranged, incorporate into and go here and there out shift registor 301～304 then according to the driving generation intermediate data 363 of full swing clock pulse, wherein between intermediate data 363 and full swing clock pulse little delay 362 is arranged.When multiplexer 311,312 during according to the driving sampling intermediate data of differential clock pulse 364, because being 1 interval, differential clock pulse 364 is consistent with intermediate data 363, error in data can't take place.Wherein, differential clock pulse is the state that 1 this differential clock pulse is in high potential, otherwise differential clock pulse is the state that 0 this differential clock pulse is in electronegative potential.
Yet, if when between full swing clock pulse and the differential clock pulse F process drift 371 being arranged, incorporate into and go here and there out shift registor 301～304 then according to the driving generation intermediate data 373 of full swing clock pulse, wherein between intermediate data 373 and full swing clock pulse little delay 372 is arranged.When multiplexer 311,312 is taken a sample intermediate data according to the driving of differential clock pulse 364, because it is not consistent with intermediate data 373 that differential clock pulse 364 is 1 interval, therefore error in data can take place in the sampling process of 311,312 pairs of middle data of multiplexer, and this error in data can be passed among the tandem dateout of serializer 300.Can't determine in advance owing to the generation randomness of S process drift and F process drift, so serializer 300 can produce error in data in the tandem dateout in randomnesss ground.
For fear of the generation of the error in data of Fig. 3 B, must remove the process drift that exists between full swing clock pulse and differential clock pulse, consistent with the phase place of the full swing clock pulse that keeps driving serializer and differential clock pulse.Fig. 4 A is a block diagram of having removed the serializer 400 of the phase difference that exists between full swing clock pulse and differential clock pulse.In an embodiment, serializer 400 comprises goes here and there out shift registor 401～404, a plurality of multiplexer 411,412,421, phase-locked loop voltage control oscillator 450, differential commentaries on classics single-end circuit 452 and current mode logic (current mode logic, CML) buffer 454 a plurality of incorporating into.Incorporate into and go here and there out the function of shift registor 401～404, and the function of multiplexer 411,412,421 is identical with the function of the multiplexer 111,112,121 of Fig. 1 with to go here and there out the function of shift registor 101～104 incorporating into of Fig. 1 identical.Phase-locked loop voltage control oscillator 450 produces the muting first differential clock pulse.Differential commentaries on classics single-end circuit 452 then produces the full swing clock pulse according to the first differential clock pulse, incorporates in order to driving and goes here and there out the running of shift registor 401～404.Then, current mode logic buffer 454 produces the second differential clock pulse according to the full swing clock pulse, to drive the running of multiplexer 411,412,421.When differential commentaries on classics single-end circuit 452 produced the full swing clock pulse according to the first differential clock pulse, differential commentaries on classics single-end circuit 452 made between the full swing clock pulse and the first differential clock pulse and has S process drift or F process drift.When current mode logic buffer 454 produced the second differential clock pulse according to the full swing clock pulse, the second differential clock pulse also had S process drift or the F process drift that exists in the full swing clock pulse.Therefore, do not exist between the full swing clock pulse and the second differential clock pulse and postpone or phase difference, to go here and there out shift registor 401～404 incorporating into of serializer 400 consistent with the running of multiplexer 411,412,421 thereby make, and avoid the error in data in the tandem dateout.
Fig. 4 B is the schematic diagram of data sampling process of the serializer 400 of Fig. 4 A.Phase-locked loop voltage control oscillator 450 produces the muting first differential clock pulse.Then, differential commentaries on classics single-end circuit 452 produces the full swing clock pulse according to the first differential clock pulse, has S process drift 461 or F process drift 471 between the full swing clock pulse and the first differential clock pulse.If when between the full swing clock pulse and the first differential clock pulse S process drift 461 being arranged, incorporate into and go here and there out shift registor 401～404 then according to the driving generation intermediate data 465 of full swing clock pulse, wherein between intermediate data 465 and full swing clock pulse little delay 462 is arranged.In addition, current mode logic buffer 454 more produces the second differential clock pulse 464 according to the full swing clock pulse, because of the process drift of current-mode-logic circuit not obvious, so only have phase difference 463 slightly between the full swing clock pulse and the second differential clock pulse.When multiplexer 411,412 during according to the driving sampling intermediate data 465 of the second differential clock pulse 464, because being 0 interval, differential clock pulse 464 is consistent with intermediate data 465, error in data can't take place.Same, if when between the full swing clock pulse and the first differential clock pulse F process drift 471 being arranged, incorporate into and go here and there out shift registor 401～404, wherein between intermediate data 475 and full swing clock pulse little delay 472 is arranged then according to the driving generation intermediate data 475 of full swing clock pulse.In addition, current mode logic buffer 454 more produces the second differential clock pulse 474 according to the full swing clock pulse, wherein only has phase difference 473 slightly between the full swing clock pulse and the second differential clock pulse.When multiplexer 411,412 during according to the driving sampling intermediate data 475 of the second differential clock pulse 474, because being 0 interval, differential clock pulse 474 is consistent with intermediate data 475, error in data can't take place.
Though serializer 400 can avoid the tandem dateout to produce error in data, yet the tandem dateout of serializer 400 has very big shake (jitter).Because the noise that differential commentaries on classics single-end circuit 452 produces in the full swing clock pulse can be passed among the second differential clock pulse, multiplexer 411,412,421 just can produce the tandem dateout that has shake when operating according to the second differential clock pulse that has noise, and the usefulness of serializer 400 is descended.
For the shake of the tandem dateout of removing Fig. 4 A, avoid the generation of the error in data of Fig. 3 B again simultaneously, the present invention proposes a kind of tandem device of new kenel.Fig. 5 is for preventing the block diagram of the serializer 500 of the shake of tandem dateout and error in data according to the present invention.Serializer 500 conversions one input data side by side are a tandem dateout.In an embodiment, serializer 500 comprises goes here and there out shift registor 501～504, a plurality of current mode logic (current mode logic, CML) D type flip-flop (D fllp-flop) 531,532,533,534, a plurality of multiplexer 511,512,521, phase-locked loop voltage control oscillator 550 and differential commentaries on classics single-end circuit 552 a plurality of incorporating into.Incorporate into and go here and there out the function of shift registor 501～504 with to go here and there out the function of shift registor 101～104 incorporating into of Fig. 1 identical.531,532,533,534 of current mode logic D type flip-flops are respectively according to differential clock pulse sampling and store to incorporate into and go here and there out first intermediate data that shift registor 501,502,503,504 produced to produce second intermediate data, with the input as multiplexer 511,512.The function of multiplexer 511,512,521 is identical with the function of the multiplexer of Fig. 1 111,112,121.Phase-locked loop voltage control oscillator 550 produces the running of muting differential clock pulse with drive current type logic D type flip-flop 531,532,533,534 and multiplexer 511,512,521.Differential commentaries on classics single-end circuit 552 produces the full swing clock pulse according to differential clock pulse, incorporates into driving and goes here and there out the running of shift registor 501～504.In an embodiment, incorporate into and go here and there out shift registor 501～504 and go here and there out shift registor for 5-to-1 incorporates into.In an embodiment, multiplexer 511,512,521 is the 2-to-1 multiplexer.
At first, incorporate into and go here and there out shift registor 501～504 and in 20 input bits of input data side by side, receive 5 input bits respectively, and 5 input bits being received separately of the full swing clock pulse tandemization that produces according to differential commentaries on classics single-end circuit 552, to produce first intermediate data.Then, the muting differential clock pulse sampling that produces according to phase-locked loop voltage control oscillator 550 of current mode logic D type flip-flop 531～534 and storing is gone here and there out first intermediate data that shift registor 501～504 produced to produce second intermediate data.Then, multiplexer 511,512 is arranged second intermediate data of current mode logic D type flip-flop 531,532 generations respectively to produce the 3rd intermediate data in regular turn according to the muting differential clock pulse of phase-locked loop voltage control oscillator 550 generations.Then, multiplexer 521 is arranged the 3rd intermediate data of multiplexer 511,512 generations in regular turn to produce the tandem dateout according to the muting differential clock pulse of phase-locked loop voltage control oscillator 550 generations.
Produce S process drift or F process drift between full swing clock pulse and the differential clock pulse though differential commentaries on classics single-end circuit 552 makes, make full swing clock pulse and differential clock pulse that one phase difference be arranged.Yet, first intermediate data because the muting differential clock pulse of current mode logic D type flip-flop 531,532 foundations is taken a sample, therefore current mode logic D type flip-flop 531,532 has the phase place that conforms to differential clock pulse according to second intermediate data that muting differential clock pulse produced, can not produce error in data when therefore multiplexer 511,512 is taken a sample second intermediate data according to differential clock pulse, and avoid serializer 500 that the problem of error in data takes place.In addition, because current mode logic D type flip-flop 531～534 and multiplexer 511,512,521 are driven by muting differential clock pulse all, therefore can not produce shake (jitter) in the tandem dateout.Because serializer 500 has successfully been avoided the problem of tandem dateout generation error in data and shake, so the usefulness of the serializer 500 of Fig. 5 be height than the usefulness of the serializer 300,400 of Fig. 3 and Fig. 4.
Fig. 6 is the schematic diagram of data sampling process of the serializer 500 of Fig. 5.Phase-locked loop voltage control oscillator 550 produces muting differential clock pulse.Then, differential commentaries on classics single-end circuit 552 produces the full swing clock pulse according to differential clock pulse, has S process drift 611 or F process drift 621 between full swing clock pulse and the differential clock pulse.If when between full swing clock pulse and the differential clock pulse S process drift 611 being arranged, incorporate into and go here and there out shift registor 501～504 and then produce first intermediate data 614, wherein between first intermediate data 614 and full swing clock pulse little delay 612 is arranged according to the driving of full swing clock pulse.Then, current mode logic D type flip-flop 531～534 is taken a sample according to muting differential clock pulse and is stored first intermediate data 614 to produce second intermediate data 615.When multiplexer 511,512 is taken a sample second intermediate data 615 according to the driving of differential clock pulse 616, because being 0 interval, differential clock pulse 616 is consistent with second intermediate data 615, error in data can't take place.Same, if when between full swing clock pulse and the differential clock pulse F process drift 621 being arranged, incorporate into and go here and there out shift registor 501～504 and then produce first intermediate data 624, wherein between first intermediate data 624 and full swing clock pulse little delay 622 is arranged according to the driving of full swing clock pulse.Then, current mode logic D type flip-flop 531,532,533,534 is taken a sample according to muting differential clock pulse and is stored first intermediate data 624 to produce second intermediate data 625.When multiplexer 511,512 is taken a sample second intermediate data 625 according to the driving of differential clock pulse 616, because the interval of differential clock pulse 616 is consistent with second intermediate data 625, error in data can't take place.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, any those who familiarize themselves with the technology, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (12)
1. a serializer is a tandem dateout according to a full swing clock pulse and muting one differential clock pulse conversion one input data arranged side by side, comprising:
A plurality of incorporating into gone here and there out shift registor, and receive respectively in a plurality of input bits of input data side by side certainly and partly import bit, and according to the described part input of this full swing clock pulse tandemization bit, to produce a plurality of first intermediate data;
A plurality of current mode logic D type flip-flops lock described first intermediate data of storage respectively according to muting this differential clock pulse, to produce a plurality of second intermediate data; And
At least one multiplexer receives described second intermediate data, and interlocks described second intermediate data to produce this tandem dateout according to muting this differential clock pulse.
2. serializer as claimed in claim 1, wherein this serializer more comprises:
One clock generating circuit produces and does not have this differential clock pulse of noise, and derives this full swing clock pulse according to this differential clock pulse.
3. serializer as claimed in claim 2, wherein this clock generating circuit comprises:
One phase-locked loop voltage control oscillator produces and does not have this differential clock pulse of noise; And
One differential commentaries on classics single-end circuit is derived this full swing clock pulse according to this differential clock pulse.
4. serializer as claimed in claim 1, wherein this at least one multiplexer comprises:
A plurality of first multiplexers, described second intermediate data of receiving unit in described second intermediate data respectively, and according to muting this differential clock pulse respectively in regular turn described second intermediate data of aligning part to produce a plurality of the 3rd intermediate data;
One second multiplexer is arranged described the 3rd intermediate data to produce this tandem dateout in regular turn according to muting this differential clock pulse.
5. serializer as claimed in claim 1 wherein saidly incorporates that to go here and there out shift registor be that 5-to-1 incorporates into and goes here and there out shift registor into.
6. serializer as claimed in claim 4, wherein said first multiplexer is the 2-to-1 multiplexer, and this second multiplexer is the 2-to-1 multiplexer.
7. serial data method, in order to change input data arranged side by side is a tandem dateout, wherein a serializer comprises and a plurality of incorporating into goes here and there out shift registor, a plurality of current mode logic D type flip-flop and at least one multiplexer, and this serial data method comprises:
Described incorporating into to go here and there out shift registor and in a plurality of input bits of arranged side by side input data, receive respectively and partly import bit;
Described incorporating into to go here and there out shift registor according to the described part input of full swing clock pulse tandemization bit, to produce a plurality of first intermediate data;
Lock described first intermediate data of storage with described current mode logic D type flip-flop respectively according to muting one differential clock pulse, to produce a plurality of second intermediate data; And
Interlock described second intermediate data to produce this tandem dateout with this at least one multiplexer according to muting this differential clock pulse.
8. serial data method as claimed in claim 7, wherein this serializer more comprises a clock generating circuit, and this method more comprises:
Produce with this clock generating circuit and not have this differential clock pulse of noise; And
Derive this full swing clock pulse with this clock generating circuit according to this differential clock pulse.
9. serial data method as claimed in claim 8, wherein this clock generating circuit comprises:
One phase-locked loop voltage control oscillator produces and does not have this differential clock pulse of noise; And
One differential commentaries on classics single-end circuit is derived this full swing clock pulse according to this differential clock pulse.
10. serial data method as claimed in claim 7, wherein this at least one multiplexer comprises a plurality of first multiplexers and one second multiplexer, and the generation step of this tandem dateout comprises:
With described first multiplexer described second intermediate data of receiving unit in described second intermediate data respectively;
With described first multiplexer according to muting this differential clock pulse respectively in regular turn described second intermediate data of aligning part to produce a plurality of the 3rd intermediate data; And
Arrange described the 3rd intermediate data in regular turn to produce this tandem dateout with this second multiplexer according to muting this differential clock pulse.
11. serial data method as claimed in claim 7 wherein saidly incorporates that to go here and there out shift registor be that 5-to-1 incorporates into and goes here and there out shift registor into.
12. serial data method as claimed in claim 10, wherein said first multiplexer is the 2-to-1 multiplexer, and this second multiplexer is the 2-to-1 multiplexer.
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| Application Number | Priority Date | Filing Date | Title |
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| TW101102438 | 2012-01-20 | ||
| TW101102438A TWI449342B (en) | 2012-01-20 | 2012-01-20 | Serializer and data serializing method |
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| CN103220000A true CN103220000A (en) | 2013-07-24 |
| CN103220000B CN103220000B (en) | 2016-06-29 |
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| US (1) | US8570198B2 (en) |
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| CN107947873A (en) * | 2016-10-13 | 2018-04-20 | 爱思开海力士有限公司 | The method of data transmission system and test transmission data with multiple transmission channels |
| CN108630138A (en) * | 2017-03-15 | 2018-10-09 | 明阳半导体股份有限公司 | Gray scale generation circuit and driving circuit using the same |
| CN109217877A (en) * | 2017-06-29 | 2019-01-15 | 爱思开海力士有限公司 | Serializer and storage device including the serializer |
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| US8630821B2 (en) * | 2011-07-25 | 2014-01-14 | Qualcomm Incorporated | High speed data testing without high speed bit clock |
| KR102006022B1 (en) * | 2013-11-06 | 2019-08-01 | 에스케이하이닉스 주식회사 | Serializer |
| CA2939453A1 (en) * | 2014-01-29 | 2015-08-06 | Matthew Guthaus | Current-mode clock distribution |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201332302A (en) | 2013-08-01 |
| CN103220000B (en) | 2016-06-29 |
| US8570198B2 (en) | 2013-10-29 |
| TWI449342B (en) | 2014-08-11 |
| US20130187799A1 (en) | 2013-07-25 |
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