TW201332302A - Serializer and data serializing method - Google Patents

Abstract

The invention provides a serializer. In one embodiment, the serializer converts parallel input data to serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively select a plurality of received input bits from the input bits of the parallel input data and respectively serialize the received input bits according to the full swing clock to obtain a plurality of first data signals. The CML D flip-flops respectively latch the first data signals according to the noiseless differential clock to generate a plurality of second data signals. The at least one multiplexer interleaves the second data signals according to the noiseless differential clock to generate the serial output data.

Description

Serializer and data serialization method

The present invention relates to data processing, and in particular to serialization of data.

A serializer is used to convert parallel input data into serial output data. Therefore, serializers are widely used in data processing. When the serializer is used in high-speed data transmission applications, the internal circuit unit of the serializer must adopt a high-speed current mode logic (CML) structure. However, the current consumed by the current-type logic unit is much larger than the power consumed by the standard cell, which increases the overall power consumption of the system; the area occupied by the current-type logic unit is larger than the area occupied by the standard unit. Larger, it will increase the overall production cost of the system. Therefore, in order to balance data transmission speed and production cost, a general serializer internally includes a current type logic unit and a standard unit.

The operation of the serializer is driven by the clock signal. In general, when the serializer includes both a current-type logic unit and a standard unit, the standard unit with a lower data transmission speed is driven by a full swing clock and has a higher data transmission speed. The current type logic unit is driven by a differential clock. In general, the differential clock system is directly generated by a voltage controlled oscillator (VCO) of a phase locked loop. The full swing clock is obtained by switching the differential clock to a differential to single circuit. However, when the differential-to-single-ended circuit converts the differential clock to a full-swing clock, it adds additional noise and corner variation to the full swing clock. When the current-type logic unit and the standard unit of the serializer operate according to the differential clock and the full-swing clock, respectively, the current-type logic unit and the standard unit will be between the differential clock and the full-swing clock. The process drifts and cannot be synchronized, resulting in errors in the output data, or additional noise caused by the full swing clock, causing jitter in the output data of the serializer. Therefore, it is necessary to provide a serializer that can operate according to the differential clock and the full swing clock without data errors.

In view of the above, it is an object of the present invention to provide a serializer to solve the problems of the prior art. In one embodiment, the serializer converts a parallel input data into a series of output data according to a full swing clock and a differential clock without noise, including multiple Parallel-input-serial-output shift register (PISO), multiple current mode logic (CML) D-type flip-flops (D filp-flop), and at least A multiplexer. The incorporation of the serial shift register receives a plurality of input bits from the plurality of input bits of the parallel input data, and serializes the partial input bits according to the full swing clock. To generate a plurality of first intermediate materials. The current-type logic D-type flip-flops respectively lock and lock the first intermediate data according to the differential clock without noise to generate a plurality of second intermediate data. The at least one multiplexer receives the second intermediate data and interleaves the second intermediate data according to the differential clock without noise to generate the serial output data.

The invention further provides a data serialization method for converting a parallel input data into a series of output data. In one embodiment, a serializer includes a plurality of Parallel-input-serial-output shift registers (PISO) and a plurality of current mode logic (CML). A D-type flip-flop (D filp-flop), and at least one multiplexer. First, the partial input bit is received from the plurality of input bits of the parallel input data by the incorporation of the serial shift register. Then, the incorporation of the serial shift register registers the partial input bits according to a full swing clock to generate a plurality of first intermediate data. Then, the current-type logic D-type flip-flops respectively lock and lock the first intermediate data according to one of the differential clocks without noise to generate a plurality of second intermediate data. Finally, the at least one multiplexer interleaves the second intermediate data according to the differential clock without noise to generate the serial output data.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

Figure 1 is a block diagram of a general serializer 100. The serializer 100 receives the parallel output data including 20 bits, and converts the parallel input data into the serial output data. The serializer 100 operates in accordance with a differential clock and a full swing clock. In one embodiment, the serializer 100 includes a plurality of parallel input serial output (PISO) shift registers 101-104 and a plurality of multiplexers 111, 112, 121. In one embodiment, the inline out shift register 101, 102, 103, 104 is a 5-to-1 inline out shift register. The incorporation of the serial shift register 101, 102, 103, 104 respectively receives 5 bits from 20 bits of the parallel input data, and serializes the 5 bits according to a full swing clock. To get the first list of data. In one embodiment, the multiplexers 111, 112, 121 are all 2-to-1 multiplexers. The multiplexer 111 receives the first serial data from the in-line serial shift register 101, 102, and sequentially arranges the first ones generated by the serial shift register 101, 102 according to the differential clock. Serialize the data to produce a second series of data. The multiplexer 112 receives the first serial data from the in-line serial shift register 103, 104, and sequentially arranges the first ones generated by the serial shift register 103, 104 according to the differential clock. Serialize the data to produce a second series of data. The multiplexer 121 receives the second serial data from the multiplexers 111 and 112, and sequentially arranges the second serial data generated by the multiplexers 111 and 112 according to the differential clock to generate the serial output data.

FIG. 2A is a block diagram of the clock generator 200. The clock generator 200 can generate a differential clock and a full swing clock to drive the serializer. In one embodiment, the clock generator 200 includes a phase locked loop (PLL) voltage controlled oscillator (VCO) 210 and a differential to single circuit 220. . The phase-locked loop voltage control oscillator 210 generates a differential clock, and the differential-to-single-ended circuit 220 generates a full swing clock based on the differential clock. Figure 2B is a schematic diagram of the differential clock and the full swing clock generated by the clock generator of Figure 2A. When the differential to single-ended circuit 220 generates a full swing clock based on the differential clock, it may introduce the two most extreme process drifts in the full swing clock. When the differential to single-ended circuit 220 causes a slow S-span variation 251, the full swing clock is delayed for a longer period of time. When the differential to single-ended circuit 220 causes a F corner variation 252, the full swing clock is delayed for a shorter period of time. However, whether it is the S process drift or the F process drift, there will be a phase difference between the full swing clock and the differential clock, which leads to the incorporation of the serializer into the shift register and the operation of the multiplexer. Inconsistent, further causing data errors in the serial output data.

Figure 3A is a block diagram of the serializer 300 incorporating the clock generator of Figure 2A. In one embodiment, the serializer 300 includes a plurality of in-line serial shift registers 301-304, a plurality of multiplexers 311, 312, 321, a phase-locked loop voltage controlled oscillator 350, and a differential turn. Single-ended circuit 352. The functions of the in-line shift register 301-304 are the same as those of the in-line shift register 101-104 of FIG. 1, and the functions of the multiplexers 311, 312, and 321 are the same as those of the first figure. The multiplexers 111, 112, and 121 have the same functions. The phase locked loop voltage control oscillator 350 generates a noise free differential clock to drive the operation of the multiplexers 311, 312, 321 . The differential to single-ended circuit 352 generates a full swing clock based on the differential clock, and the full swing clock is used to drive the operation of the incorporation into the serial shift registers 301-304. Since the differential to single-ended circuit 352 causes the S-process drift or the F-process drift between the full swing clock and the differential clock, the full swing clock has a phase difference with the differential clock, resulting in a serializer. The incorporation of the 300-incorporated shift register registers 301-304 is inconsistent with the operation of the multiplexers 311, 312, and 321 to further cause data errors in the serial output data.

Figure 3B is a schematic diagram of data errors generated by the serializer 300 of Figure 3A. The phase locked loop voltage control oscillator 350 produces one of the differential clocks without noise. Then, the differential to single-ended circuit 352 generates a full swing clock according to the differential clock, and there is an S process drift 361 or an F process drift 371 between the full swing clock and the differential clock. If there is an S process drift 361 between the full swing clock and the differential clock, the incorporation of the serial shift register 301~304 then generates the intermediate data 363 according to the driving of the full swing clock, wherein the intermediate data 363 There is a slight delay 362 between the full swing clock and the pulse. When the multiplexers 311, 312 sample the intermediate data according to the driving of the differential clock 364, since the interval in which the differential clock 364 is 1 coincides with the intermediate data 363, no data error occurs. Wherein, the differential clock is 1 system, and the differential clock is in a state of high potential. Conversely, when the differential clock is 0, the differential clock is in a low state.

However, if there is an F process drift 371 between the full swing clock and the differential clock, the incorporation of the serial shift register 301~304 then generates the intermediate data 373 according to the driving of the full swing clock, wherein the middle There is a slight delay 372 between the data 373 and the full swing clock. When the multiplexers 311, 312 sample the intermediate data according to the driving of the differential clock 364, since the interval in which the differential clock 364 is 1 does not coincide with the intermediate data 373, the multiplexers 311, 312 sample the intermediate data. A data error occurs in the process, and this data error is passed to the serial output data of the serializer 300. Since the occurrence of the S process drift and the F process drift is random and cannot be determined in advance, the serializer 300 randomly generates data errors in the serial output data.

In order to avoid the data error of Figure 3B, it is necessary to remove the process drift between the full swing clock and the differential clock to keep the phase of the full swing clock and the differential clock of the drive serializer consistent. . Figure 4A is a block diagram of the serializer 400 with the phase difference between the full swing clock and the differential clock removed. In one embodiment, the serializer 400 includes a plurality of in-line serial shift registers 401-404, a plurality of multiplexers 411, 412, 421, a phase-locked loop voltage controlled oscillator 450, and a differential transfer order. Terminal circuit 452, and current mode logic (CML) buffer 454. The functions of the in-line shift register 401 to 404 are the same as those of the in-line shift register 101 to 104 of FIG. 1, and the functions of the multiplexers 411, 412, and 421 are the same as those of the first figure. The multiplexers 111, 112, and 121 have the same functions. The phase locked loop voltage control oscillator 450 produces a first differential clock without noise. The differential to single-ended circuit 452 then generates a full swing clock based on the first differential clock to drive the operation of the in-line shift registers 401-404. Next, the current mode logic buffer 454 generates a second differential clock according to the full swing clock to drive the operation of the multiplexers 411, 412, and 421. When the differential to single-ended circuit 452 generates a full swing clock according to the first differential clock, the differential to single-ended circuit 452 causes an S-process drift between the full swing clock and the first differential clock. F process drift. When the current mode logic buffer 454 generates the second differential clock according to the full swing clock, the second differential clock also has the S process drift or the F process drift existing in the full swing clock. Therefore, there is no delay or phase difference between the full swing clock and the second differential clock, so that the serializer 400 is incorporated into the serial shift register 401~404 and the multiplexers 411, 412, The operation of 421 is consistent, and the data in the serial output data is avoided.

Figure 4B is a schematic diagram of the data sampling process of the serializer 400 of Figure 4A. The phase locked loop voltage control oscillator 450 produces a first differential clock without noise. Next, the differential to single-ended circuit 452 generates a full swing clock according to the first differential clock, and there is an S process drift 461 or an F process drift 471 between the full swing clock and the first differential clock. If there is an S process drift 461 between the full swing clock and the first differential clock, the in-line serial shift register 401~404 then generates the intermediate data 465 according to the driving of the full swing clock, wherein the middle There is a slight delay 462 between the data 465 and the full swing clock. In addition, the current-type logic buffer 454 generates a second differential clock 464 according to the full-swing clock. Since the process drift of the current-type logic circuit is not obvious, the entire swing clock and the second differential clock are only between There are some micro phase differences 463. When the multiplexers 411, 412 drive the intermediate data 465 according to the driving of the second differential clock 464, since the interval in which the differential clock 464 is 0 coincides with the intermediate data 465, no data error occurs. Similarly, if there is an F process drift 471 between the full swing clock and the first differential clock, the incorporation of the serial shift register 401~404 then generates the intermediate data according to the driving of the full swing clock. There is a slight delay 472 between the intermediate data 475 and the full swing clock. In addition, the current-type logic buffer 454 generates a second differential clock 474 according to the full swing clock, wherein the full swing clock has only a slight phase difference 473 between the second differential clock and the second differential clock. When the multiplexers 411, 412 are driven to sample the intermediate data 475 according to the driving of the second differential clock 474, since the interval in which the differential clock 474 is 0 coincides with the intermediate data 475, no data error occurs.

Although the serializer 400 can avoid data errors caused by the serial output data, the serial output data of the serializer 400 has a large jitter. Since the noise generated by the differential to single-ended circuit 452 in the full swing clock is transmitted to the second differential clock, the multiplexers 411, 412, and 421 are based on the second differential with noise. When the pulse is operated, the serial output data with jitter is generated, which reduces the performance of the serializer 400.

In order to remove the jitter of the serial output data of FIG. 4A while avoiding the occurrence of data errors in FIG. 3B, the present invention proposes a novel state serializer. Figure 5 is a block diagram of a serializer 500 for preventing jitter and data errors of serial output data in accordance with the present invention. The serializer 500 converts a parallel input data into a series of output data. In one embodiment, the serializer 500 includes a plurality of in-line shift register registers 501-504, and a plurality of current mode logic (CML) D-type flip-flops (D filp-flop) 531. 532, 533, 534, a plurality of multiplexers 511, 512, 521, a phase locked loop voltage controlled oscillator 550, and a differential to single circuit 552. The functions incorporated in the serial shift registers 501 to 504 are the same as those incorporated in the serial shift registers 101 to 104 of FIG. The current-type logic D-type flip-flops 531, 532, 533, 534 respectively sample and store the first intermediate data generated by the serial-out shift register 501, 502, 503, 504 according to the differential clock to generate The second intermediate data is used as input to the multiplexers 511, 512. The functions of the multiplexers 511, 512, and 521 are the same as those of the multiplexers 111, 112, and 121 of FIG. The phase-locked loop voltage control oscillator 550 generates a noise-free differential clock to drive the operation of the current-mode logic D-type flip-flops 531, 532, 533, 534 and the multiplexers 511, 512, 521. The differential to single-ended circuit 552 generates a full swing clock based on the differential clock to drive the operation of the in-line shift registers 501-504. In one embodiment, the inline out shift registers 501-504 are 5-to-1 incorporated into the serial shift register. In one embodiment, the multiplexers 511, 512, 521 are 2-to-1 multiplexers.

First, the in-line shift register registers 501-504 receive 5 input bits from the 20 input bits of the parallel input data, and are based on the full swing clock sequence generated by the differential single-ended circuit 552. The five input bits received by each are listed to generate a first intermediate data. Then, the current-type logic D-type flip-flops 531-534 control the noise-free differential clock sampling generated by the oscillator 550 according to the phase-locked loop voltage and store the first generated by the serial shift register 501-504. Intermediate data to generate second intermediate data. Then, the multiplexers 511 and 512 sequentially arrange the second intermediate data generated by the current-type logic D-type flip-flops 531 and 532 according to the non-noise differential clock generated by the oscillator 550 to generate the second intermediate data. The third intermediate information. Then, the multiplexer 521 sequentially controls the third intermediate data generated by the multiplexers 511, 512 according to the phase difference loop voltage control oscillator 550 to generate the serial output data.

Although the differential to single-ended circuit 552 causes an S-process drift or an F-process drift between the full swing clock and the differential clock, the full swing clock has a phase difference with the differential clock. However, since the current-type logic D-type flip-flops 531 and 532 sample the first intermediate data according to the differential clock without noise, the current-type logic D-type flip-flops 531 and 532 are based on the differential clock without noise. The generated second intermediate data has a phase corresponding to the differential clock. Therefore, the multiplexer 511, 512 does not generate a data error when sampling the second intermediate data according to the differential clock, and avoids data error of the serializer 500. The problem. In addition, since the current-type logic D-type flip-flops 531-534 and the multiplexers 511, 512, and 521 are driven by the differential clock without noise, the jitter is not generated in the serial output data. . Since the serializer 500 successfully avoids data error and jitter in the serial output data, the performance of the serializer 500 of FIG. 5 is higher than that of the serializers 300 and 400 of FIGS. 3 and 4 high.

Figure 6 is a schematic diagram of the data sampling process of the serializer 500 of Figure 5. The phase locked loop voltage control oscillator 550 generates a differential clock without noise. Then, the differential to single-ended circuit 552 generates a full swing clock according to the differential clock, and there is an S process drift 611 or an F process drift 621 between the full swing clock and the differential clock. If there is an S process drift 611 between the full swing clock and the differential clock, the in-line jump shift registers 501-504 then generate the first intermediate data 614 according to the driving of the full swing clock, wherein There is a slight delay 612 between an intermediate data 614 and the full swing clock. Next, the current-type logic D-type flip-flops 531-534 sample and store the first intermediate data 614 according to the noise-free differential clock to generate the second intermediate data 615. When the multiplexers 511, 512 sample the second intermediate data 615 according to the driving of the differential clock 616, since the interval in which the differential clock 616 is 0 coincides with the second intermediate data 615, no data error occurs. Similarly, if there is an F process drift 621 between the full swing clock and the differential clock, the merged serial shift registers 501-504 then generate the first intermediate data 624 according to the driving of the full swing clock. There is a slight delay 622 between the first intermediate data 624 and the full swing clock. Next, the current mode logic D-type flip-flops 531, 532, 533, 534 sample and store the first intermediate data 624 according to the noise-free differential clock to generate the second intermediate data 625. When the multiplexers 511, 512 sample the second intermediate data 625 according to the driving of the differential clock 616, since the interval of the differential clock 616 coincides with the second intermediate data 625, no data error occurs.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

(Figure 1)

100. . . Serializer

101,102,103,104. . . 5-to-1 in-line serial shift register

111, 112, 121. . . 2-to-1 multiplexer

(Figure 2A)

200. . . Clock generator

210. . . Phase-locked loop voltage controlled oscillator

220. . . Differential to single-ended circuit

(Figure 3A)

300. . . Serializer

301,302,303,304. . . 5-to-1 in-line serial shift register

311,312,321. . . 2-to-1 multiplexer

350. . . Phase-locked loop voltage controlled oscillator

352. . . Differential to single-ended circuit

(Fig. 4A)

400. . . Serializer

401, 402, 403, 404. . . 5-to-1 in-line serial shift register

411,412,421. . . 2-to-1 multiplexer

450. . . Phase-locked loop voltage controlled oscillator

452. . . Differential to single-ended circuit

454. . . Current mode logic buffer

(Figure 5)

500. . . Serializer

501, 502, 503, 504. . . 5-to-1 in-line serial shift register

531,532,533,534. . . Current-type logic D-type flip-flop

511,512,521. . . 2-to-1 multiplexer

550. . . Phase-locked loop voltage controlled oscillator

552. . . Differential to single-ended circuit

Figure 1 is a block diagram of a general serializer;

Figure 2A is a block diagram of the clock generator;

Figure 2B is a schematic diagram of the differential clock and the full swing clock generated by the clock generator of Figure 2A;

Figure 3A is a block diagram of a serializer incorporating the clock generator of Figure 2A;

Figure 3B is a schematic diagram of data errors generated by the serializer of Figure 3A;

Figure 4A is a block diagram of the serializer with the phase difference between the full swing clock and the differential clock removed;

Figure 4B is a schematic diagram of the data sampling process of the serializer of Figure 4A;

Figure 5 is a block diagram of a serializer for preventing jitter and data errors of serial output data according to the present invention;

Figure 6 is a schematic diagram of the data sampling process of the serializer of Figure 5.

500. . . Serializer

501, 502, 503, 504. . . 5-to-1 in-line serial shift register

531,532,533,534. . . Current-type logic D-type flip-flop

511,512,521. . . 2-to-1 multiplexer

550. . . Phase-locked loop voltage controlled oscillator

552. . . Differential to single-ended circuit

Claims (12)

A serializer converts a parallel input data into a series of output data according to a full swing clock and a differential clock without noise, including: a plurality of a Parallel-input-serial-output shift register (PISO), which receives a plurality of input bits from a plurality of input bits of the parallel input data, and according to the full swing The plurality of input bits are serially generated to generate a plurality of first intermediate data; a plurality of current mode logic (CML) D-type flip-flops (D filp-flop), based on no noise The differential clock respectively locks the first intermediate data to generate a plurality of second intermediate data; and at least one multiplexer receives the second intermediate data and is based on no noise The differential clock interleaves the second intermediate data to generate the serial output data. The serializer of claim 1, wherein the serializer further comprises: a clock generation circuit that generates the differential clock without noise, and derives the full swing according to the differential clock Clock. The serializer according to claim 2, wherein the clock generation circuit comprises: a Phase Locked Loop (PLL) Voltage Controlled Oscillator (VCO), which generates no noise. The differential clock; and a differential to single circuit, the full swing clock is derived according to the differential clock. The serializer of claim 1, wherein the at least one multiplexer comprises: a plurality of first multiplexers respectively receiving a portion of the second intermediate data from the second intermediate materials, and And arranging, according to the differential clock without noise, a portion of the second intermediate data to generate a plurality of third intermediate data; and a second multiplexer sequentially arranging according to the differential clock without noise The third intermediate data is used to generate the serial output data. The serializer of claim 1, wherein the incorporation of the serial shift register is a 5-to-1 incorporation of a serial shift register. The serializer of claim 4, wherein the first multiplexer is a 2-to-1 multiplexer, and the second multiplexer is a 2-to-1 multiplexer. A data serialization method for converting a parallel input data into a series of output data, wherein a serializer includes a plurality of parallel-input-shift shift registers (Parallel-input-serial-output shift register) , PISO), multiple current mode logic (CML) D-type flip-flops (D filp-flop), and at least one multiplexer, the data serialization method includes: incorporating The serial out shift register receives a portion of the input bits from the plurality of input bits of the parallel input data; and the incorporation of the serial shift register is based on a full swing clock (full swing clock) Aligning the partial input bits to generate a plurality of first intermediate data; respectively, locking and storing the current-type logic D-type flip-flops according to a differential clock of one of no noises ( The first intermediate data is generated to generate a plurality of second intermediate data; and the second intermediate data is interleaved by the at least one multiplexer according to the differential clock without noise to generate the serial output data . The data serialization method of claim 7, wherein the serializer further comprises a clock generation circuit, and the method further comprises: generating, by the clock generation circuit, the differential clock without noise; And using the clock generation circuit to derive the full swing clock according to the differential clock. The data serialization method of claim 8, wherein the clock generation circuit comprises: a Phase Locked Loop (PLL) Voltage Controlled Oscillator (VCO), which generates no noise. The differential clock; and a differential to single circuit, the full swing clock is derived according to the differential clock. The data serialization method of claim 7, wherein the at least one multiplexer comprises a plurality of first multiplexers and a second multiplexer, and the step of generating the serial output data comprises: The first multiplexers respectively receive a portion of the second intermediate data from the second intermediate data; and the first multiplexers sequentially arrange the portions according to the differential clocks without noise. The second intermediate data is used to generate a plurality of third intermediate data; and the third intermediate data is sequentially arranged by the second multiplexer according to the differential clock without noise to generate the serial output data. The data serialization method of claim 7, wherein the incorporation of the serial shift register is a 5-to-1 incorporation into the serial shift register. The data serialization method of claim 10, wherein the first multiplexer is a 2-to-1 multiplexer, and the second multiplexer is a 2-to-1 multiplexer.