CN103219365B - high-frequency semiconductor switch - Google Patents
high-frequency semiconductor switch Download PDFInfo
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- CN103219365B CN103219365B CN201210017775.0A CN201210017775A CN103219365B CN 103219365 B CN103219365 B CN 103219365B CN 201210017775 A CN201210017775 A CN 201210017775A CN 103219365 B CN103219365 B CN 103219365B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 14
- 238000003780 insertion Methods 0.000 abstract description 10
- 230000037431 insertion Effects 0.000 abstract description 10
- 238000009826 distribution Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The object of the invention is for providing the high-frequency semiconductor switch forming good voltage's distribiuting on gate line and improve insertion loss characteristic and harmonic characterisitic。The field-effect transistor of the present invention is as the field-effect transistor (50) of high-frequency semiconductor switch being included in for radio communication switching, including source electrode line (60)；Drain line (70)；There is the grid (120) of the parallel portion (122) extended substantially in parallel with source electrode line (60) and drain line (70) between source electrode line (60) and drain line (70)；For executing alive gate line (80) to grid (120)；The gate vias (82) of electrical connection grid (120) and gate line (80)。And parallel portion (122) has two ends (126), and forms the applying path of voltage respectively from gate vias (82) to two ends (126)。
Description
Technical field
The present invention relates to high-frequency semiconductor switch, particularly relate to the high-frequency semiconductor switch being used on Wireless Telecom Equipment。
Background technology
The front end of the Wireless Telecom Equipment such as portable phone or PC uses high-frequency semiconductor switch。The path sending signal that high-frequency semiconductor switch switching transmission is sent from the path receiving signal that antenna receives and transmission by antenna。In order to switch, high-frequency semiconductor switch includes multiple FET (field-effect transistor: FieldEffectTransistor)。
FET is connected to input and sends in the receiving terminal sending terminal or output reception signal of signal。When sending signal, voltage is applied on the grid being connected to the FET sent on terminal, and when receiving signal, voltage is applied on the grid of the FET being connected to receiving terminal, thus forming signal transmission path。
The FET of existing comb shape be known (such as, referenced patent file 1), the transistor overlooking comb shape is visible, and the source electrode line being connected on source region and the drain line being connected to drain region form comb shape respectively, and the ctenii of comb shape (teeth) is configured to left and right alternately occlusion。Grid is again formed as comb shape, and source electrode line or drain line and ctenii (teeth) configured in parallel。
Patent documentation 1: flat No. 11-103072 of Japanese Laid-Open Patent Publication
But, in the grid of comb shape as above, the ctenii part of comb shape can extend to and source region or drain region equal length or length above。At this moment, the resistance components of the grid owing to extending causes voltage drop, therefore can not obtain good voltage's distribiuting。Thus insertion loss characteristic and harmonic characterisitic deterioration will be made。
Summary of the invention
The present invention is used for solving the problems referred to above point, its object is to form good voltage's distribiuting on gate line, thus improve the high-frequency semiconductor switch of insertion loss characteristic and harmonic characterisitic。
For the field-effect transistor switched included by the high-frequency semiconductor switch of radio communication, there is source electrode line, drain line, grid, gate line, gate vias (via)。Source electrode line is connected electrically in the source region being formed on substrate, and extends to a direction。Drain line is connected electrically in the drain region being formed on substrate, and extends substantially in parallel with source electrode line。Grid has the parallel portion extended substantially in parallel between source electrode line and drain line with source electrode line and drain line。Grid alignment grid applies voltage。Gate vias makes grid electrically connect with gate line。Parallel portion has two ends, and forms the applying path of voltage respectively from gate vias to two ends。
According to said structure, forming two ends in parallel portion, therefore executing alive path from gate vias will be divided。Thus, along with path shortens the voltage drop that correspondingly can reduce owing to path causes, therefore can so that the voltage's distribiuting of grid be more uniform。
Thus, insertion loss characteristic and harmonic characterisitic can be improved。
Accompanying drawing explanation
Fig. 1 is an example of the brief circuit structure of high-frequency semiconductor switch。
Fig. 2 is the grid of the FET that switch includes。
Fig. 3 indicates that the top view being positioned at the area of grid of distribution bottom, source region and drain region。
Fig. 4 is the 4-4 profile of Fig. 2。
Fig. 5 is the 5-5 profile of Fig. 2。
Fig. 6 is the 6-6 profile of Fig. 2。
Fig. 7 is the 7-7 profile of Fig. 2。
Fig. 8 is the top view of the distribution illustrating way of contrast。
The grid of the FET that Fig. 9 is included in the high-frequency semiconductor switch of the second embodiment。
Figure 10 is in the grid of the bottom of distribution。
Figure 11 is the schematic cross sectional view carrying out the FET cut along the 11-11 line of Fig. 9。
Detailed description of the invention
Below, with reference to accompanying drawing, embodiments of the present invention are illustrated。As reference, give same symbol to same key element in the description of the drawings and omit repeat specification。For the ease of illustrating to be exaggerated the dimension scale of accompanying drawing, thus have the situation different from actual ratio。Further, in explanation " formed and exist ... on " statement, not only include the situation that directly contact is formed, also include the situation that the material by other indirectly forms。" substantially " in description refers to foozle, manufactures precision。Such as, " substantially " parallel also include due to foozle, manufacture precision and cannot completely parallel situation。
(the first embodiment)
Fig. 1 is an example of the brief circuit structure of high-frequency semiconductor switch。
As it is shown in figure 1, high-frequency semiconductor switch 10 includes 4 tandem taps (20a～20d)。Tandem tap (20a～20d) is arranged between antenna terminal 30 and RF terminal (40a～40d)。Tandem tap (20a～20d) at least includes a field-effect transistor (hereinafter referred to as FET) respectively。The multiple FET being included in same tandem tap (20a～20d) can be applied in voltage at grid as shown in the figure simultaneously。Thus, each tandem tap (20a～20d) can switch the voltage being applied to grid, such that it is able to the conducting controlled between antenna terminal 30 and RF terminal (40a～40d)。Further, FET is also applied with voltage in base stage。
In example shown in FIG, in RF terminal (40a～40d), RF terminal (40a～40b) is receiving terminal RX for sending terminal TX, RF terminal (40c～40d)。Transmission/receiving terminal is the terminal of such as different frequency for Frequency Division Multiplex communication mode, or the terminal for switching in each appointment time for time multiplex communication mode。
Such as, along with tandem tap 20a (ON) switched on, other tandem tap (20c, 20d) is cut off (OFF), the transmission of 900MHz frequency can be realized, along with tandem tap 20c is by ON, tandem tap (20a, 20b, 20d) is by OFF, it is possible to achieve the reception of 900MHz frequency。The quantity of tandem tap 20 and RF terminal 40 can carry out suitable increase and decrease according to transmission/reception mode or required multiformity。
Secondly, in the multiple FET50 included by tandem tap (20a～20d), the structure of one of them FET is illustrated。
Fig. 2 is the schematic plan view illustrating the gate line of FET included by switching, source electrode line and drain line, and Fig. 3 is the top view being shown at the area of grid of distribution bottom, source region and drain region。Fig. 2 illustrates the distribution of the FET50a such as irised out in FIG by circular dashed line。Fig. 3 illustrates that formation is in the area of grid of the bottom of Fig. 2 distribution, source region and drain region。
As in figure 2 it is shown, FET50a is provided with source electrode line 60, drain line 70, gate line 80 and base line 90。
Source electrode line 60 and drain line 70 form comb shape respectively。Trunk (stem) part 62 that source electrode line 60 has comb shape and the ctenii part 64 extended to the direction (direction) being substantially orthogonal with torso portion 62。Ctenii part 64 is formed path 66。Source electrode line 60 is connected on the source region 100 that figure 3 illustrates by path 66。Source region 100 is formed on substrate, and as it is shown on figure 3, is divided in the both sides of grid 120。But, owing to the ctenii part 64 of source electrode line 60 connects on top, therefore voltage can be applied to the both sides of divided source region 100 from source electrode line 60。
The formation of drain line 70 is also similar with source electrode line 60。Torso portion 72 that drain line 70 has comb shape and the ctenii part 74 extended to the direction (direction) being substantially orthogonal with torso portion 72。Ctenii part 74 is formed path 76。Drain line 70 is connected on the drain region 110 that figure 3 illustrates by path 76。Drain region 110 is formed on substrate, and is divided in the both sides of grid 120 as shown in Figure 3。But, owing to the ctenii part 74 of drain line 70 connects on top, therefore voltage can be applied to the both sides of divided drain region 110 from drain line 70。
Gate line 80, between the torso portion 62 of source electrode line 60 and the torso portion 72 of drain line 70, overlooks visible being substantially orthogonal with ctenii part 64, ctenii part 74, almost parallel with torso portion 62, torso portion 72。Preferred gate line 80 is positioned at the substantial middle of torso portion 62, torso portion 72。Gate line 80 is formed path (gate vias) 82。Gate line 80 is connected on the grid 120 that figure 3 illustrates by path 82。
As it is shown on figure 3, grid 120 has parallel portion 122 that the ctenii part 74 of the ctenii part 64 with source electrode line 60 and drain line 70 extends substantially in parallel and one formed at same layer quadrature component 124 that is orthogonal with parallel portion 122 and that extend with parallel portion 122。Parallel portion 122 has two ends 126, and extends from a quadrature component 124 to both sides。Path 82 is positioned on quadrature component 124, and is positioned away from the position of the intersection point of parallel portion 122 and quadrature component 124。
The quadrature component 124 of base line 90 and grid 120 is formed as two in the both sides of grid 120, source region 100 and drain region 110 substantially in parallel。Base line 90 is formed path (base stage path) 92。Base line 90 is connected electrically on the base region of SOI substrate described later by path 92。Base region is formed below grid 120。Path 92 is such as arranged on the both sides of the parallel portion 122 of grid 120 shown in Fig. 3。Voltage is applied to base region by path 92。
Secondly, for above-mentioned distribution, region, path three-dimensional position relation reference section figure illustrate。
Fig. 4 is the profile obtained along the 4-4 line cutting of Fig. 2, Fig. 5 is the profile obtained along the 5-5 line cutting of Fig. 2, Fig. 6 is the profile obtained along the 6-6 line cutting of Fig. 2, Fig. 7 is the profile obtained along the 7-7 line cutting of Fig. 2, it should be noted that eliminate diagram for a part of interlayer dielectric in Fig. 4 to Fig. 7。
As shown in Fig. 4 to Fig. 7, FET50 is formed in SOI substrate。Arbitrary conductivity type (such as P type) silicon substrate 130 is formed the dielectric film 140 of silicon oxide。Semiconductor layer 150 on dielectric film 140 is formed conductivity type (such as N-type) source region 100 different from substrate and drain region 110。On base region 150 between source region 100 and drain region 110, it is formed with grid 120 across oxide-film 160。
Grid 120 is formed by polysilicon layer。As shown in Fig. 4, Fig. 7, gate line 80 forms the top at grid 120, and is electrically connected with grid 120 by path 82。Path 82 can be formed by flowing into metal material in the via hole carrying out opening on interlayer dielectric and produce。
The top of grid 120 is formed with source electrode line 60 and drain line 70, and does not contact with grid 120。Source electrode line 60 and drain line 70 are respectively electrically connected on source region 100 and drain region 110 by path 66, path 76 as shown in Figure 5。Path 66, path 76 can be formed by flowing into metal material in the via hole carrying out opening on interlayer dielectric and produce。
As shown in Figure 6, base line 90 is formed above the both sides of grid 120。The path 92 being connected to base line 90 is connected with base region 150。As it is shown in fig. 7, base line 90 is formed at the height identical with gate line 80。
As it is shown in fig. 7, source electrode line 60 can cover gate line 80 and grid 120。Source electrode line 60 applies voltage by path 66 to the source region 100 split by the base region 150 of grid 120 bottom。
Below, comparative illustration is carried out with the manner of comparison being used for carrying out contrasting with the present invention。
Fig. 8 is the top view of the distribution illustrating way of contrast。
As shown in Figure 8, in manner of comparison, source electrode line 160, drain line 170, gate line 180 are respectively formed as comb shape。Therefore, voltage drop can be there is corresponding to starting the distance Lp to the end 222 of grid 220 from the gate vias 182 being arranged on gate line 180, thus causing that voltage's distribiuting is bad。Thus the deterioration of insertion loss characteristic and harmonic characterisitic can be caused。
On the other hand, gate line 80 is formed between source electrode line 60 and drain line 70 in the present embodiment as shown in Figure 2, and gate line 80 is provided with path 82。And the parallel portion 122 of grid 120 is formed two ends 126。Thus, the distance L two ends from path 82 to grid 120 shortens than the distance Lp of Fig. 8。In other words, because being formed with two ends 126 in the parallel portion 122 of grid 120, therefore not one from path 82 to the path of end 126 but two can be divided into, and respective distance also can shorten。The shortening voltage drop of respective distances is as well as minimizing, and therefore the voltage's distribiuting on grid 120 can become impartial。Because the voltage at grid 120 becomes impartial, the inversion layer therefore formed on base region 150 also can become impartial, and can improve insertion loss characteristic。Meanwhile, if the voltage's distribiuting at grid 120 becomes impartial, then because there is no the distortion of signal, harmonic characterisitic can also therefore be improved。
Particularly, when gate line 80 is arranged in source electrode line 60 and drain line 70 central, symmetrical, and the only about half of of distance Lp can be become from the path 82 distance to the end 126 of grid 120。Thus, the voltage's distribiuting that can make grid 120 is more impartial, therefore can improve insertion loss characteristic and harmonic characterisitic。
Further, in the manner of comparison that figure 8 illustrates, base line 190 is one and is formed in side。Execute alive base region from base line 190 to be formed below grid 220。Thus, from path 192, the distance to the end of base region will become substantially identical with grid 120 distance Lp。Voltage to base region applying also can be generally corresponding to the voltage drop of the length of distance Lp。In manner of comparison, the voltage's distribiuting at base region also can become bad, thus the deterioration of insertion loss characteristic and harmonic characterisitic will be caused。
On the other hand, base line 90 is formed in left and right in the present embodiment as shown in Figure 2。The base region 150 of grid 120 bottom applies voltage from the path 92 of both sides (left and right accompanying drawing), and therefore the about half that distance is distance Lp of voltage drop occurs。From result, contrast manner of comparison can improve insertion loss characteristic and harmonic characterisitic。
(the second embodiment)
Fig. 9 is the schematic top illustrating the gate line of FET in the high-frequency semiconductor switch being included in the second embodiment, source electrode line and drain line, Figure 10 is the top view of the area of grid of the bottom being shown at distribution, source region and drain region, and Figure 11 is the schematic cross sectional view of the FET cut along the 11-11 line of Fig. 9。The reference marks that the structure mark identical with the first embodiment is identical, and the description thereof will be omitted。
Including the FET50 in the high-frequency semiconductor switch of the second embodiment, its source electrode line 260 and drain line 270 and the first embodiment are identically formed comb shape。Source electrode line 260 and drain line 270 are respectively provided with torso portion 262, torso portion 272, ctenii part 264, ctenii part 274 and path 266, path 276。As it is shown in figure 9, gate line 280 be parallel to the torso portion 262 of source electrode line 260 and drain line 270, torso portion 272 and both sides formed two。
Extend two gate lines 280 along the direction orthogonal with the direction (direction) that the ctenii part 264 of source electrode line 260 and drain line 270, ctenii part 274 extend, and formed across grid 320 (parallel portion)。Grid 320 is divided into two on said one direction, and starts extend and make close to each other from each gate line 280。Two end 322 of grid 320 is positioned at the both sides of base line 290。
Gate line 280 has gate vias 282, and is connected electrically on grid 320 by path 282。Path 282 is arranged on the intersection point of gate line 280 and grid 320。
Base line 290 is almost parallel with gate line 280, and vertical view is formed between divided grid 320 as seen。Base line 290 is overlooked visible in central authorities' extension so that also pass through between divided source region 300 and drain region 310。Base line 290 has base stage path 292, and as shown in figure 11, is connected on the base region 350 being formed in SOI substrate。Voltage is applied from base line 290 to base region by base stage 292。
In the FET50 of the second embodiment of said structure, grid 320 is divided into two in a direction, and extends to respective central authorities。Because grid 320 is divided, therefore compares with the mode that figure 8 illustrates from the path 282 distance to the end 322 of grid 320 and be about its half。Correspondence executes the shortening of alive distance, and voltage drop will reduce, therefore can so that the voltage's distribiuting of grid 320 is uniform。
Further, because base line 290 is formed in central authorities, therefore from path 292, distance to the end of base region 350 compares with the mode shown in Fig. 8 and is about its half。Corresponding to executing the shortening of alive distance, voltage drop will reduce, therefore can so that the voltage's distribiuting of base region 350 is uniform。Even if as it has been described above, manner of comparison compared to Fig. 8 in this second embodiment, the voltage's distribiuting of FET50 is more uniformly distributed, such that it is able to improve insertion loss characteristic and harmonic characterisitic。
Gate line visible be arranged in central authorities to overlooking and base line is arranged in the mode of both sides is illustrated by this specification as the first embodiment, and as the second embodiment, base line is arranged in central authorities and gate line is arranged in the mode of both sides is illustrated。This configuration relation only need to be met when the present invention overlooks。For gate line, source electrode line, drain line, base line high and low position relation, it is possible to be designed change。Such as, in the first embodiment, it is possible to base line 90 is formed in the position higher than source electrode line 60 and drain line 70。
And, although it is that the situation of comb shape is illustrated to source electrode line 60, source electrode line 260 and drain line 70, drain line 270, but is not limited to this。Even if not being comb shape, as long as at least extending to the direction of a position。Such as, it is possible to using a ctenii part 64 as the source electrode line 60 extended to direction, and using a ctenii part 74 as the drain line 70 extended substantially in parallel with source electrode line 60。
Symbol description
10: high-frequency semiconductor switch 20a～20d: tandem tap
30: antenna terminal 40a～40d:RF terminal
50:FET60,260: source electrode line
62,262: torso portion 64,264: ctenii part
66,76,82,92,282,292: path 70,270: drain line
72: torso portion 74: ctenii part
80,280: gate line 90,290: base line
100,300: source region 110,310: drain region
120,220,320: grid 122: parallel portion
124: quadrature component 126,322: end
130: silicon substrate 140: dielectric film
150,350: base region 160: oxide-film
Claims (6)
1. a field-effect transistor, described field-effect transistor comprises the high-frequency semiconductor switch for carrying out radio communication switching, including:
Source electrode line, described source electrode line electrically connects with the source region formed on substrate, and extends to a direction；
Drain line, described drain line electrically connects with the drain region formed on substrate, and extends parallel to described source electrode line；
Grid, described grid has the parallel portion extended parallel between described source electrode line and described drain line with described source electrode line and described drain line；
Gate line, for applying voltage to described grid；And
Gate vias, described gate vias makes described grid and the electrical connection of described gate line,
And described parallel portion has two ends, and forms voltage applying path respectively from described gate vias to said two end,
Wherein, said two end is respectively further from gate vias。
2. field-effect transistor according to claim 1, it is characterised in that
Described grid is formed at same layer with described parallel portion, and also has quadrature component that is orthogonal with described parallel portion and that extend,
And described path is arranged on described quadrature component。
3. field-effect transistor according to claim 2, it is characterised in that
Form a described quadrature component,
Described parallel portion extends from described quadrature component to both sides。
4. field-effect transistor according to claim 3, it is characterised in that also include:
Base region, described base region is formed on the substrate and is positioned at the bottom of described grid；
Base line, for applying voltage to described base region；
Base stage path, described base stage path makes described base region and the electrical connection of described base line,
And described base line and described quadrature component are formed parallel in the both sides of described grid。
5. field-effect transistor according to claim 1, it is characterised in that
Along direction extension two the described gate lines orthogonal with a direction, and formed across described parallel portion,
And described parallel portion is divided into two and starts to extend from each gate line so that close to each other。
6. field-effect transistor according to claim 5, it is characterised in that also include:
Base region, described base region is formed on the substrate and is positioned at the bottom of described grid；
Base line, for applying voltage to described base region；
Base stage path, described base stage path makes described base region and the electrical connection of described base line,
Described base line and described gate line are formed parallel between divided described parallel portion。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210017775.0A CN103219365B (en) | 2012-01-19 | 2012-01-19 | high-frequency semiconductor switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210017775.0A CN103219365B (en) | 2012-01-19 | 2012-01-19 | high-frequency semiconductor switch |
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| Publication Number | Publication Date |
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| CN103219365A CN103219365A (en) | 2013-07-24 |
| CN103219365B true CN103219365B (en) | 2016-06-22 |
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| CN201210017775.0A Expired - Fee Related CN103219365B (en) | 2012-01-19 | 2012-01-19 | high-frequency semiconductor switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6674108B2 (en) * | 2000-12-20 | 2004-01-06 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| US7005708B2 (en) * | 2001-06-14 | 2006-02-28 | Sarnoff Corporation | Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling |
| GB0416174D0 (en) * | 2004-07-20 | 2004-08-18 | Koninkl Philips Electronics Nv | Insulated gate field effect transistors |
| JP5237842B2 (en) * | 2009-01-29 | 2013-07-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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