CN103219333A - Enhancement type Flash chip, encapsulating method and instruction execution method - Google Patents

Abstract

The invention provides an enhancement type Flash chip, an encapsulating method and an instruction execution method. The enhancement type Flash chip comprises a plurality of FLASHs encapsulated together and an RPMC (Replay Protection Monotonic Counter), wherein each FLASH and the PRMC respectively comprises respective independent controller, the same IO pin and internal IO pin; the same IO pins in the FLASHs and the PRMC are connected with the same external sharing pin of the chip, or the FLASH and the PRMC comprise a plurality of same IO pins together which are connected with each other and are connected with the same external sharing pin of the chip; and the FLASH and the PRMC comprise a plurality of internal IO pins connected with each other. The problems of nonexpendable Flash volume, high complexity of chip design, long design period and high design cost can be solved.

Description

Enhancement mode Flash chip, method for packing and instruction executing method

Technical field

The present invention relates to the chip technology field, particularly relate to a kind of enhancement mode Flash chip, a kind of method for packing and a kind of instruction executing method.

Background technology

Contain and reply the dull calculator of protection (Replay Protection Monotonic Counter; RPMC) enhancement mode FLASH is that Intel is with basic input output system (the Basic Input-Output System that promotes mainly; BIOS) chip, it comprises a jumbo Flash chip and RPMC circuit.Wherein, the Flash chip is used for storing code and the data of CPU BIOS, and capacity is 8M, 16M, 32M, 64M, 128M, 256M or higher; The RPMC circuit is used to protect the confidentiality and integrity that reads and writes data.The RPMC circuit has constituted the hardware platform of BIOS in the PC system with its integrated Flash chip.

Present RPMC chip is integrated in big capacity Flash chip and RPMC circuit on the chip (die), and RPMC circuit and Flash chip design together, and there is following shortcoming in this RPMC chip:

1, the capacity of integrated back Flash can not be expanded;

2, owing to Flash and RPMC need be integrated on the chip, so the area of monolithic chip is big, package area is big, causes design cost higher;

3, the design cycle long, the reuse of chip is poor;

4, chip can only be carried out a kind of operation at synchronization, causes chip functions limited.

Summary of the invention

The invention provides a kind of enhancement mode Flash chip, a kind of method for packing and a kind of instruction executing method, with the capacity that solves Flash can not expand, chip design complexity height, the design cycle is long, design cost is high problem.

In order to address the above problem, the invention discloses a kind of enhancement mode Flash chip, comprising:

The a plurality of FLASH that are packaged together and one reply protection monotone counter RPMC; Wherein,

Each FLASH comprises separately independently controller, identical IO pin and inner IO pin respectively with described RPMC;

Described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, or a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip;

External command is transferred among described FLASH and the described RPMC by the outside shared pins of described chip, and the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively;

The a plurality of inner IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and the inside IO pin by interconnection intercoms mutually to carrying out inside between described FLASH and the described RPMC or between each FLASH.

Preferably, when described chip receives first external command by outside shared pins, if being judged as described first external command, the controller of RPMC need RPMC to carry out, and each FLASH controller is judged as described first external command needs all or part of FLASH to carry out, and then RPMC and each FLASH all carry out corresponding operating according to described first external command;

If only need part FLASH to carry out described first external command, or only need RPMC to carry out described first external command, then described FLASH or described RPMC carry out corresponding operating according to described first external command.

Preferably, if only need whole FLASH to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at whole FLASH, if described chip receives second external command by outside shared pins, and only need RPMC to carry out, then RPMC carries out corresponding operating according to described second external command;

If only need part FLASH to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at part FLASH, if described chip receives second external command by outside shared pins, and only need other FLASH and/or RPMC to carry out, then other FLASH or RPMC carry out corresponding operating according to described second external command;

If only need part FLASH and RPMC to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at part FLASH and RPMC, if described chip receives second external command by outside shared pins, and only need other FLASH to carry out, then other FLASH carries out corresponding operating according to described second external command;

If only need RPMC to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at RPMC, if described chip receives second external command by outside shared pins, and only need part or all of FLASH to carry out, then described FLASH carries out corresponding operating according to described second external command.

Preferably, described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, comprising:

The IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip, and the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip;

The a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip, comprising:

Identical IO pin b_y interconnection among the IO pin a_x of described FLASH and the described RPMC, and the IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip, perhaps, the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip;

Wherein, described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging.

Preferably, when part FLASH is carrying out external command, and when other FLASH and described RPMC are idle, if described chip receives by outside shared pins and hangs up instruction, the controller of then carrying out the FLASH of external command is judged as needs FLASH to carry out described hang-up instruction, and the controller of other FLASH and the controller of RPMC are judged as does not need RPMC to carry out described hang-up instruction;

After the operation that the FLASH that is carrying out external command is carrying out according to described hang-up instruction suspends, inside other FLASH of IO pin subtend and described RPMC by described interconnection send the notification message that FLASH has hung up, after other FLASH and described RPMC receive described notification message, by carrying out the synchronous of described hang-up instruction each FLASH of realization and described RPMC.

Preferably, the inside IO pin of described interconnection is to being a plurality of;

The outside shared pins of described chip is a plurality of.

Preferably, each FLASH also comprises the independent IO pin of the realization FLASH function that links to each other with FLASH, and the described independent IO pin that links to each other with FLASH is connected on the outside individual pin of described chip;

Described RPMC also comprises the independent IO pin of the realization RPMC function that links to each other with RPMC, and the described independent IO pin that links to each other with RPMC is connected on the other outside individual pin of described chip;

Wherein, the described independent IO pin that links to each other with FLASH does not link to each other mutually with the independent IO pin that links to each other with described RPMC.

The invention also discloses a kind of method for packing, comprising:

Protect monotone counter RPMC to be placed on the chip carrier with replying a plurality of FLASH of needs encapsulation, described FLASH and described RPMC are separate;

All adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, or adopt metal lead wire to interconnect in twos a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC, adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the interconnection;

Adopt metal lead wire to interconnect in twos a plurality of inner IO pin that comprises altogether among described FLASH and the described RPMC;

With a plurality of FLASH, described RPMC and described chip carrier plastic packaging is the enhancement mode Flash chip with RPMC function.

Preferably, described method also comprises:

Adopt metal lead wire to be connected on the outside individual pin of described chip carrier the independent IO pin of realizing the FLASH function among each FLASH;

Adopt metal lead wire to be connected on the other outside individual pin of described chip carrier the independent IO pin of realizing the RPMC function among the described RPMC;

Wherein, the independent IO pin among the described FLASH does not link to each other mutually with independent IO pin among the described RPMC.

Preferably, all adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, comprising:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip the IO pin a_x of described FLASH, and the identical IO pin b_y among the described RPMC adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip;

Adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the described interconnection, comprising:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the IO pin a_x of described FLASH, perhaps, adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the identical IO pin b_y among the described RPMC;

Described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging.

Preferably, the described FLASH that encapsulates that will need protects monotone counter RPMC to be placed on the chip carrier with replying, and comprising:

A plurality of FLASH and described RPMC are all placed side by side on chip carrier, perhaps, with a FLASH and described RPMC vertical pile on chip carrier, and with placed side by side on chip carrier after other FLASH vertical pile with described RPMC, perhaps, a plurality of FLASH and described RPMC vertical pile are on chip carrier;

When described FLASH and described RPMC vertical pile are on chip carrier:

If the area of described FLASH is greater than the area of described RPMC, then described RPMC vertical pile is on described FLASH;

If the area of described RPMC is greater than the area of described FLASH, then described FLASH vertical pile is on described RPMC;

When a plurality of FLASH vertical pile are on chip carrier, with the little FLASH vertical pile of area on the big FLASH of area.

The invention also discloses a kind of instruction executing method, be packaged with a plurality of FLASH and one in the described chip and reply protection monotone counter RPMC, described method comprises:

Receive first external command;

By each FLASH and RPMC separately independently controller judge whether to carry out described first external command respectively;

If being judged as needs RPMC and all or part of FLASH to carry out described first external command, then carry out corresponding operating according to described first external command by RPMC and each FLASH;

If being judged as only needs part FLASH to carry out described first external command, or only needs RPMC to carry out described first external command, then carry out corresponding operating according to described first external command by described FLASH or described RPMC.

Preferably, described method also comprises:

Receive second external command;

If have idle FLASH or RPMC, and idle FLASH or RPMC judge and need to carry out described second external command that then the FLASH of described free time or RPMC carry out corresponding operating according to described second external command.

Preferably, described method also comprises:

Receive and hang up instruction;

The FLASH and/or the RPMC that are carrying out described first external command carry out described hang-up instruction, and send the notification message of having hung up to FLASH and/or the RPMC of free time;

After idle FLASH and/or RPMC receive notification message, carry out described hang-up instruction.

Compared with prior art, the present invention includes following advantage:

1, the enhancement mode Flash chip with RPMC function that the embodiment of the invention proposed is that a plurality of FLASH and a RPMC are packaged together; Wherein, each FLASH circuit comprises separately independently controller, identical IO pin and inner IO pin respectively with described RPMC circuit; Described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, or a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip; External command is transferred among FLASH and the RPMC by the outside shared pins of described chip, and the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively; The a plurality of identical inner IO pins that comprise altogether among described FLASH and the described RPMC interconnect in twos, and the inside IO pin by interconnection intercoms mutually to carrying out inside between described FLASH and the described RPMC or between each FLASH.In the embodiment of the invention, because a plurality of FLASH and RPMC are packaged together, can be according to real needs, select a plurality of Flash chips of different capabilities, different process, satisfied demand, avoided the secondary development of Flash, reduced design cost and production cost the Flash capacity extension; And the FLASH circuit module can reuse existing FLASH chip, and the designer only need design the RPMC circuit module and get final product, and therefore, the chip design complexity is low, the design cycle is short, cost is low; And can reduce package area, reduce cost.

2, each FLASH can carry out different instructions simultaneously, and FLASH also can carry out different instructions simultaneously with RPMC, and promptly FLASH and RPMC can concurrent workings, and different FLASH also can concurrent working, therefore, has improved the performance of chip.

3, between a plurality of FLASH, and can intercom mutually to carrying out inside by the inside IO pin of interconnection between FLASH and the RPMC.Therefore, in FLASH and RPMC at least one carried out external command, and when other FLASH and/or RPMC are idle, if receive the hang-up instruction by outside shared pins, the FLASH and/or the RPMC that are then carrying out external command carry out described hang-up instruction, and the FLASH of free time and/or the RPMC of inside IO pin subtend free time that can be by interconnection send the notice of having hung up, make idle FLASH and/or RPMC also carry out described hang-up instruction, thus can guarantee FLASH and RPMC synchronously.

4, multicore sheet encapsulation can be the FLASH of different process and RPMC encapsulation together, thereby can multiplexing existing resources, reduces development cost.

Description of drawings

Fig. 1 is the logic connection diagram of the embodiment of the invention two described a kind of enhancement mode Flash chips;

Fig. 2 is the encapsulation schematic diagram of the embodiment of the invention two described a kind of enhancement mode Flash chips;

Fig. 3 is the flow chart of the embodiment of the invention three described a kind of method for packing;

Fig. 4 is the flow chart of the embodiment of the invention four described a kind of instruction executing methods.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.

The embodiment of the invention has proposed a kind of chip that utilizes multicore sheet method for packing to realize the RPMC function, RPMC is encapsulated with a plurality of FLASH chips, thereby form an enhancement mode Flash chip with RPMC function, RPMC and each FLASH can share unified pin.Can select a plurality of Flash chips of different capabilities, different process according to real needs by the embodiment of the invention, satisfied demand to the Flash capacity extension, avoid the secondary development of Flash, the design complexities and the design cost of chip have been reduced, and, can intercom mutually to carrying out inside by the inside IO pin of interconnection between RPMC and the FLASH, thus the synchronism of assurance RPMC and FLASH.

Embodiment one:

The embodiment of the invention one has proposed a kind of enhancement mode Flash chip, and described chip can comprise: a plurality of FLASH that are packaged together and one reply protection monotone counter RPMC.

In the embodiment of the invention, each FLASH and RPMC can be chips independently separately.FLASH can select different capacity, different technology according to actual demand.Therefore the FLASH chip that this FLASH can multiplexingly design needn't redesign, and has significantly reduced the construction cycle; RPMC has possessed the function of the dull counting of the protection of replying, and also can use separately.

In the enhancement mode Flash chip with RPMC function that the embodiment of the invention proposes, each FLASH and described RPMC can comprise separately independently controller respectively.For the instruction that send the outside, each FLASH and RPMC can by separately independently controller control each FLASH and RPMC receives respectively, deciphers, after successfully decoded, carry out operation accordingly.

In addition, can have identical IO pin among each FLASH and the RPMC, these identical IO pins are connected to same outside shared pins, and external command is transferred among each FLASH and the RPMC by outside shared pins.

The connected mode of identical IO pin can all be connected on the same outside shared pins of described chip with identical IO pin among the described RPMC for, described FLASH.

The connected mode of identical IO pin also can interconnect in twos for a plurality of identical IO pin that comprises altogether among, described FLASH and the described RPMC, and is connected on the same outside shared pins of described chip.Because the chip of the embodiment of the invention includes a plurality of FLASH, identical IO pin interconnects in twos, can be the interconnection between FLASH and the FLASH, also can be the interconnection of FLASH and RPMC.

Particularly, in the time of a plurality of FLASH and RPMC need being connected to same outside shared pins, whole identical IO pins can be directly connected on the outside shared pins, also can be with each FLASH with after RPMC links to each other in twos, getting one of them is connected on the outside shared pins, also can be that a plurality of FLASH and RPMC are divided into many groups, every group links to each other in twos, and the identical IO pin with FLASH in every group or RPMC is connected on the outside shared pins then.

Wherein, RPMC can not link to each other with any one FLASH, but is directly connected on the outside shared pins, and this moment, FLASH can all be directly connected on the outside shared pins, was connected on the outside shared pins after also can linking to each other in twos.

For example, chip comprises three FLASH and a RPMC, when identical IO pin among each FLASH and the RPMC is connected to same outside shared pins, the identical IO pin of each FLASH can be connected to same outside shared pins, RPMC also is connected on this outside shared pins; Also three FLASH can be linked to each other in twos with a RPMC, again with one of them FLASH or RPMC is connected on the outside shared pins; Also the identical IO pin of two FLASH wherein can be linked to each other, identical IO pin with a FLASH among two FLASH after the connection is connected on the outside shared pins, simultaneously, another FLASH is linked to each other with the identical IO pin of RPMC, then the identical IO pin of this FLASH or the identical IO pin of RPMC are connected on the same outside shared pins.

In the embodiment of the invention, FLASH can refer to the IO pin that function is identical with identical IO pin among the RPMC, for example, IO pin CE among the FLASH can realize that (the IO pin CSE among the RPMC also can realize the function of S PI interface to Serial Peripheral Interface (SPI) for Serial Peripheral Interface, the SPI) function of interface, at this moment, IO pin CE among the FLASH promptly can be identical IO pin with IO pin CSE among the RPMC, therefore, and can be with these two pin CE and CSE interconnection.External command can be transferred to by the outside shared pins of described chip among each FLASH and the described RPMC, judge whether to carry out described external command respectively by the controller of FLASH and the controller of RPMC then, and control FLASH and RPMC execution corresponding operating according to the result who judges.

In the embodiment of the invention, described FLASH and described RPMC can also comprise inside IO pin separately, the a plurality of inner IO pin that comprises altogether among the inside IO pin of described FLASH and the described RPMC interconnects in twos, can intercom mutually to carrying out inside by the inside IO pin of interconnection between described FLASH and the described RPMC or between each FLASH, thereby can guarantee the synchronism of FLASH and RPMC.

For the interconnection of a plurality of inner IO pin that is comprised of FLASH and RPMC, can be will be among FLASH and the RPMC inside IO pin interconnection of the same mode bit of expression.

For example, inside IO pin IO_0 among the FLASH is used for the output of mode bit busy, inside IO pin IO_2 among the RPMC is used for the input of mode bit busy, therefore, can be with inside IO pin IO_0 among the FLASH and the interconnection of the inside IO pin IO_2 among the RPMC, it is right that IO_0 and IO_2 are the inside IO pin of interconnection.Interconnection back FLASH can export the mode bit busy of self the inside IO pin IO_2 of RPMC to by its inner IO pin IO_0, and RPMC can be known the state that FLASH is current.

Again for example, inside IO pin IO_1 among the FLASH is used for the input of mode bit busy, inside IO pin IO_3 among the RPMC is used for the output of mode bit busy, therefore, can be with inside IO pin IO_1 among the FLASH and the interconnection of the inside IO pin IO_3 among the RPMC, it is right that IO_1 and IO_3 are the inside IO pin of interconnection.Interconnection back RPMC can export the mode bit busy of self the inside IO pin IO_1 of FLASH to by its inner IO pin IO_3, and FLASH can be known the state that RPMC is current.

For the interconnection of a plurality of inner IO pin that is comprised between the FLASH, can be inside IO pin interconnection with the same mode bit of expression between each FLASH.

For example, the inside IO pin IO_4 among the FLASH_0 is used for the output of mode bit busy, and the inside IO pin among another FLASH_1 is the input that IO_6 is used for mode bit busy.Therefore, can be with inside IO pin IO_4 among two FLASH and IO_6 interconnection, it is right that IO_4 and IO_6 are the inside IO pin of interconnection, interconnection back FLASH_0 can export the mode bit busy of self the inside IO pin IO_6 of FLASH_1 to by its inner IO pin IO_4, and FLASH_1 can be known the state that FLASH_0 is current.

Again for example, inside IO pin IO_5 among the FLASH_0 is used for the input of mode bit busy, inside IO pin IO_7 among the FLASH_1 is used for the output of mode bit busy, therefore, can be with inside IO pin IO_5 among the FLASH_0 and the interconnection of the inside IO pin IO_7 among the FLASH_1, it is right that IO_5 and IO_7 are the inside IO pin of interconnection.Interconnection back FLASH_1 can export the mode bit busy of self the inside IO pin IO_5 of FLASH_0 to by its inner IO pin IO_7, and FLASH_0 can be known the state that FLASH_1 is current.

For described enhancement mode Flash chip, will introduce in detail in the following embodiments with RPMC function.In the embodiment of the invention, because a plurality of FLASH and RPMC are packaged together, can select a plurality of Flash chips of different capabilities, different process according to real needs, satisfied demand to the Flash capacity extension, avoid the secondary development of Flash, reduce design cost and production cost, and, the FLASH circuit module can reuse existing FLASH chip, the designer only need design the RPMC circuit module and get final product, and therefore, the chip design complexity is low, the design cycle is short, cost is low.And, can intercom mutually to carrying out inside by the inside IO pin of interconnection between RPMC and the FLASH, thus the synchronism of assurance RPMC and FLASH.

Embodiment two:

Below, describe in detail by two pairs of described enhancement mode Flash chips of the embodiment of the invention.

With reference to Fig. 1, show the logic connection diagram of the embodiment of the invention two described a kind of enhancement mode Flash chips.

As can be seen from Figure 1, the described enhancement mode Flash chip of the embodiment of the invention can comprise a plurality of FLASH and the RPMC that is packaged together.

Wherein, all comprise a plurality of pins among FLASH and the RPMC respectively, RPMC can be connected on the same set of outside shared pins with identical IO pin among each FLASH, the outside instruction meeting that sends is received simultaneously by RPMC and each FLASH, and RPMC and each FLASH can make corresponding response.

FLASH and RPMC also comprise inner IO pin separately, the inside IO pin of FLASH and the inside IO pin of RPMC, and the inside IO pin interconnection between the different FLASH; RPMC and FLASH also can have separately independently IO pin.A plurality of FLASH are in the same place with a RPMC Chip Packaging, have realized having the FLASH of RPMC function.

In the embodiment of the invention, described pin of chip can comprise following three kinds:

1, outside shared pins

In the embodiment of the invention, comprise identical IO pin among FLASH and the RPMC, described FLASH is connected to same outside shared pins with identical IO pin among the described RPMC, specifically can be described FLASH all be connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, or, the a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and be connected on the same outside shared pins of described chip, described outside shared pins can be for a plurality of.

For example, comprise a RPMC among Fig. 1, and FLASH_0～FLASH_m, IO_0, IO_1 ..., IO_n is the outside of described chip and shares interface, among the FLASH with IO_0, IO_1, ..., among IO interface that IO_n connects and the RPMC with IO_0, IO_1 ..., the IO interface that IO_n connects is identical IO interface among FLASH and the RPMC.

Need to prove, because Fig. 1 is the logic connection diagram of chip, so IO_0 wherein, IO_1 ..., IO_n all is called interface, and these interfaces in this logic connection layout promptly are called pin on the physical connection of chip.

In the embodiment of the invention, described FLASH and described RPMC comprise separately independently controller respectively, external command can be transferred to by the outside shared pins of described chip among FLASH_0～FLASH_m and the described RPMC, and the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively.

Preferably, when described chip receives external command by outside shared pins, can carry out following process:

When described chip receives first external command by outside shared pins, if being judged as described first external command, the controller of RPMC need RPMC to carry out, and the controller of each FLASH and the controller of RPMC are judged as described first external command respectively needs part or all of FLASH to carry out, and then each FLASH and described RPMC carry out corresponding operating according to described first external command separately;

If only need part FLASH to carry out described first external command, or only need RPMC to carry out described first external command, then carry out according to described first external command in the process of corresponding operating at described FLASH or described RPMC, then described FLASH or described RPMC carry out corresponding operating according to described first external command.

For example, receive external command a as fruit chip, this moment, external command a can be transferred to respectively among each FLASH and the described RPMC by outside shared pins, and the controller of FLASH and the controller of RPMC all can judge whether carry out described external command separately.If the controller by each FLASH is judged as and need carries out external command a by whole FLASH, controller by RPMC is judged as needs RPMC to carry out external command a, and then all FLASH and RPMC can carry out the operation of corresponding instruction a simultaneously according to described external command a.

Do not need FLASH to carry out external command a if the controller by each FLASH is judged as, the controller by RPMC is judged as and needs RPMC to carry out external command a, and then RPMC carries out the operation of corresponding instruction a according to described external command a.

If being judged as, the controller by each FLASH only need part FLASH to carry out external command a, controller by RPMC is judged as needs RPMC to carry out external command a, and then part FLASH and RPMC can carry out the operation of corresponding instruction a simultaneously according to described external command a.

If the controller by each FLASH is judged as and need carries out external command a (for example program PROGRAM or chip erase instruction ERASE) by whole FLASH, controller by RPMC is judged as does not need RPMC to carry out external command a, and then part FLASH carries out the operation of corresponding instruction a according to described external command a.

If being judged as, the controller by each FLASH only need part FLASH to carry out external command a (piece erasing instruction), controller by RPMC is judged as does not need RPMC to carry out external command a, and then part FLASH carries out the operation of corresponding instruction a according to described external command a.

After receiving first external command, if described chip receives second external command by outside shared pins, then the controller of the controller of each FLASH and RPMC also judges whether respectively to carry out described second external command, can be divided into following several situation:

1, if only need whole FLASH to carry out described first external command, promptly RPMC is in idle condition, and after receiving second external command, if second external command needs RPMC to carry out, then RPMC carries out corresponding operating according to described second external command; For example, receive external command b as fruit chip, the controller by each FLASH was judged as and need carries out external command b by whole FLASH this moment, controller by RPMC is judged as does not need RPMC to carry out external command b, is then carried out the operation of corresponding instruction b according to described external command b by whole FLASH.Carry out in the process of described external command b at FLASH, receive external command c again as fruit chip, controller by FLASH is judged as does not need FLASH to carry out external command c, controller by RPMC is judged as needs RPMC to carry out external command c, then can be carried out the operation of corresponding instruction c by RPMC according to described external command c.

2, if only need part FLASH to carry out described first external command, be that part FLASH and RPMC are in idle condition, after receiving second external command, if second external command only needs other FLASH and/or RPMC to carry out, then other FLASH and/or RPMC carry out corresponding operating according to described second external command.

For example, receive external command b as fruit chip, the controller by FLASH was judged as and only needed part FLASH to carry out external command b this moment, controller by RPMC is judged as does not need RPMC to carry out external command b, then can be carried out the operation of corresponding instruction b by part FLASH according to described external command b.Carry out in the process of described external command b at part FLASH, receive external command c again as fruit chip.Need other FLASH and/or RPMC to carry out external command c if the controller by other FLASH and RPMC is judged as, then can carry out the operation of corresponding instruction c according to described external command c by other FLASH and/or RPMC.

3, if only need part FLASH and RPMC to carry out described first external command, be that other FLASH is in idle condition, after receiving second external command, if second external command only needs other FLASH to carry out, then other FLASH carries out corresponding operating according to described second external command;

For example, receive external command b as fruit chip, the controller by each FLASH was judged as and needed part FLASH to carry out external command b this moment, controller by RPMC is judged as needs RPMC to carry out external command b, is then carried out the operation of corresponding instruction b according to described external command b by part FLASH and RPMC.Carry out in the process of described external command b at part FLASH and RPMC, receive external command c again as fruit chip, controller by other FLASH is judged as needs FLASH to carry out external command c, controller by RPMC is judged as does not need RPMC to carry out external command c, then can be carried out the operation of corresponding instruction c by other FLASH according to described external command c.

4, if only need RPMC to carry out described first external command, after receiving second external command, if second external command needs part or all of FLASH to carry out, then described FLASH carries out corresponding operating according to described second external command.

For example, receive external command b as fruit chip, the controller by each FLASH was judged as and did not need FLASH to carry out external command b this moment, and the controller by RPMC is judged as and needs RPMC to carry out external command b, is then carried out the operation of corresponding instruction b according to described external command b by RPMC.Carry out in the process of described external command b at RPMC, receive external command c again as fruit chip, controller by FLASH is judged as and need carries out external command c by part or all of FLASH, controller by RPMC is judged as does not need RPMC to carry out external command c, then can be carried out the operation of corresponding instruction c by part or all of FLASH according to described external command c.

If all FLASH and RPMC are all carrying out first external command, then second external command is not all carried out in the judgement of the controller of the controller of each FLASH and RPMC.

More than in the various situations, if second external command is SUSPEND, Deep Power Down and Reset instruction, first external command that then can interrupt carrying out.

Therefore,, comprise that a plurality of chips of a plurality of FLASH and RPMC can be carried out identical instruction or different instructions simultaneously, thereby realize FLASH and RPMC by said process, or the process of parallel execution of instructions between the FLASH.For example, FLASH is at executive program (PROGRAM) or wipe in the process of (ERASE), and RPMC can execute instruction.

2, Hu Lian inside IO pin is right

In the embodiment of the invention, described FLASH and described RPMC also comprise inner IO pin separately, the inside IO pin interconnection of the inside IO pin of described FLASH and described RPMC intercoms to carrying out inside mutually by the inside IO pin that interconnects between described FLASH and the described RPMC.

For example, inside IO interface (being pin) IO_# among Fig. 1 among FLASH_0～FLASH_m and promptly form the inside IO interface that interconnects on the described chip to (i.e. Hu Lian inside IO pin to) with inside IO interface IO_# among the RPMC of its interconnection, the inside IO interface of described interconnection is to being a plurality of.Can carry out inside and intercom mutually by the inside IO interface IO_# among the FLASH with inside IO interface IO_# among the RPMC of its interconnection between described FLASH and the described RPMC.

In the embodiment of the invention, can intercom mutually to carrying out inside by the inside IO pin of interconnection between FLASH and the RPMC.For example, can the inside IO pin IO_2 interconnection of the inside IO pin IO_0 of output of mode bit busy and the input that RPMC is used for mode bit busy will be used among the FLASH_0; And the inside IO pin IO_3 interconnection of the inside IO pin IO_1 of input of mode bit busy and the output that RPMC is used for mode bit busy will be used among the FLASH.It is right that IO_0 and IO_2 and IO_1 and IO_3 are respectively the inside IO pin of interconnection.Therefore, inside IO pin that can be by above-mentioned interconnection between FLASH_0 and the RPMC carries out inside to IO_0 and IO_2 and intercoms mutually, notifies the other side with the value of mode bit busy of self.

Take similar mode, the inside IO pin interconnection by with different FLASH can realize the communication between the different FLASH, notifies the other side with the value of mode bit busy of self.

Therefore, in a plurality of FLASH and RPMC at least one carried out external command, and when existing FLASH or RPMC idle, if receive hang-up (SUSPEND) instruction by outside shared pins, then carrying out external command described any one carry out described hang-up instruction, and can send the notification message of having hung up by other FLASH of inside IO pin subtend free time or the RPMC of interconnection, make other idle FLASH or RPMC also carry out described hang-up instruction, thereby can guarantee FLASH and RPMC, and between a plurality of FLASH synchronously.

Preferably, the synchronizing process of FLASH and RPMC can comprise:

When part FLASH is carrying out external command, and when other FLASH and described RPMC are idle, if described chip receives by outside shared pins and hangs up instruction, the controller of then carrying out the FLASH of external command is judged as needs FLASH to carry out described hang-up instruction, and the controller of other FLASH and the controller of described RPMC are judged as does not need RPMC to carry out described hang-up instruction;

After the operation that the FLASH that is carrying out external command is carrying out according to described hang-up instruction suspends, inside other FLASH of IO pin subtend and described RPMC by described interconnection send the notification message that FLASH has hung up, after other FLASH and described RPMC receive described notification message, by carrying out the synchronous of described hang-up instruction each FLASH of realization and described RPMC.

Perhaps,

When described RPMC is carrying out external command, and when all FLASH is idle, if described chip receives by outside shared pins and hangs up instruction, then the controller of described whole FLASH is judged as does not need FLASH to carry out described hang-up instruction, and the controller of described RPMC is judged as needs RPMC to carry out described hang-up instruction;

After the operation that described RPMC is carrying out according to described hang-up instruction suspends, whole FLASH send the notification message that RPMC has hung up by the inside IO pin subtend of described interconnection, after all FLASH receives described notification message, by carrying out the synchronous of described hang-up instruction realization and described RPMC.

In concrete realization, also there are other situations, for example all FLASH is carrying out external command, has only the described RPMC free time etc., and the process that instruction is hung up in corresponding execution is similar to above-mentioned example, differs one for example at this.

For example, part FLASH is in busy (busy) state, other FLASH and RPMC are in free time (idle) state:

When chip receives external command A by outside shared pins, controller by FLASH is judged as needs part FLASH to carry out external command A, controller by RPMC is judged as does not need RPMC to carry out external command A, then carry out the operation of corresponding instruction A according to described external command A by FLASH, and FLASH carries out in the process of A, configuration state position busy=1, RPMC is in idle condition, configuration state position busy=0.

At this moment, as fruit chip by as described in outside shared pins receive and hang up instruction, because this moment, part FLASH was in busy condition, other FLASH and RPMC are in idle condition, therefore, controller by FLASH is judged as the FLASH that need carry out external command and carries out described hang-up instruction, and the controller by other FLASH and RPMC is judged as and does not need RPMC to carry out described hang-up instruction, is then carrying out the operation that the FLASH of external command is carrying out according to described hang-up instruction suspends.

After the operation that the FLASH that is carrying out external command is carrying out according to described hang-up instruction suspends, inside other FLASH of IO pin subtend and described RPMC by described interconnection send the notification message that FLASH has hung up, after other FLASH and RPMC receive described notification message, recognize that the FLASH that is in the busy=1 state hangs up, thus other FLASH and RPMC also will by carry out described hang-up instruction realize with described FLASH synchronously.

And for example, all FLASH are in free time (idle) state, RPMC is in busy (busy) state:

When chip receives external command B by outside shared pins, controller by each FLASH is judged as does not all need FLASH to carry out external command B, controller by RPMC is judged as needs RPMC to carry out external command B, then carry out the operation of corresponding instruction B according to described external command B by RPMC, and RPMC carries out in the process of B, configuration state position busy=1, FLASH is in idle condition, configuration state position busy=0.

At this moment, as fruit chip by as described in outside shared pins receive and hang up instruction, because this moment, all FLASH was in idle condition, RPMC is in busy condition, therefore, controller by each FLASH is judged as does not need FLASH to carry out described hang-up instruction, and the controller by RPMC is judged as and needs RPMC to carry out described hang-up instruction, the operation that then described RPMC is carrying out according to described hang-up instruction suspends.

After the operation that RPMC is carrying out according to described hang-up instruction suspends, RPMC sends the notification message that RPMC has hung up by the whole FLASH of the inside IO pin subtend of described interconnection, after each FLASH receives described notification message, recognize that the RPMC that is in the busy=1 state hangs up, so each FLASH also all to pass through to carry out the synchronous of described hang-up instruction realization and described RPMC.

But, right as the inside IO pin that does not have interconnection on the fruit chip, can't notify RPMC (perhaps RPMC can't notify FLASH after hanging up) after then FLASH hangs up, therefore, after the RPMC of idle condition (perhaps FLASH) receives and hangs up instruction, can ignore this hang-up instruction, thereby cause RPMC also can continue to carry out the follow-up instruction that receives, but FLASH (perhaps RPMC) can not carry out the follow-up instruction that receives owing to hang up, and then causes FLASH and the nonsynchronous problem of RPMC.

In addition, if FLASH and RPMC all are in busy condition (being that FLASH and RPMC are according to external command execution corresponding operating).At this moment, receive the hang-up instruction as fruit chip by outside shared pins, then the controller by FLASH is judged as needs FLASH to carry out described hang-up instruction, controller by RPMC is judged as needs RPMC to carry out described hang-up instruction, the operation that described FLASH and RPMC all can carry out according to described hang-up instruction suspends, and the notification message of inside IO pin by described interconnection to having hung up to the other side's transmit leg respectively.

3, outside individual pin

In the embodiment of the invention, the outside individual pin on the described chip can comprise following two kinds:

(1) the outside individual pin relevant with FLASH

In the embodiment of the invention, the independent IO pin that also comprises the realization FLASH function that links to each other with FLASH among each FLASH, the independent IO pin that described and FLASH link to each other are connected on the outside individual pin (promptly with FLASH relevant outside individual pin) of described chip.

For example, the IO_F_0 among Fig. 1 ..., IO_F_0, IO_F0_0 ..., IO_F0_0 ..., IO_Fm_0 ..., IO_Fm_0 is outside stand-alone interface relevant with FLASH on the described chip (being pin), among the FLASH with IO_F_0, ..., IO_F_0, IO_F0_0, ..., IO_F0_0 ..., IO_Fm_0 ..., the IO interface that IO_Fm_0 connects is the described independent IO interface that links to each other with FLASH.

In the embodiment of the invention, external command can be transferred to by outside individual pin relevant with FLASH on the described chip among the described FLASH, the controller of FLASH need can judge whether FLASH to carry out described external command, if desired, then carry out corresponding operating according to described external command by FLASH.

(2) the outside individual pin relevant with RPMC

In the embodiment of the invention, the independent IO pin that also comprises the realization RPMC function that links to each other with RPMC among the described RPMC, the independent IO pin that described and RPMC link to each other are connected on the other outside individual pin (promptly with RPMC relevant outside individual pin) of described chip.

For example, the IO_R_0 among Fig. 1 ..., IO_R_0 be on the described chip with the relevant outside stand-alone interface (being pin) of RPMC, among the RPMC with IO_R_0 ..., the IO interface that IO_R_0 connects is the described independent IO interface that links to each other with RPMC.

In the embodiment of the invention, external command can be transferred to by outside individual pin relevant with RPMC on the described chip among the described RPMC, the controller of RPMC need can judge whether RPMC to carry out described external command, if desired, then carries out corresponding operating by RPMC according to described external command.

In above-mentioned (1) and (2), the described independent IO pin that links to each other with FLASH does not link to each other mutually with the independent IO pin that links to each other with described RPMC.

Below, introducing between each pin in conjunction with Fig. 2 and how to connect, Fig. 2 is the encapsulation schematic diagram of the embodiment of the invention two described a kind of enhancement mode Flash chips.

Among Fig. 2, Package is a wrapper, and Die_a_0..., Die_a_m are FLASH, and Die_b is RPMC, and the area of FLASH is greater than the area of RPMC.Among Fig. 2, PAD_0 ..., PAD_# ..., PAD_n is the IO pin of Chip Packaging, comprising outside shared pins and outside individual pin; Pin_a_0 ..., Pin_a_#, ..., Pin_a_n ..., Pin_x_0 ..., Pin_x_#, ..., Pin_x_n ..., Pin_m_0 ..., Pin_m_#, ..., Pin_m_n is the IO pin of FLASH, comprising the independent IO pin of the IO pin identical with RPMC, the realization FLASH function that links to each other with FLASH and the inside IO pin of FLASH; Pin_b_0 ..., Pin_b_# ..., Pin_b_n is the IO pin of RPMC, comprising the independent IO pin of the IO pin identical with FLASH, the realization RPMC function that links to each other with RPMC and the inside IO pin of RPMC.Wherein, # represents any one number between 0 to n.

The connection of I, outside shared pins

In the embodiment of the invention, the identical IO pin interconnection among described FLASH and the described RPMC, and be connected on the same outside shared pins of described chip, can comprise:

Identical IO pin b_y interconnection (function of the IO pin b_y of the IO pin a_x of FLASH and RPMC is identical) among the IO pin a_x of described FLASH and the described RPMC, and the IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip;

For example, among Fig. 2, Pin_a_0 (be a_x, x=0) with Pin_b_# (be b_y, y=#) interconnection, Pin_a_0 be connected to chip same outside shared pins PAD_0 (be PAD_z, z=0) on; And Pin_a_# (be a_x, x=#) with RPMC in the interconnection of identical IO pin, Pin_a_# be connected to chip same outside shared pins PAD_# (be PAD_z, z=#) on.Above-mentioned two kinds all belong to the situation that the outside shared pins of this kind connects.

Perhaps,

Identical IO pin b_y interconnection among the IO pin a_x of described FLASH and the described RPMC, the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip.

For example, among Fig. 2, Pin_a_n (be a_x, x=n) with Pin_b_0 (be b_y, y=0) interconnection, Pin_b_0 be connected to chip same outside shared pins PAD_# (be PAD_z, z=#) on, promptly belong to the situation that the outside shared pins of this kind connects.

Perhaps,

The IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip, and the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip;

For example, among Fig. 2, Pin_a_0 (be a_x, x=0) with Pin_m_# (be m_y, y=#) be directly connected to same outside shared pins PAD_# (be PAD_z, z=#) on, promptly belong to the situation that the outside shared pins of this kind connects.Need to prove that in concrete realization, RPMC can not link to each other with FLASH, but is directly connected on the outside shared pins.

Wherein, described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH, x=0, and 1 ..., n; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC, y=0, and 1 ..., n; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging, z=0, and 1 ..., n.

II, the right connection of inner IO pin

The inside IO pin interconnection of the inside IO pin of described FLASH and described RPMC, can comprise: the inside IO pin a_x of described FLASH is connected to the inside IO pin b_y of described RPMC.Wherein, the inside IO pin b_y of the inside IO pin a_x of FLASH and RPMC can represent same mode bit.

For example, Pin_a_# among Fig. 2 (be a_x, x=#) with RPMC in the interconnection of inside IO pin, and Pin_b_n (is b_y, y=n) with FLASH in the interconnection of inside IO pin, the situation that the inside IO pin of above-mentioned two kinds of inside IO pins that all belong to FLASH and RPMC interconnects.

The connection of III, outside individual pin

(i) the described independent IO pin that links to each other with FLASH is connected on the outside individual pin of described chip, can comprise: the IO pin a_x of described FLASH is connected on the outside individual pin PAD_z of described chip.

For example, lower right-hand corner among Fig. 2, the independent IO pin a_x that links to each other with FLASH be connected to described chip outside individual pin PAD_n (be PAD_z, z=n) on.

The (ii) described independent IO pin that links to each other with RPMC is connected on the other outside individual pin of described chip, can comprise: the IO pin b_y of described RPMC is connected on the outside individual pin PAD_z of described chip.

For example, among Fig. 2, the independent IO pin Pin_b_# that links to each other with RPMC (be b_y, y=#) be connected to described chip outside individual pin PAD_# (be PAD_z, z=#) on.

For the connection of other pin among Fig. 2, the embodiment of the invention is discussed no longer in detail at this.At last, need to prove, be to be vertical pile among Fig. 2 with a FLASH and RPMC, placed side by side on chip carrier after other FLASH vertical pile with described RPMC, in described chip, a plurality of FLASH and described RPMC also can be all placed side by side on chip carrier, perhaps, a plurality of FLASH and described RPMC can vertical pile on chip carrier, the embodiment of the invention is not limited this.And superpose when encapsulation when described FLASH is vertical with described RPMC: if the area of described FLASH is greater than the area of described RPMC, then described RPMC vertical pile is on described FLASH; If the area of described RPMC is greater than the area of described FLASH, then described FLASH vertical pile is on described RPMC, be also can be that Die_a is RPMC among Fig. 2, Die_b is FLASH, when a plurality of FLASH vertical pile are on chip carrier, with the little FLASH vertical pile of area on the big FLASH of area.

The embodiment of the invention has proposed a kind of enhancement mode Flash chip that utilizes multicore sheet method for packing to realize the RPMC function, by on the basis of FLASH chip, RPMC is encapsulated with a plurality of FLASH chips, thereby form an enhancement mode Flash chip with RPMC function, RPMC and FLASH can share unified pin.The embodiment of the invention can be according to real needs, select a plurality of Flash chips of different capabilities, different process, satisfied demand to the Flash capacity extension, avoid the secondary development of Flash, reduce design cost and production cost, and, can intercom mutually to carrying out inside by the inside IO pin of interconnection between RPMC and the FLASH, thus the synchronism of assurance RPMC and FLASH.In addition, in the embodiment of the invention, FLASH can also carry out different instructions simultaneously with RPMC, and promptly FLASH and RPMC can concurrent workings, therefore, improved the performance of chip.

Embodiment three:

Below, introduce the concrete method for packing of said chip by the embodiment of the invention three.

With reference to Fig. 3, show the flow chart of the embodiment of the invention three described a kind of method for packing, described method for packing can comprise:

Step 300, a plurality of FLASH that needs are encapsulated protect monotone counter RPMC to be placed on the chip carrier with replying, and described FLASH and described RPMC are separate.

In the embodiment of the invention, mainly be that a plurality of FLASH and RPMC are packaged together, thereby obtain having the enhancement mode Flash chip of RPMC function, and FLASH described in the chip and described RPMC are separate.

At first, the FLASH and the RPMC of needs encapsulation can be placed on the chip carrier, the described chip carrier of the embodiment of the invention can be corresponding to the Package among Fig. 2.

Preferably, this step 300 can comprise: a plurality of FLASH and described RPMC are all placed side by side on chip carrier, perhaps, with a FLASH and described RPMC vertical pile on chip carrier, and with placed side by side on chip carrier after other FLASH vertical pile with described RPMC, perhaps, a plurality of FLASH and described RPMC vertical pile are on chip carrier.

Encapsulation principle shown in Figure 2 is described FLASH and described RPMC vertical pile on chip carrier.

In the embodiment of the invention, when described FLASH and described RPMC vertical pile are on chip carrier:

If the area of described FLASH is greater than the area of described RPMC, then described RPMC vertical pile is on described FLASH;

If the area of described RPMC is greater than the area of described FLASH, then described FLASH vertical pile is on described RPMC;

When a plurality of FLASH vertical pile are on chip carrier, with the little FLASH vertical pile of area on the big FLASH of area.

Step 302, all adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, or adopt metal lead wire to interconnect in twos a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC, adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the interconnection.

In the embodiment of the invention, can there be some identical IO pins (function is identical) among FLASH and the RPMC, can adopt the metal lead wire interconnection for these identical IO pins.Concrete, can adopt metal lead wire to interconnect with identical IO pin b_y among the described RPMC IO pin a_x of described FLASH.Preferably, all adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, can comprise:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip the IO pin a_x of described FLASH, and the identical IO pin b_y among the described RPMC adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip.

Adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the interconnection, can comprise:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the IO pin a_x of described FLASH, perhaps, adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the identical IO pin b_y among the described RPMC;

Wherein, the IO pin b_y among the IO pin a_x of described FLASH and the described RPMC is the identical IO pin of interconnection;

Described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging.

Above-mentioned steps 302 is the situation that outside shared pins connects.For example, the upper right corner of FLASH_0 place, Pin_a_0 (be a_x, x=0) with Pin_b_# (be b_y, y=#) interconnection, Pin_a_0 be connected to chip same outside shared pins PAD_0 (be PAD_z, z=0) on; The lower right corner Pin_a_# of FLASH_0 (be a_x, x=#) with RPMC in the interconnection of identical IO pin, Pin_a_# be connected to chip same outside shared pins PAD_# (be PAD_z, z=#) on; And among Fig. 2, Pin_a_n (be a_x, x=n) with Pin_b_0 (be b_y, y=0) interconnection, Pin_b_0 be connected to chip same outside shared pins PAD_# (be PAD_z, z=#) on.Above-mentioned situation all belongs to the situation that outside shared pins connects.

Being used among Fig. 2 connects the dotted line of two pins and can represent the described metal lead wire of the embodiment of the invention.

Step 304 adopts metal lead wire to interconnect in twos a plurality of inner IO pin that comprises altogether among described FLASH and the described RPMC.

In the embodiment of the invention, can also comprise inside IO pin separately among FLASH and the RPMC, the inside IO pin a_x of FLASH can be adopted metal lead wire be connected to the inside IO pin b_y of described RPMC.Wherein, the inside IO pin b_y of the inside IO pin a_x of FLASH and RPMC can represent same mode bit.

For example, the Pin_a_# in the FLASH_0 lower right corner (is a_x, x=#) with RPMC in inside IO pin interconnect by metal lead wire, and Pin_b_n (is b_y, y=n) with FLASH in inside IO pin interconnect the situation that the inside IO pin of above-mentioned two kinds of inside IO pins that all belong to FLASH and RPMC adopts metal lead wire to interconnect by metal lead wire.

Step 306 adopts metal lead wire to be connected on the outside individual pin of described chip carrier the independent IO pin of realizing the FLASH function among each FLASH.

In the embodiment of the invention, can also comprise the independent IO pin of realizing the FLASH function among each FLASH, the independent IO pin among these FLASH can be adopted metal lead wire be connected on the outside individual pin of described chip carrier.

For example, lower right-hand corner among Fig. 2, the independent IO pin a_x that links to each other with FLASH by metal lead wire be connected to described chip outside individual pin PAD_n (be PAD_z, z=n) on.

Step 308 adopts metal lead wire to be connected on the other outside individual pin of described chip carrier the independent IO pin of realizing the RPMC function among the described RPMC.

Same, can also comprise the independent IO pin of realizing the RPMC function among the described RPMC, the independent IO pin among these RPMC can be adopted metal lead wire be connected on the other outside individual pin of described chip carrier.

For example, among Fig. 2, the independent IO pin Pin_b_n that links to each other with RPMC (is b_y, y=n) is connected on the outside individual pin PAD_z of described chip by metal lead wire.

Wherein, the independent IO pin among the described FLASH does not link to each other mutually with independent IO pin among the described RPMC.

Step 310 is the enhancement mode Flash chip with RPMC function with a plurality of FLASH, described RPMC and described chip carrier plastic packaging.

After through above-mentioned steps 300-step 308, finished being connected of each pin on the placement of a plurality of FLASH and RPMC and the chip.At last, can be enhancement mode Flash chip with a plurality of FLASH, described RPMC and described chip carrier plastic packaging with RPMC function, promptly finished the encapsulation of chip after the plastic packaging.

Embodiment four:

Below, be presented in the manner of execution of instructing in the said chip by the embodiment of the invention four.

With reference to Fig. 4, show the flow chart of the embodiment of the invention four described a kind of instruction executing methods, specifically can comprise:

Step 400 receives first external command.

In the embodiment of the invention; be packaged with a plurality of FLASH and one in the described chip and reply protection monotone counter RPMC; can have identical IO pin among each FLASH and the RPMC; these identical IO pins are connected to same outside shared pins, and external command is transferred among each FLASH and the RPMC by outside shared pins.

Step 402, by each FLASH and RPMC separately independently controller judge whether to carry out described first external command respectively.

Each FLASH and described RPMC can comprise separately independently controller respectively, the instruction of sending for the outside, each FLASH and RPMC can by separately independently controller control each FLASH and RPMC receives respectively, deciphers, after successfully decoded, the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively, if carry out, then carry out corresponding operation according to first external command.

Step 404 needs RPMC and all or part of FLASH to carry out described first external command if be judged as, and then carries out corresponding operating by RPMC and each FLASH according to described first external command.

Step 406 only needs part FLASH to carry out described first external command if be judged as, or only needs RPMC to carry out described first external command, then carries out corresponding operating by described FLASH or described RPMC according to described first external command.

The controller of RPMC and the controller of each FLASH judge whether to carry out described external command respectively, and judged result can be divided into two class situations:

One class is to need RPMC and FLASH to carry out first external command simultaneously, the controller judgement that specifically can be RPMC needs to carry out first external command, the judged result of the controller of a plurality of FLASH be whole FLASH all need to carry out first external command or, only part FLASH all needs to carry out first external command.In this case, carry out corresponding operating by RPMC and each FLASH according to described first external command.

Another kind of RPMC of being and FLASH do not carry out first external command simultaneously, specifically can be, the controller of RPMC is judged to be needed to carry out first external command, and the judged result of the controller of a plurality of FLASH is all not need to carry out first external command; Perhaps, the controller of RPMC is judged not to be needed to carry out first external command, and the judged result of the controller of a plurality of FLASH is that needs part or whole FLASH carry out first external command.In this case, carry out corresponding operating by RPMC or FLASH according to described first external command.

Further, described method can also comprise:

Receive second external command;

If have idle FLASH or RPMC, and idle FLASH or RPMC judge and need to carry out described second external command that then the FLASH of described free time or RPMC carry out corresponding operating according to described second external command.

In concrete realization, chip can receive a plurality of instructions, the controller of each FLASH and the controller of RPMC judge whether to carry out second external command, if all FLASH and RPMC are all carrying out first external command, then second external command is not all carried out in the judgement of the controller of the controller of each FLASH and RPMC; If have idle FLASH or RPMC, and idle FLASH or RPMC judge and need to carry out described second external command that then the FLASH of described free time or RPMC carry out corresponding operating according to described second external command.

Further, described method can also comprise: receive and hang up instruction;

The FLASH and/or the RPMC that are carrying out described first external command carry out described hang-up instruction, and send the notification message of having hung up to FLASH and/or the RPMC of free time;

After idle FLASH and/or RPMC receive notification message, carry out described hang-up instruction.

In a plurality of FLASH and RPMC at least one carried out external command, and when existing FLASH or RPMC idle, if receive the hang-up instruction by outside shared pins, then carrying out external command described any one carry out described hang-up instruction, and can send the notification message of having hung up to other FLASH or the RPMC of free time, make other idle FLASH or RPMC also carry out described hang-up instruction, thereby can guarantee FLASH and RPMC, and between a plurality of FLASH synchronously.

In sum, the embodiment of the invention can comprise following advantage:

1, the enhancement mode Flash chip with RPMC function that the embodiment of the invention proposed is that a plurality of FLASH and a RPMC are packaged together; Wherein, each FLASH circuit comprises separately independently controller, identical IO pin and inner IO pin respectively with described RPMC circuit; Described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, or a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip; External command is transferred among FLASH and the RPMC by the outside shared pins of described chip, and the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively; The a plurality of identical inner IO pins that comprise altogether among described FLASH and the described RPMC interconnect in twos, and the inside IO pin by interconnection intercoms mutually to carrying out inside between described FLASH and the described RPMC or between each FLASH.In the embodiment of the invention, because a plurality of FLASH and RPMC are packaged together, can be according to real needs, select a plurality of Flash chips of different capabilities, different process, satisfied demand, avoided the secondary development of Flash, reduced design cost and production cost the Flash capacity extension; And the FLASH circuit module can reuse existing FLASH chip, and the designer only need design the RPMC circuit module and get final product, and therefore, the chip design complexity is low, the design cycle is short, cost is low; And can reduce package area, reduce cost.

2, each FLASH can carry out different instructions simultaneously, and FLASH also can carry out different instructions simultaneously with RPMC, and promptly FLASH and RPMC can concurrent workings, and different FLASH also can concurrent working, therefore, has improved the performance of chip.

3, between a plurality of FLASH, and can intercom mutually to carrying out inside by the inside IO pin of interconnection between FLASH and the RPMC.Therefore, in FLASH and RPMC at least one carried out external command, and when other FLASH and/or RPMC are idle, if receive the hang-up instruction by outside shared pins, the FLASH and/or the RPMC that are then carrying out external command carry out described hang-up instruction, and the FLASH of free time and/or the RPMC of inside IO pin subtend free time that can be by interconnection send the notice of having hung up, make idle FLASH and/or RPMC also carry out described hang-up instruction, thus can guarantee FLASH and RPMC synchronously.

4, multicore sheet encapsulation can be the FLASH of different process and RPMC encapsulation together, thereby can multiplexing existing resources, reduces development cost.

Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.

For aforesaid method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the specification all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.

At last, also need to prove, in this article, relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or in proper order between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make and comprise that process, method, commodity or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as this process, method, commodity or equipment intrinsic key element.Do not having under the situation of more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, commodity or the equipment that comprises described key element and also have other identical element.

More than to a kind of enhancement mode Flash chip provided by the present invention, a kind of method for packing and a kind of instruction executing method, be described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (14)

1. an enhancement mode Flash chip is characterized in that, comprising:

The a plurality of FLASH that are packaged together and one reply protection monotone counter RPMC; Wherein,

Each FLASH comprises separately independently controller, identical IO pin and inner IO pin respectively with described RPMC;

Described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, or a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip;

External command is transferred among described FLASH and the described RPMC by the outside shared pins of described chip, and the controller of each FLASH and the controller of RPMC judge whether to carry out described external command respectively;

The a plurality of inner IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and the inside IO pin by interconnection intercoms mutually to carrying out inside between described FLASH and the described RPMC or between each FLASH.

2. enhancement mode Flash chip according to claim 1 is characterized in that:

When described chip receives first external command by outside shared pins, if being judged as described first external command, the controller of RPMC need RPMC to carry out, and each FLASH controller is judged as described first external command needs all or part of FLASH to carry out, and then RPMC and each FLASH all carry out corresponding operating according to described first external command;

If only need part FLASH to carry out described first external command, or only need RPMC to carry out described first external command, then described FLASH or described RPMC carry out corresponding operating according to described first external command.

3. enhancement mode Flash chip according to claim 2 is characterized in that:

If only need whole FLASH to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at whole FLASH, if described chip receives second external command by outside shared pins, and only need RPMC to carry out, then RPMC carries out corresponding operating according to described second external command;

If only need part FLASH to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at part FLASH, if described chip receives second external command by outside shared pins, and only need other FLASH and/or RPMC to carry out, then other FLASH or RPMC carry out corresponding operating according to described second external command;

If only need part FLASH and RPMC to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at part FLASH and RPMC, if described chip receives second external command by outside shared pins, and only need other FLASH to carry out, then other FLASH carries out corresponding operating according to described second external command;

If only need RPMC to carry out described first external command, then carry out in the process of corresponding operating according to described first external command at RPMC, if described chip receives second external command by outside shared pins, and only need part or all of FLASH to carry out, then described FLASH carries out corresponding operating according to described second external command.

4. enhancement mode Flash chip according to claim 1 is characterized in that,

Described FLASH all is connected on the same outside shared pins of described chip with identical IO pin among the described RPMC, comprising:

The IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip, and the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip;

The a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC interconnects in twos, and is connected on the same outside shared pins of described chip, comprising:

Identical IO pin b_y interconnection among the IO pin a_x of described FLASH and the described RPMC, and the IO pin a_x of described FLASH is connected on the same outside shared pins PAD_z of described chip, perhaps, the identical IO pin b_y among the described RPMC is connected on the same outside shared pins PAD_z of described chip;

Wherein, described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging.

5. according to the described enhancement mode Flash chip of claim 1-3, it is characterized in that:

When part FLASH is carrying out external command, and when other FLASH and described RPMC are idle, if described chip receives by outside shared pins and hangs up instruction, the controller of then carrying out the FLASH of external command is judged as needs FLASH to carry out described hang-up instruction, and the controller of other FLASH and the controller of RPMC are judged as does not need RPMC to carry out described hang-up instruction;

After the operation that the FLASH that is carrying out external command is carrying out according to described hang-up instruction suspends, inside other FLASH of IO pin subtend and described RPMC by described interconnection send the notification message that FLASH has hung up, after other FLASH and described RPMC receive described notification message, by carrying out the synchronous of described hang-up instruction each FLASH of realization and described RPMC.

6. enhancement mode Flash chip according to claim 1 is characterized in that:

The inside IO pin of described interconnection is to being a plurality of;

The outside shared pins of described chip is a plurality of.

7. enhancement mode Flash chip according to claim 1 is characterized in that:

Each FLASH also comprises the independent IO pin of the realization FLASH function that links to each other with FLASH, and the described independent IO pin that links to each other with FLASH is connected on the outside individual pin of described chip;

Described RPMC also comprises the independent IO pin of the realization RPMC function that links to each other with RPMC, and the described independent IO pin that links to each other with RPMC is connected on the other outside individual pin of described chip;

Wherein, the described independent IO pin that links to each other with FLASH does not link to each other mutually with the independent IO pin that links to each other with described RPMC.

8. a method for packing is characterized in that, comprising:

Protect monotone counter RPMC to be placed on the chip carrier with replying a plurality of FLASH of needs encapsulation, described FLASH and described RPMC are separate;

All adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, or adopt metal lead wire to interconnect in twos a plurality of identical IO pin that comprises altogether among described FLASH and the described RPMC, adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the interconnection;

Adopt metal lead wire to interconnect in twos a plurality of inner IO pin that comprises altogether among described FLASH and the described RPMC;

With a plurality of FLASH, described RPMC and described chip carrier plastic packaging is the enhancement mode Flash chip with RPMC function.

9. method for packing according to claim 8 is characterized in that, also comprises:

Adopt metal lead wire to be connected on the outside individual pin of described chip carrier the independent IO pin of realizing the FLASH function among each FLASH;

Adopt metal lead wire to be connected on the other outside individual pin of described chip carrier the independent IO pin of realizing the RPMC function among the described RPMC;

Wherein, the independent IO pin among the described FLASH does not link to each other mutually with independent IO pin among the described RPMC.

10. according to Claim 8 or 9 described method for packing, it is characterized in that,

All adopt metal lead wire to be connected on the same outside shared pins of described chip carrier with identical IO pin among the described RPMC described FLASH, comprising:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip the IO pin a_x of described FLASH, and the identical IO pin b_y among the described RPMC adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip;

Adopt metal lead wire to be connected on the same outside shared pins of described chip carrier the identical IO pin after the described interconnection, comprising:

Adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the IO pin a_x of described FLASH, perhaps, adopt metal lead wire to be connected on the same outside shared pins PAD_z of described chip carrier the identical IO pin b_y among the described RPMC;

Described a represents the IO pin of FLASH, and described x represents the IO pin sign of FLASH; Described b represents the IO pin of RPMC, and described y represents the IO pin sign of RPMC; Described PAD represents the IO pin of Chip Packaging, and described z represents the IO pin sign of Chip Packaging.

11. according to Claim 8 or 9 described method for packing, it is characterized in that, describedly will need the FLASH that encapsulates and reply protection monotone counter RPMC to be placed on the chip carrier, comprising:

A plurality of FLASH and described RPMC are all placed side by side on chip carrier, perhaps, with a FLASH and described RPMC vertical pile on chip carrier, and with placed side by side on chip carrier after other FLASH vertical pile with described RPMC, perhaps, a plurality of FLASH and described RPMC vertical pile are on chip carrier;

When described FLASH and described RPMC vertical pile are on chip carrier:

If the area of described FLASH is greater than the area of described RPMC, then described RPMC vertical pile is on described FLASH;

If the area of described RPMC is greater than the area of described FLASH, then described FLASH vertical pile is on described RPMC;

When a plurality of FLASH vertical pile are on chip carrier, with the little FLASH vertical pile of area on the big FLASH of area.

12. an instruction executing method is characterized in that, is packaged with a plurality of FLASH and one in the described chip and replys protection monotone counter RPMC, described method comprises:

Receive first external command;

By each FLASH and RPMC separately independently controller judge whether to carry out described first external command respectively;

If being judged as needs RPMC and all or part of FLASH to carry out described first external command, then carry out corresponding operating according to described first external command by RPMC and each FLASH;

If being judged as only needs part FLASH to carry out described first external command, or only needs RPMC to carry out described first external command, then carry out corresponding operating according to described first external command by described FLASH or described RPMC.

13. according to the described method of claim 12, it is characterized in that, also comprise:

Receive second external command;

If have idle FLASH or RPMC, and idle FLASH or RPMC judge and need to carry out described second external command that then the FLASH of described free time or RPMC carry out corresponding operating according to described second external command.

14. according to the described method of claim 12, it is characterized in that, also comprise:

Receive and hang up instruction;

The FLASH and/or the RPMC that are carrying out described first external command carry out described hang-up instruction, and send the notification message of having hung up to FLASH and/or the RPMC of free time;

After idle FLASH and/or RPMC receive notification message, carry out described hang-up instruction.

Images