CN103219287A - Method for improving carrier mobility of complementary metal oxide semiconductor (CMOS) device - Google Patents
Method for improving carrier mobility of complementary metal oxide semiconductor (CMOS) device Download PDFInfo
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- CN103219287A CN103219287A CN201310084508XA CN201310084508A CN103219287A CN 103219287 A CN103219287 A CN 103219287A CN 201310084508X A CN201310084508X A CN 201310084508XA CN 201310084508 A CN201310084508 A CN 201310084508A CN 103219287 A CN103219287 A CN 103219287A
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Abstract
A method for improving the carrier mobility of a complementary metal oxide semiconductor (CMOS) device comprises the following steps: first, conducting trap implantation to form an N/P trap; second, conducting N/P trap annealing in a deuterium atmosphere; third, growing a grid insulating oxide layer; fourth, depositing polycrystalline silicon gates; fifth, etching the polycrystalline silicon gates to form a grid; sixth, forming first side walls on two sides of the grid; seventh, conducting light dope implantation on a semiconductor substrate to form a light dope source drain structure; eighth, conducting source drain implantation to form a source electrode and a drain electrode; and ninth, manufacturing metal front media, a through hole, a metal plug and a metal layer. According to the method for improving the carrier mobility of the CMOS device, after the N/P trap is formed, conducting annealing in the deuterium atmosphere on the semiconductor substrate before the grid insulating oxide layer is generated, the surface of the semiconductor substrate is made to be smooth, and the surface oxidizing reaction of the semiconductor substrate is conducted stably. Meanwhile, implanted ions in the N/P trap are further activated in the process of annealing, and the carrier mobility of the CMOS device is further improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method of the CMOS of raising carrier mobility.
Background technology
For the deep sub-micron MOS device, the thickness of gate oxide is less than 3nm, and the doping content of channel region is near 10
18Cm
-3Magnitude, these will cause Si/SiO
2Electric field at the interface strengthens.The general interface place surpasses 10 perpendicular to the electric field of surface direction
5V/cm, described highfield not only makes the channel electrons quantization, and stronger surface field also makes transoid mobility of charge carrier rate degenerate.For heavily doped MOS device, Coulomb scattering that ionized impurity causes and phon scattering are strengthened, and are the assignable causes that causes mobility to descend.In addition, because the interface scattering that the out-of-flatness on Si/SiO2 surface causes also is the major reason that Inversion Layer Carrier Mobility descends.
Along with the development of cmos semiconductor device technology and in proportion size dwindle, stress engineering is playing increasing effect aspect semiconductor technology and the device performance.As everyone knows, by to applying corresponding stress in the device channel, can improve the hole mobility (effective mass in hole is much larger than electronics) of PMOS raceway groove, so in technical process, can initiatively introduce the performance that some stress improve device, for example in the SiGe technology, just by applying corresponding stress, to change the lattice constant of raceway groove Si on the raceway groove both sides, and then the effective mass in change hole, in order to improve the mobility in hole.
But described SiGe technology is only used commonplace at 32nm and following technical grade thereof.Because the SiGe board is relatively more expensive, reasons such as the integrated more complicated of technology, more than 40nm, it is quite limited that the SiGe technology is used.Simultaneously, the serious situation about descending of channel carrier mobility is also very general in 40nm and above technical grade thereof.
In addition, along with the thickness of gate oxide constantly dwindles, the leakage current of grid oxygen is also more and more obvious.If control gate oxide layer rough interface degree well, the varied in thickness that the growth of gate oxide heat brings, problems such as oxide layer defective all can be brought fatal harm to device property and reliability.
Therefore, seek a kind of low cost, be easy to integratedly, and when improving the gate oxide quality, can improve the mobility of charge carrier rate again, and then the technology that improves the performance of device has become one of this area problem demanding prompt solution.
So at the problem that prior art exists, this case designer relies on the industry experience for many years of being engaged in, the active research improvement is so there has been a kind of method that improves the cmos device carrier mobility of the present invention.
Summary of the invention
The present invention be directed in the prior art, traditional semiconductor device channel carrier mobility descends serious, and along with the thickness of gate oxide constantly dwindles, the leakage current of grid oxygen is also more and more obvious, gate oxide rough interface degree is wayward, the varied in thickness that gate oxide heat growth brings, problems such as oxide layer defective all can bring defective such as fatal harm that a kind of method that improves the cmos device carrier mobility is provided to device property and reliability.
In order to address the above problem, the invention provides a kind of method that improves the cmos device carrier mobility, described method comprises:
Execution in step S1: carry out trap and inject formation N/P trap;
Execution in step S2: in the deuterium atmosphere, carry out the annealing of N/P trap;
Execution in step S3: growth gate insulator oxide layer;
Execution in step S4: deposit polysilicon gate;
Execution in step S5: the described polysilicon gate of etching, to form grid;
Execution in step S6: form the first side wall in described grid both sides, the formation of described the first side wall further comprises the oxidation of polysilicon gate and the deposit of silicon nitride;
Execution in step S7: in the Semiconductor substrate of described grid and described the first side wall both sides, carry out light dope and inject, to form the lightly-doped source drain structure;
Execution in step S8: carry out the source and leak injection, to form source-drain electrode;
Execution in step S9: make the preceding medium of metal, through hole, metal plug and metal level.
Alternatively, after described step S7 with described step S8 before, further comprise step S: form second side wall, the formation of described second side wall further comprises the deposit of oxide, the deposit of silicon nitride, and the etching of silicon nitride.
Alternatively, described N/P trap is to form the N trap by phosphorus doping, and mixing by boron forms the P trap.
Alternatively, described annealing temperature is 1050 ℃, and described annealing time is 30 seconds.
Alternatively, described gate insulator oxide layer be silicon oxynitride or silica one of them.
Alternatively, the preparation growing method of described gate insulator oxide layer is original position aqueous vapor growth pattern (In-suit Steam Generation, ISSG), ald, physical vapour deposition (PVD), chemical vapour deposition (CVD), or one of them of plasma enhanced chemical vapor deposition.
Alternatively, the deposition process of described polysilicon gate is one of them of PECVD, high density plasma chemical vapor deposition technology.
In sum, a kind of method of cmos device carrier mobility that improves of the present invention is by after the N/P trap forms, before the gate insulator oxide layer generates, described Semiconductor substrate is carried out annealing under the deuterium atmosphere, make that not only described semiconductor substrate surface is level and smooth, and described semiconductor substrate surface oxidation reaction is stablized; Simultaneously, in described annealing process, also activate the injection ion in the described N/P trap, and then improve the CMOS carrier mobility.
Description of drawings
Figure 1 shows that the present invention improves the flow chart of the method for cmos device carrier mobility.
Embodiment
By the technology contents, the structural feature that describe the invention in detail, reached purpose and effect, described in detail below in conjunction with embodiment and conjunction with figs..
See also Fig. 1, Figure 1 shows that a kind of flow chart that improves the method for cmos device carrier mobility of the present invention.Shown in improve the cmos device carrier mobility method may further comprise the steps,
Execution in step S1: carry out trap and inject formation N/P trap; In the present invention, include but not limited to form the N trap by phosphorus doping, mixing by boron forms the P trap;
Execution in step S2: in the deuterium atmosphere, carry out the annealing of N/P trap; Carry out in the deuterium atmosphere in the N/P trap annealing process, described semiconductor substrate surface is smooth-out, and described semiconductor substrate surface oxidation reaction is stablized.Simultaneously, in order to activate the injection ion in the described N/P trap in described annealing process, as the specific embodiment of the present invention, when described N/P trap was annealed in described deuterium atmosphere, preferably, described annealing temperature was 1050 ℃, and described annealing time is 30 seconds.Described Semiconductor substrate is a Si base substrate.
Execution in step S3: growth gate insulator oxide layer; Described gate insulator oxide layer includes but not limited to one of them of silicon oxynitride or silica.The preparation growing method of described gate insulator oxide layer includes but not limited to original position aqueous vapor growth pattern (In-suit Steam Generation, ISSG), ald, physical vapour deposition (PVD), chemical vapour deposition (CVD), or one of them of plasma enhanced chemical vapor deposition.
Execution in step S4: deposit polysilicon gate; The material layer of described polysilicon gate includes but not limited to polysilicon.The deposition process of described polysilicon gate includes but not limited to one of them of PECVD, high density plasma chemical vapor deposition technology.
Execution in step S5: the described polysilicon gate of etching, to form grid; Particularly, on described polysilicon gate, mask layer is set, for example, silicon nitride, and adopt the pecvd process deposit to form described silicon nitride, apply photoresist and patterning photoresist position then, utilize photoresist and silicon nitride subsequently, adopt the described gate material layers of plasma etching method etching to form the grid of device as mask with the definition grid.Remove remaining photoresist and hard mask silicon nitride then, cineration technics is adopted in the removal of photoresist, and hard mask silicon nitride adopts the phosphoric acid wet method to remove.
Execution in step S6: form the first side wall in described grid both sides, the formation of described the first side wall further comprises the oxidation of polysilicon gate and the deposit of silicon nitride;
Execution in step S7: in the Semiconductor substrate of described grid and described the first side wall both sides, carry out light dope and inject, to form the lightly-doped source drain structure;
Execution in step S8: carry out the source and leak injection, to form source-drain electrode;
Alternatively, after described step S7 with described step S8 before, can further comprise step S: form second side wall, the formation of described second side wall further comprises the deposit of oxide, the deposit of silicon nitride, and the etching of silicon nitride.
Execution in step S9: make the preceding medium of metal, through hole, metal plug and metal level.
In sum, a kind of method of cmos device carrier mobility that improves of the present invention is by after the N/P trap forms, before the gate insulator oxide layer generates, described Semiconductor substrate is carried out annealing under the deuterium atmosphere, make that not only described semiconductor substrate surface is level and smooth, and described semiconductor substrate surface oxidation reaction is stablized; Simultaneously, in described annealing process, also activate the injection ion in the described N/P trap, and then improve the CMOS carrier mobility.
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (7)
1. a method that improves the cmos device carrier mobility is characterized in that, described method comprises:
Execution in step S1: carry out trap and inject formation N/P trap;
Execution in step S2: in the deuterium atmosphere, carry out the annealing of N/P trap;
Execution in step S3: growth gate insulator oxide layer;
Execution in step S4: deposit polysilicon gate;
Execution in step S5: the described polysilicon gate of etching, to form grid;
Execution in step S6: form the first side wall in described grid both sides, the formation of described the first side wall further comprises the oxidation of polysilicon gate and the deposit of silicon nitride;
Execution in step S7: in the Semiconductor substrate of described grid and described the first side wall both sides, carry out light dope and inject, to form the lightly-doped source drain structure;
Execution in step S8: carry out the source and leak injection, to form source-drain electrode;
Execution in step S9: make the preceding medium of metal, through hole, metal plug and metal level.
2. the method for raising cmos device carrier mobility as claimed in claim 1, it is characterized in that, after described step S7 with described step S8 before, further comprise step S: form second side wall, the formation of described second side wall further comprises the deposit of oxide, the deposit of silicon nitride, and the etching of silicon nitride.
3. the method for raising cmos device carrier mobility as claimed in claim 1 is characterized in that, described N/P trap is to form the N trap by phosphorus doping, and mixing by boron forms the P trap.
4. the method for raising cmos device carrier mobility as claimed in claim 1 is characterized in that, described annealing temperature is 1050 ℃, and described annealing time is 30 seconds.
5. the method for raising cmos device carrier mobility as claimed in claim 1 is characterized in that, described gate insulator oxide layer is one of them of silicon oxynitride or silica.
6. the method for raising cmos device carrier mobility as claimed in claim 5, it is characterized in that, the preparation growing method of described gate insulator oxide layer is original position aqueous vapor growth pattern (In-suit Steam Generation, ISSG), ald, physical vapour deposition (PVD), chemical vapour deposition (CVD), or one of them of plasma enhanced chemical vapor deposition.
7. the method for raising cmos device carrier mobility as claimed in claim 1 is characterized in that, the deposition process of described polysilicon gate is one of them of PECVD, high density plasma chemical vapor deposition technology.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040110325A1 (en) * | 2002-12-03 | 2004-06-10 | Samsung Electronics Co., Ltd. | Method of forming gate oxide layer in semiconductor devices |
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040110325A1 (en) * | 2002-12-03 | 2004-06-10 | Samsung Electronics Co., Ltd. | Method of forming gate oxide layer in semiconductor devices |
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
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Application publication date: 20130724 |