CN103217610B - Device for capturing and processing transient events of power quality - Google Patents
Device for capturing and processing transient events of power quality Download PDFInfo
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- CN103217610B CN103217610B CN201310176546.8A CN201310176546A CN103217610B CN 103217610 B CN103217610 B CN 103217610B CN 201310176546 A CN201310176546 A CN 201310176546A CN 103217610 B CN103217610 B CN 103217610B
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Abstract
The invention relates to a device for capturing and processing transient events of power quality, belonging to the technical field of power supply management. The core component FPGA (Field Programmable Gate Array) of the device at least comprises a sampling control module, an effective value judging module, a variable judging module, a break variable judging module, a first internal memory control module, a transient event capturing control module and a second internal memory control module. According to the invention, the FPGA is reasonably used for creating the effective value judging module, the variable judging module and the break variable judging module parallel to the sampling control module, and the first and the second internal memory control modules performing respective functions are created to reasonably divide the work of first and the second internal memories, thereby being capable of simultaneously extracting and processing various transient event data with different attributes of power quality through a scientific internal operation structure, having the capability of processing high frequency transient data higher than 5 MHz, greatly improving the sampling rate and laying a foundation for satisfying high-precision monitoring of power quality.
Description
Technical field
The present invention relates to a kind of equipment for monitoring power quality, especially a kind of device being suitable for electric energy quality transient affair and catching and process, belongs to power supply management technical field.
Background technology
According to the applicant understood, at present in electric energy quality monitoring field, not yet realize voltage transient monitoring truly.
Retrieval find, application number be 201210262537.6 Chinese patent application disclose a kind of online equipment for monitoring power quality.It is introduced, this device can make existing common quality of power supply device possess high speed transient signal capture function.Be widely used in nonlinear-load and impact load, comprise the monitoring that conventional power quality index parameter is carried out in transition interference place as more serious in problems such as the equipment connection on electrical network and thunderbolts online, and when there is the anomalous event of high speed voltage transient, can automatic capturing the transient signal truly intactly recorded at that time, for the fault analysis of the device in supply line and equipment provides Data support.
In addition, application number be 201210247188.0 Chinese patent application disclose a kind of based on dual rate double-range sampling equipment for monitoring power quality.It is introduced, this device not only can be applicable to equipment for monitoring power quality, can also be used for super wide range electric energy meter or impact load electric energy meter, the high precision (especially small load) that it can make electric energy meter both keep stable state to measure, and does not lose again any impact electric energy.
But research and analyse known, there are the following problems in actual applications for above-mentioned prior art:
1, the problem of sampling rate: be limited to processing power, adopts general DSP or CPU cannot obtain high sampling rate; Once had and provide sampling rate to be the transient state solution of 1MHz by DSP, but under its hardware structure, be difficult to obtain higher sampling rate and processing power; Can be provided the transient state solution of sampling rate 2MHz by the scheme of FPGA and POWERPC, but still be difficult to the requirement meeting transient state monitoring, according to the standard of IEEE, the higher-order of oscillation transition dominant frequency that may occur in voltage transients is up to 5MHz.Too low sampling rate is not enough to support and is further analyzed the process of transient affair.For Lightning Over-voltage, the wave head time (being raised to the maximal value time from above freezing) of thunder-strike current is 2.6us, and according to the sampling rate of 2MHz, then overall process only can collect 5 sampled points, adopts the sampling rate of 1MHz then to count less.
2, the problem of sampling precision: the transient state solution of prior art is 12 precision solutions, because transient process itself is rich in high frequency harmonic components, when needs do the analysis of high precision entire spectrum to transient waveform, 12 sampling precisions are difficult to meet the requirement analyzed.
3, the problem of detection criteria: substantially only adopt a kind of fairly simple criterion in the transient state solution of prior art, such as effective value criterion or variable quantity criterion, be limited to processing power for Sudden Changing Rate criterion and be difficult to process.In the case, important transient affair of very likely failing to judge at the scene, reduction effective value or variable quantity criterion threshold then bring the possibility of erroneous judgement; Be difficult to provide reliable, comprehensive criterion to make the transient state monitoring device scope of application be subject to certain impact on on-the-spot transient state monitoring.
In a word, the problems referred to above create following impact to electric energy quality monitoring:
1) owing to not having device support, electric energy quality monitoring field stays cool substantially for the research of voltage transient event;
2) for voltage transient sensitive users, the device damage in production run and yields decline solution cannot be proposed;
3) professional user has certain understanding to the harm that voltage transient causes, but does not have corresponding monitoring device to provide Monitoring Data, and the reason be difficult to transient state occurs is further analyzed.
Therefore, be improve electric energy quality monitoring level, the solution of a kind of technical feasibility, reasonable price be provided for the seizure of electric energy quality transient affair and process, have very important significance.
Summary of the invention
Primary and foremost purpose of the present invention is: for above-mentioned prior art Problems existing, propose a kind of device being suitable for electric energy quality transient affair seizure and process with enough sampling rates, thus support is further analyzed to the process of transient affair.
The present invention puies forward further object and is: provide the device being suitable for electric energy quality transient affair seizure and process that a kind of sampling precision is high, have reasonable detection criteria, thus the electric energy quality transient affair realized truly catches.
In order to reach above-mentioned primary and foremost purpose, the present invention is suitable for the device of electric energy quality transient affair seizure and process with FPGA(field programmable gate array---Field-Programmable Gate Array) and be core devices, described FPGA at least contains
Sampling control module, in order to periodically to latch in internal data bus by the power quality data of AD acquisition circuit Gather and input;
The effective value data of superthreshold, in order to extract from internal data bus and to obtain effective value data, then after comparing with effective value threshold value, are transported to transient affair acquisition control module by effective value criterion module;
Variable quantity criterion module, obtains variable quantity data in order to extract also differential from internal data bus, then after comparing with variable quantity threshold value, the variable quantity data of superthreshold is transported to transient affair acquisition control module;
The Sudden Changing Rate data of superthreshold, in order to extract from internal data bus and to try to achieve Sudden Changing Rate data, then after comparing with Sudden Changing Rate threshold value, are transported to transient affair acquisition control module by Sudden Changing Rate criterion module;
First Memory control module, in order to control outside first internal memory, temporary sampling control module latches the original power quality data in internal data bus;
Transient affair acquisition control module, in order to read the original power quality data stored in the first Memory control module, is transported to the second Memory control module together with the effective value sent, variable quantity, Sudden Changing Rate data;
Second Memory control module, in order to control outside second internal memory, the various data of temporary transient affair acquisition control module conveying, and be transported to outer CPU.
During work, the sampled data that sampling control module of the present invention controls outside high-speed AD (analog to digital converter) is read in, and will read in that data are sent to effective value criterion by data bus, variable quantity criterion, Sudden Changing Rate criterion carry out parallel processing.Read in data after effective value criterion module, variable quantity criterion module, Sudden Changing Rate criterion module carry out necessary computing judgement, be sent to transient affair acquisition control module, by transient affair acquisition control module by these transient datas stored in the second external memory, notify that outer CPU reads by interaction logic control module subsequently, be further analyzed process.
The present invention not only rationally adopts FPGA to build the effective value criterion module parallel with sampling control module, variable quantity criterion module, Sudden Changing Rate criterion module (other parallel modules can also be increased as one sees fit), and construct that Each performs its own functions first, Memory control module, make outside first, second internal memory rational division of work, therefore the internal operation framework of science can be relied on, the electric energy transient affair data of the various different attribute of extraction process simultaneously, there is the ability being enough to process more than 5MHz high frequency transient data, increase substantially sampling rate, lay a good foundation for meeting high-precision electric energy quality monitoring.
In order to reach further object, described FPGA also reads control module containing time delay, in order to power quality data time delay one week after date of will be kept in by the first Memory control module, flows to Sudden Changing Rate criterion module as multilevel iudge foundation; Described Sudden Changing Rate criterion module in order to after extract the instantaneous value data in this cycle power quality data from internal data bus, using with read the difference of a upper cycle corresponding data of control module from time delay as Sudden Changing Rate data.Like this, the ingenious monitoring problem having properly settled Sudden Changing Rate in the quality of power supply that prior art cannot realize, avoiding failing to judge of important parameter in transient affair, having established solid foundation for effectively improving electric energy quality monitoring level.
Further, the input termination signal condition loop of described AD acquisition circuit, described signal condition loop is that three-phase voltage and voltage common terminal input terminal connect the Differential input circuit of corresponding binary channels amplifier integrated chip formation respectively by one group of resistance in series.
Further, the signal condition loop that described Differential input circuit is formed is exported by the binary channels in high-speed AD acquisition loop, is connected on corresponding FPGA input pin through bus; Described first internal memory and the second internal memory are connected respectively to corresponding FPGA and read and write on pin.
Further again, described second Memory control module is transported to outer CPU by outside interaction logic control module.
In a word, the present invention has divided each functional module for realizing electric energy quality transient affair seizure and processing, and establish data interaction between each functional module, logic exchange channels, not only practical, and there is compact overall structure, data stream and the remarkable advantage such as logic control process is clear, cost is low, Function Extension is convenient.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of one embodiment of the invention.
Fig. 2 is the structured flowchart of FPGA in Fig. 1 embodiment.
Fig. 3 is the circuit theory diagrams in signal condition loop in Fig. 1 embodiment.
Fig. 4 is the circuit theory diagrams of Fig. 1 embodiment high speed AD acquisition circuit.
Fig. 5 is the circuit theory diagrams of a FPGA part in Fig. 1 embodiment.
Fig. 6 is the circuit theory diagrams of FPGA another part in Fig. 1 embodiment.
Embodiment
Embodiment one
The present embodiment is suitable for the device of electric energy quality transient affair seizure and process as shown in Figure 1, forms primarily of fpga chip, the first internal memory, the second internal memory, high-speed AD acquisition loop, signal condition loop.Core devices FPGA wherein as shown in Figure 2, contains: sampling control module 1, in order to periodically to latch in internal data bus by the power quality data of AD acquisition circuit Gather and input; Effective value criterion module 2, in order to after comparing with effective value threshold value, to be transported to transient affair acquisition control module 7 by the effective value data of superthreshold from internal data bus extraction process effective value data; Variable quantity criterion module 3, in order to after comparing with variable quantity threshold value, to be transported to transient affair acquisition control module 7 by the variable quantity data of superthreshold from internal data bus extraction process variable quantity data; Sudden Changing Rate criterion module 4, Sudden Changing Rate criterion module is in order to after extracting the instantaneous value data in this cycle power quality data from internal data bus, using with read the difference of a upper cycle corresponding data of control module from time delay as Sudden Changing Rate data, the Sudden Changing Rate data of superthreshold are transported to transient affair acquisition control module 7; First Memory control module 8, in order to control outside first internal memory, by write memory control module 5, temporary sampling control module latches the original power quality data in internal data bus; Transient affair acquisition control module 7, in order to read the original power quality data stored in the first Memory control module, is transported to the second Memory control module 9 together with the effective value sent, variable quantity, Sudden Changing Rate data; Second Memory control module 9, in order to control outside second internal memory, the various data that temporary transient affair acquisition control module 7 is carried, and be transported to outer CPU by outside interaction logic control module 10; Control module 6 is read in time delay, in order to power quality data time delay one week after date of will be kept in by the first Memory control module 8, flows to Sudden Changing Rate criterion module 4 as multilevel iudge foundation.
During work, external voltage signal is reduced to the simulating signal that high-speed AD can access by signal condition loop; Simulating signal is converted to digital signal by high-speed AD acquisition loop; The FIFO that first internal memory is caught as transient affair; The transient data bag that second internal memory is caught as buffer memory reads for outer CPU.
The physical circuit in above-mentioned signal condition loop as shown in Figure 3, BNC connector BNC1 ~ BNC4 is as three-phase voltage input and voltage common terminal input terminal, this three-phase voltage and voltage common terminal input terminal meet corresponding binary channels amplifier integrated chip LF412 respectively by one group of resistance in series, form Differential input circuit.Many groups precision resister forms resistance pressure-dividing network, increases the insulation distance that resistance pressure-dividing network resistance number can increase signal input part and back-end circuit as required; Adopt binary channels amplifier integrated chip LF412 to form Differential input circuit together with resistance pressure-dividing network, can improve the ability of the anti-common mode interference of signal input part, the high voltage of front end input is transformed to the small-signal that directly can access high-speed AD after the conditioning of this circuit.
As shown in Figure 4, with ADI company High-Speed Double-Channel AD acquisition chip AD9268 for core devices, most high sampling rate supports 125M/S, and sampling precision is 16 in high-speed AD acquisition loop, adopts 1.8V low voltage power supply to reduce chip power-consumption; Meanwhile, this double channel A/D adopts independently data bus to export, to improve data throughput.
First internal memory adopts DDR2 sdram memory particle MT47H32M16, and its data width is 16, and its data throughput rate supports 400M/S.Second internal memory adopts DDR2 sdram memory particle MT47H32M16, is connected to FPGA, provides independently access control ability with said external internal memory 1 by respective independently data bus, address bus and control bus.
FPGA(programmable gate array) circuit theory diagrams as shown in Figure 5, adopt the 780 pin chip bgas of ALTERA company high power capacity fpga chip EP3C80F780, there is provided 429 user-programmable I/O pin and 81264 logical blocks, the component of its internal module as previously mentioned.The signal condition loop that Differential input circuit is formed is exported by the binary channels in high-speed AD acquisition loop, is connected on corresponding FPGA input pin, to provide higher data throughput through bus; First internal memory and the second internal memory are connected respectively to corresponding FPGA and read and write on pin, provide FPGA to read while write the ability of two panels internal memory.
When the device of this enforcement works, for power factor correction capacitor switching in supply line cause one low-frequency oscillation transient process---oscillation frequency is less than 5KHz usually, duration is 0.3-50ms, voltage magnitude is up to the rated voltage of 4 times, Sudden Changing Rate is responsive, and this transient process can be caught by Sudden Changing Rate criterion effectively.The device of the present embodiment can utilize the periodicity of power network signal, and the sampled point of the sampled point corresponding with one-period and this sampling period opposite position is made comparisons, if difference is greater than pre-set threshold value, then judges to there occurs transient process.This transient affair can coordinate catching this event by the Sudden Changing Rate criterion module 4 in Fig. 2, time delay one cycle read through model.Specifically, time delay one cycle read through model 6 reads 20 milliseconds (corresponding power network signal cycle) front data by multiport first Memory control module 8 from the first internal memory, and the current data that these data and sampling control module 1 obtain is compared, if the absolute value of difference is greater than pre-set threshold value, then export a pulse MUT_REQ by Sudden Changing Rate criterion module 4, notice transient affair acquisition control module 7, transient affair acquisition control module 7 reads the data of preset length from the first internal memory by multiport first Memory control module 8 subsequently, and write the second internal memory by multiport second Memory control module 9, after preservation terminates, outside interaction logic control module 10 notifies outer CPU reading and saving result.
In addition, when the controllable silicon false triggering of Power Electronic Circuit, also the transient process of electrical network can be caused---there is the punching of voltage point at normal sinusoidal waveform 120 degree or 60 degree of phase place places, its amplitude is relevant with the pulse relative time of duration and false triggering, effective value criterion and Sudden Changing Rate criterion are difficult to reliably catch this transient process, and variable quantity criterion can reliably catch this transient process.Because the differential signal that variable quantity asks for input signal obtains result, if the differential signal of respective signal is greater than setting threshold values, then thinks and have transient affair to occur.Because derivative constant can take the circumstances into consideration to dynamically arrange, therefore different acquisition sensitivities can be obtained.Specifically, above-mentioned transient process by Fig. 2 variable quantity criterion module 3 according to setting derivative constant, buffered data in module, and these data are compared with the current data obtained by sampling control module 1, if absolute difference is greater than pre-set threshold value, then export a pulsed D V_REQ by variable quantity criterion module 3 and notify transient affair acquisition control module 7, transient affair acquisition control module 7 reads the data of preset length by multiport first Memory control module 8 and is written to the second internal memory by multiport second Memory control module 9 from the first internal memory subsequently, after preservation terminates, outside interaction logic control module 10 notifies outer CPU reading and saving result.
Above embodiment is nonrestrictive.The technician of the industry should be appreciated that, under the prerequisite not departing from core architecture of the present invention and main method, the present invention also has various change and improvement, and these changes and improvement all fall in the claimed scope of the invention.
Claims (4)
1. be suitable for the device that electric energy quality transient affair catches and processes, be core devices with FPGA, it is characterized in that: described FPGA at least contains
Sampling control module, in order to periodically to latch in internal data bus by the power quality data of AD acquisition circuit Gather and input;
The effective value data of superthreshold, in order to extract from internal data bus and to obtain effective value data, then after comparing with effective value threshold value, are transported to transient affair acquisition control module by effective value criterion module;
Variable quantity criterion module, obtains variable quantity data in order to extract also differential from internal data bus, then after comparing with variable quantity threshold value, the variable quantity data of superthreshold is transported to transient affair acquisition control module;
The Sudden Changing Rate data of superthreshold, in order to extract from internal data bus and to try to achieve Sudden Changing Rate data, then after comparing with Sudden Changing Rate threshold value, are transported to transient affair acquisition control module by Sudden Changing Rate criterion module;
First Memory control module, in order to control outside first internal memory, temporary sampling control module latches the original power quality data in internal data bus;
Transient affair acquisition control module, in order to read the original power quality data stored in the first Memory control module, is transported to the second Memory control module together with the effective value sent, variable quantity, Sudden Changing Rate data;
Second Memory control module, in order to control outside second internal memory, the various data of temporary transient affair acquisition control module conveying, and be transported to outer CPU;
Described FPGA also reads control module containing time delay, in order to power quality data time delay one week after date of will be kept in by the first Memory control module, flows to Sudden Changing Rate criterion module as multilevel iudge foundation; Described Sudden Changing Rate criterion module in order to after extract the instantaneous value data in this cycle power quality data from internal data bus, using with read the difference of a upper cycle corresponding data of control module from time delay as Sudden Changing Rate data.
2. the device being suitable for electric energy quality transient affair and catching and process according to claim 1, it is characterized in that: the input termination signal condition loop of described AD acquisition circuit, input and voltage common terminal input terminal using the BNC1 ~ BNC4 of BNC connector as three-phase voltage, described signal condition loop is that three-phase voltage and voltage common terminal input terminal connect the Differential input circuit of corresponding binary channels amplifier integrated chip formation respectively by one group of resistance in series.
3. the device being suitable for electric energy quality transient affair and catching and process according to claim 2, it is characterized in that: the signal condition loop that described Differential input circuit is formed is exported by the binary channels of AD acquisition circuit, be connected on corresponding FPGA input pin through bus; Described first internal memory and the second internal memory are connected respectively to corresponding FPGA and read and write on pin.
4. the device being suitable for electric energy quality transient affair and catching and process according to claim 3, is characterized in that: described second Memory control module is transported to outer CPU by outside interaction logic control module.
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| KR100445636B1 (en) * | 2002-06-17 | 2004-08-25 | 삼성전자주식회사 | Computer system test device using FPGA and programmable memory modules and the test method thereof |
| JP3817555B2 (en) * | 2004-01-19 | 2006-09-06 | 株式会社エネゲート | Distribution line short circuit detector |
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Address after: Jiangning District of Nanjing City, Jiangsu province Rhine Road No. 699 211100 Patentee after: Nanjing can electric power automation Limited by Share Ltd Address before: Jiangning District of Nanjing City, Jiangsu province Rhine Road No. 699 211100 Patentee before: Nanjing Shining Electric Automation Co., Ltd. |