CN103208509A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN103208509A CN103208509A CN2012100122796A CN201210012279A CN103208509A CN 103208509 A CN103208509 A CN 103208509A CN 2012100122796 A CN2012100122796 A CN 2012100122796A CN 201210012279 A CN201210012279 A CN 201210012279A CN 103208509 A CN103208509 A CN 103208509A
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Abstract
The invention discloses a semiconductor device and a production method thereof. The semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer and a gate structure. The substrate is provided with a first doped region and a second doped region located on the first doped region, wherein the first doped region and the second doped region have a first electric conduction type, and at least one first groove and at least one second groove adjacent to the at least one first groove are arranged in the second doped region. The first epitaxial layer is arranged in the first groove and has a second electric conduction type. The second epitaxial layer is arranged in the second groove and has the first electric conduction type. The concentration of the second epitaxial layer is larger than that of the second doped region and is smaller than that of the first doped region. The gate structure is arranged above the second groove.
Description
Technical field
The invention relates to a kind of semiconductor device, special system has super semiconductor device and a manufacture method thereof that connects face (super junction) structure relevant for a kind of.
Background technology
Fig. 1 shows the rectilinear diffused MOS field-effect of existing N-type to answer transistor (vertical double-diffused MOSFET, VDMOSFET) generalized section.The rectilinear diffused MOS field-effect of N-type answers transistor 10 to comprise: semiconductor substrate and a grid structure that is located thereon.Have P mold base (base) district 102 of a N-type extension (epitaxy) drift (drift region) district 100 and the side of being located thereon at semiconductor-based the end and form P-N and connect face.Moreover 100 belows, N-type extension drift region have a drain region 106, and it is connected to a drain electrode 114.Have one source pole district 104 in the P mold base district 102, it is connected to one source pole electrode 112.Grid structure is made of a gate dielectric 108 and the gate electrode 110 that is located thereon.
Answer P-N in the transistor 10 to meet withstand voltage (the withstand voltage) of face in order to promote the rectilinear diffused MOS field-effect of N-type, must reduce the doping content of N-type extension drift region 100 and/or promote its thickness.Yet, when promoting P-N in the above described manner and connecing face withstand voltage, also can increase the conducting resistance (Ron) that the rectilinear diffused MOS field-effect of N-type is answered transistor 10 simultaneously.That is conducting resistance can be subjected to the doping content of N-type extension drift region and the restriction of thickness.
Have the super rectilinear diffused MOS field-effect that connects face (Super-junction) structure and answer transistor can improve the dopant concentration of N-type extension drift region, and then promote P-N and connect the withstand voltage of face, can avoid the increase of conducting resistance simultaneously.In a prior art, utilize multilayer epitaxial technology (multi-epi technology) to form super contact structure, above-mentioned multilayer epitaxial Technology Need carries out epitaxial growth, P type doping process and High temperature diffusion technology, and repeats above-mentioned technology.Therefore, above-mentioned multilayer epitaxial technology has that technology is complicated, manufacturing cost is high and component size is difficult to shortcomings such as micro.
Therefore, be necessary to seek a kind of semiconductor device with super contact structure, it can improve or address the above problem.
Summary of the invention
One embodiment of the invention provides a kind of semiconductor device, comprise: a substrate, one second doped region that has one first doped region and be located thereon, wherein first and second doped region has one first conduction type, and at least one second groove that wherein has at least one first groove and be adjacent in second doped region; One first epitaxial loayer is arranged in first groove, and has one second conduction type; One second epitaxial loayer is arranged in second groove, and has first conduction type, and wherein second epitaxial loayer has a doping content greater than the doping content of second doped region, and less than the doping content of first doped region; And a grid structure, be arranged at second groove top.
Another embodiment of the present invention provides a kind of manufacture method of semiconductor device, comprising: a substrate is provided, and one second doped region that has one first doped region and be located thereon, wherein first and second doped region has one first conduction type; In second doped region, form at least one first groove; Insert one first epitaxial loayer in first groove, wherein first epitaxial loayer has one second conduction type; In second doped region, form at least one second groove adjacent with first groove; Insert one second epitaxial loayer in second groove, wherein second epitaxial loayer has first conduction type, and second epitaxial loayer has a doping content greater than the doping content of second doped region, and less than the doping content of first doped region; And above second groove, form a grid structure.
Description of drawings
Fig. 1 shows the rectilinear diffused MOS field-effect of existing N-type to answer the transistor generalized section.
Fig. 2 A to Fig. 2 G shows the manufacture method generalized section of semiconductor device according to an embodiment of the invention.
Fig. 3 A to Fig. 3 E shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention.
Fig. 4 A to Fig. 4 F is the manufacture method generalized section that shows according to the present invention again the semiconductor device of another embodiment.
Drawing reference numeral:
Existing
The rectilinear diffused MOS field-effect of 10～N-type is answered transistor;
100～N-type extension drift region;
102～P mold base district;
104～source area;
106～drain region;
108～grid electrode layer;
110～gate electrode;
112～source electrode;
114～drain electrode.
Embodiment
20,20 ', 20 "～semiconductor device;
200～substrate;
200a～first doped region;
200b～second doped region;
201～interface;
202,210,218～hard mask;
202a, 210a, 218a～opening;
204～the first grooves;
206,214,222～insulation liner layer;
208,208 '～the first epitaxial loayer;
209,217,226～dielectric materials layer;
212～the second grooves;
216,216 '～the second epitaxial loayer;
216a～extension;
220～the 3rd grooves;
224～doping process;
224a～the 3rd doped region;
228～gate dielectric;
230～gate electrode;
232～wellblock;
234～source area;
A～active region.
Embodiment
Semiconductor device and the manufacture method thereof of the embodiment of the invention below are described.Yet, can understand embodiment provided by the present invention easily and only be used for explanation with the ad hoc approach making and use the present invention, be not in order to limit to scope of the present invention.
Please refer to Fig. 2 G, it shows semiconductor device generalized section according to an embodiment of the invention.The semiconductor device 20 of the embodiment of the invention comprises that the rectilinear diffused MOS field-effect with super contact structure answers transistor (VDMOSFET).Semiconductor device 20 comprises a substrate 200, and the one second doped region 200b that it has one first doped region 200a and is located thereon wherein has an interface 201 between the first doped region 200a and the second doped region 200b.Shown in Fig. 2 G, substrate 200 can comprise an active region (active region) A and distinguish (not illustrating) around the terminal (termination) of active region A.In one embodiment, it is formed thereon that active region A provides semiconductor element, and the termination environment is as the insulation between the different semiconductor devices.In one embodiment, the first doped region 200a can be made of a semi-conducting material that mixes, and the second doped region 200b then is made of the epitaxial loayer that mixes.In another embodiment, having the first doped region 200a of different levels of doping and the second doped region 200b is formed in the substrate 200 that same semi-conducting material constitutes.In the present embodiment, the first doped region 200a and the second doped region 200b have one first conduction type, and the first doped region 200a can be a heavily doped region, and the second doped region 200b can be a light doping section.
A plurality of second grooves 212 that have a plurality of first grooves 204 in the second doped region 200b and alternately arrange with first groove 204, make each second groove 212 adjacent with at least one first groove 204, perhaps each first groove 204 is adjacent with at least one second groove 212.Herein, for simplicity of illustration, two first grooves 204 that only show one second groove 212 and be adjacent.In the present embodiment, the bottom of first groove 204 and second groove 212 is above the interface 201 between the first doped region 200a and the second doped region 200b.Yet in other embodiments, first groove 204 and second groove 212 also can expose the interface 201 between the first doped region 200a and the second doped region 200b.
One first epitaxial loayer 208 is arranged in each first groove 204, and has one second conduction type, and wherein first epitaxial loayer 208 has a doping content greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.One second epitaxial loayer 216 is arranged in each second groove 212, and has first conduction type, and wherein second epitaxial loayer 216 has a doping content greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.
In the present embodiment, first conduction type is N-type, and second conduction type is the P type.Yet in other embodiments, first conduction type also can be the P type, and second conduction type is N-type.Therefore, first epitaxial loayer 208 with second conduction type lies in second epitaxial loayer 216 with first conduction type and forms super contact structure in the second doped region 200b.
One grid structure is arranged at each second groove, 212 top, and it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover the wellblock 232 with second conduction type is formed at the first half of each first epitaxial loayer 208, and extends in the second doped region 200b in first epitaxial loayer, 208 outsides.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, answers transistor and constitute a rectilinear diffused MOS field-effect with grid power structure and first doped region (as the drain region) 200a.
Please refer to Fig. 3 E, it shows semiconductor device generalized section according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 G use identical label and omit its explanation.In the present embodiment, second epitaxial loayer 216 in the semiconductor device 20 ' more comprises an extension 216a, is positioned to cover the second doped region 200b in the substrate 200.Specifically have one the 3rd groove 220 in the extension 216a of second epitaxial loayer 216 and expose first epitaxial loayer 208 corresponding to each first groove 204.Moreover, have the sidewall that one the 3rd doped region 224a is adjacent to each the 3rd groove 220 in the extension 216a of second epitaxial loayer 216, wherein the 3rd doped region 224a has second conduction type.In the present embodiment, the doping content of the 3rd doped region 224a is greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.Therefore, the 3rd doped region 224a with second conduction type has equally also formed super contact structure with the extension 216a with first conduction type.
One insulation liner layer 222 and a dielectric materials layer 226 are arranged in each the 3rd groove 220.In one embodiment, insulation liner layer 222 can comprise silica, and dielectric materials layer 226 can comprise silica or unadulterated polysilicon.
In the present embodiment, grid structure is arranged on the extension 216a, and corresponding to each second groove 212.Moreover wellblock 232 is formed at the first half of each the 3rd doped region 224a, and extends in the extension 216a in the 3rd doped region 224a outside.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, answers transistor and constitute a rectilinear diffused MOS field-effect with grid structure and first doped region (as the drain region) 200a.
Please refer to Fig. 4 F, the semiconductor device generalized section that it shows according to the present invention again another embodiment, the parts that wherein are same as Fig. 2 G use identical label and omit its explanation.In the present embodiment, semiconductor device 20 " in first epitaxial loayer 208 ' and second epitaxial loayer 216 ' insert in the first local groove 204 and second groove 212 respectively.For instance, first epitaxial loayer, 208 ' compliance is arranged at sidewall and the bottom of first groove 204, and second epitaxial loayer, 216 ' compliance is arranged at sidewall and the bottom of second groove interior 212.Moreover dielectric materials layer 209 and 217 is arranged at respectively in first groove 204 and second groove in 212, to fill up in first groove 204 and second groove 212.In one embodiment, dielectric materials layer 209 and 217 can comprise silica or unadulterated polysilicon.Therefore, first epitaxial loayer 208 ' with second conduction type forms super contact structure with second epitaxial loayer 216 ' with first conduction type in the second doped region 200b.
In the present embodiment, wellblock 232 is formed at the first half of each first epitaxial loayer 208 ', and extends in the second doped region 200b in first epitaxial loayer, the 208 ' outside.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, answers transistor and constitute a rectilinear diffused MOS field-effect with grid structure and first doped region (as the drain region) 200a.
Fig. 2 A to Fig. 2 G shows the manufacture method generalized section of semiconductor device 20 according to an embodiment of the invention.Please refer to Fig. 2 A, a substrate 200 is provided, the one second doped region 200b that it has one first doped region 200a and is located thereon wherein has an interface 201 between the first doped region 200a and the second doped region 200b.Substrate 200 can comprise an active region A and center on the termination environment (not illustrating) of active region A.In one embodiment, the first doped region 200a can be made of a semi-conducting material that mixes, and the second doped region 200b then sees through epitaxial growth, goes up the epitaxial loayer that forms a doping and constitutes at the semi-conducting material (that is the first doped region 200a) that mixes.In another embodiment, can carry out different doping processs to the substrate 200 that is constituted by the semiconductor material, to form the first doped region 200a and the second doped region 200b with different levels of doping within it, the doping process that wherein is used to form the first doped region 200a can carry out after follow-up formation transistor arrangement.In the present embodiment, the first doped region 200a and the second doped region 200b have one first conduction type, and the first doped region 200a can be a heavily doped region, and the second doped region 200b can be a light doping section.
Then, please refer to Fig. 2 A and Fig. 2 B, it illustrates the generation type of first groove 204.Can see through chemical vapour deposition (CVD) (chemical vapor deposition, CVD), above substrate 200, form a hard mask (hard mask, HM) 202, then carry out lithography process and etching technics, in the hard mask 202 of active region A, to form in order to define a plurality of opening 202a of first groove 204.Afterwards, carry out an anisotropic etching technics, to form a plurality of first grooves 204 in the second doped region 200b below opening 202a.In the present embodiment, the bottom of first groove 204 (for example, near interface 201) above the interface 201 between the first doped region 200a and the second doped region 200b.Yet in other embodiments, first groove 204 and second groove 212 also can expose the interface 201 between the first doped region 200a and the second doped region 200b.
In the present embodiment, can be after removing hard mask 202, see through CVD or thermal oxidation method, form an insulation liner layer (insulating liner) 206 in sidewall and the bottom compliance of each first groove 204.In an embodiment of the present invention, insulation liner layer 206 can be the oxide liner layer, and it can reduce the stress in the second doped region 200b.
Please refer to Fig. 2 C, after removing insulation liner layer 206, can in each first groove 204, insert one first epitaxial loayer 208 with one second conduction type.First epitaxial loayer 208 has a doping content greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.For instance, can see through epitaxial growth, form first epitaxial loayer 208 above substrate 200 and in each first groove 204.Afterwards, see through grinding technics again, for example (chemical mechanical polishing CMP), removes first epitaxial loayer 208 of substrate 200 tops to cmp.In the present embodiment, first conduction type is N-type, and second conduction type is the P type.Yet in other embodiments, first conduction type also can be the P type, and second conduction type is N-type.
Then, please refer to Fig. 2 D and Fig. 2 E, it illustrates the generation type of second groove 212.Above substrate 200, form a hard mask 210, its material and make can be similar or be same as hard mask 210 (being illustrated in Fig. 2 A).Then in the hard mask 210 of active region A, form in order to define a plurality of opening 210a of second groove 212.Afterwards, carry out an anisotropic etching technics, to form a plurality of second grooves 212 in the second doped region 200b below opening 210a.Second groove 212 and first groove 204 are alternately arranged, and make each second groove 212 adjacent with at least one first groove 204, and perhaps each first groove 204 is adjacent with at least one second groove 212.Herein, for simplicity of illustration, only show and two one second grooves 212 that first groove 204 is adjacent, shown in Fig. 2 D.
In the present embodiment, can be after removing hard mask 210, form an insulation liner layer 214 in sidewall and the bottom compliance of each second groove 212, to reduce the stress in the second doped region 200b, shown in Fig. 2 E.The material of insulation liner layer 214 and make can be similar or be same as insulation liner layer 206 (being illustrated in Fig. 2 B).
Please refer to Fig. 2 F, after removing insulation liner layer 214, can in each second groove 212, insert one second epitaxial loayer 216 with first conduction type.Second epitaxial loayer 216 has a doping content greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.The making of second epitaxial loayer 216 can be similar or be same as first epitaxial loayer 208 (being illustrated in Fig. 2 C).Therefore, first epitaxial loayer 208 with second conduction type lies in second epitaxial loayer 216 with first conduction type and forms super contact structure in the second doped region 200b.
Please refer to Fig. 2 G, can see through existing MOS technology, form a grid structure above each second groove 212, it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can have a wellblock 232 of second conduction type in the first half formation of each first epitaxial loayer 208, and extend in the second doped region 200b in first epitaxial loayer, 208 outsides.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish the making of semiconductor device 20, wherein source area 234, grid structure and first doped region (as the drain region) 200a constitute a rectilinear diffused MOS field-effect and answer transistor.
Fig. 3 A to Fig. 3 E shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 A to Fig. 2 G use identical label and omit its explanation.Please refer to Fig. 3 A, a substrate 200 is provided, the termination environment (not illustrating) that it can comprise an active region A and center on active region A.Moreover, the one second doped region 200b that substrate 200 has one first doped region 200a and is located thereon, and the first doped region 200a and the second doped region 200b have first conduction type.Has an interface 201 between the first doped region 200a and the second doped region 200b.A plurality of second grooves 212 that have a plurality of first grooves 204 in the second doped region 200b and alternately arrange with first groove 204, make each second groove 212 adjacent with at least one first groove 204, perhaps each first groove 204 is adjacent with at least one second groove 212.Herein, for simplicity of illustration, two first grooves 204 that only show one second groove 212 and be adjacent.One first epitaxial loayer 208 with second conduction type is arranged in each first groove 204.In one embodiment, said structure can be via carrying out as the fabrication schedule of Fig. 2 A to Fig. 2 E and is formed.
Then, can see through epitaxial growth, in each second groove 212, insert one second epitaxial loayer 216 with first conduction type, and in second groove 212, extend second epitaxial loayer 216 in substrate 200, to form an extension 216a who covers the second doped region 200b, as shown in Figure 3A.
Then, please refer to Fig. 3 A and Fig. 3 B, it illustrates the generation type of the 3rd groove 220.Above extension 216a, form a hard mask 218, its material and make can be similar or be same as hard mask 210 (being illustrated in Fig. 2 A).Then in the hard mask 218 of active region A, form in order to define a plurality of opening 218a of the 3rd groove 220.Afterwards, carry out an anisotropic etching technics, to form a plurality of the 3rd grooves 220 in second epitaxial loayer 216 below opening 218a (that is extension 216a).The 3rd groove 220 is substantially in alignment with first groove 204 and expose first epitaxial loayer 208 in first groove 204, shown in Fig. 3 B.
Referring again to Fig. 3 B, in the present embodiment, can be after removing hard mask 218, sidewall and bottom compliance at each the 3rd groove 220 form an insulation liner layer 222, to reduce the stress in the extension 216a, and can be as the screen oxide (pre-implant oxide) of follow-up doping process, to reduce channelling effect.The material of insulation liner layer 222 and make can be similar or be same as insulation liner layer 206 (being illustrated in Fig. 2 B).
Please refer to Fig. 3 C, can carry out a doping process 224, for example ion cloth is planted, to form a plurality of the 3rd doped region 224a in the extension 216a of second epitaxial loayer 216, wherein each the 3rd doped region 224a is adjacent to a sidewall of each the 3rd groove 220, and has second conduction type.In the present embodiment, the doping content of the 3rd doped region 224a is greater than the doping content of the second doped region 200b, and less than the doping content of the first doped region 200a.Therefore, the 3rd doped region 224a with second conduction type forms super contact structure with the extension 216a with second epitaxial loayer 216 of first conduction type.
Please refer to Fig. 3 D, in each the 3rd groove 220, insert a dielectric materials layer 226.For instance, can see through chemical vapor deposition (CVD) technology, reach at the extension 216a of second epitaxial loayer 216 and form a dielectric materials layer 226, for example silica or unadulterated polysilicon in each the 3rd groove 220.Afterwards, remove dielectric materials layer 226 on the extension 216a of second epitaxial loayer 216 with cmp (CMP) technology again.
Please refer to Fig. 3 E, can see through existing MOS technology, the extension 216a of second epitaxial loayer 216 forms a grid structure above each second groove 212, and it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can have a wellblock 232 of second conduction type in the first half formation of each the 3rd doped region 224a, and extend in the extension 216a in the 3rd doped region 224a outside.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish the making of semiconductor device 20 ', wherein source area 234, grid structure and first doped region (as the drain region) 200a constitute a rectilinear diffused MOS field-effect and answer transistor.
Fig. 4 A to Fig. 4 F shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention, and the parts system that wherein is same as Fig. 2 A to Fig. 2 G uses identical label and omits its explanation.Please refer to Fig. 4 A, a substrate 200 is provided, the termination environment (not illustrating) that it can comprise an active region A and center on active region A.Moreover, the one second doped region 200b that substrate 200 has one first doped region 200a and is located thereon, and the first doped region 200a and the second doped region 200b have first conduction type.Has an interface 201 between the first doped region 200a and the second doped region 200b.Have a plurality of first grooves 204 in the second doped region 200b.In one embodiment, said structure can be via carrying out as the fabrication schedule of Fig. 2 A to Fig. 2 B and is formed.Then, can see through epitaxial growth, form one first epitaxial loayer 208 ' with second conduction type at the sidewall of each first groove 204 and bottom compliance.
Please refer to Fig. 4 B, in each first groove 204, insert a dielectric materials layer 209.For instance, chemical vapor deposition (CVD) technology be can see through, a dielectric materials layer 209, for example silica or unadulterated polysilicon in substrate 200 and each first groove 204, formed.Afterwards, remove dielectric materials layer 209 in the substrate 200 with cmp (CMP) technology again.
Please refer to Fig. 4 C, carry out the described fabrication schedule as Fig. 2 D, form a plurality of second grooves 212 in the second doped region 200b below the opening 210a of hard mask 210.Second groove 212 and first groove 204 are alternately arranged.Herein, for simplicity of illustration, only show and two one second grooves 212 that first groove 204 is adjacent.
Please refer to Fig. 4 D, carry out the described fabrication schedule as Fig. 2 E, form an insulation liner layer 214 in sidewall and the bottom compliance of each second groove 212, to reduce the stress in the second doped region 200b.
Please refer to Fig. 4 E, can see through epitaxial growth, forming one second epitaxial loayer, 216 ' its production method with first conduction type in the sidewall of each second groove 212 and bottom compliance can be similar or be same as first epitaxial loayer 208 '.Afterwards, insert a dielectric materials layer 217 in each first groove 204, its material and production method can be similar or be same as dielectric materials layer 209.
Please refer to Fig. 4 F, can see through existing MOS technology, form a grid structure above each second groove 212, it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can form the wellblock 232 with second conduction type in the second doped region 200b outside the first half of each first epitaxial loayer 208 '.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish semiconductor device 20 " making, wherein source area 234, grid structure and first doped region (as the drain region) 200a constitute a rectilinear diffused MOS field-effect and answer transistor.
According to above-described embodiment, because N-type doping content regional and the p type island region territory reaches charge balance (charge balance) in the super contact structure that can constitute by control first epitaxial loayer 208 or 208 ' and second epitaxial loayer 216 or 216 ', therefore above-mentioned super contact structure can be formed at light doping section (namely, the second doped region 200b) in, and then promote rectilinear diffused MOS field-effect and answer that P-N connects the withstand voltage of face in the transistor, can avoid the increase of conducting resistance simultaneously.
Moreover, according to above-described embodiment, only need carry out the epitaxial growth of secondary, just can form the super contact structure of the P-N column of alternately arranging in a plurality of grooves in light doping section, so can simplify technology, reduce manufacturing cost and dwindle component size.
In addition, according to above-described embodiment, owing to can above a plurality of grooves, form extra super contact structure, so need not to increase gash depth and just can further promote P-N and connect the withstand voltage of face, and can not increase the difficulty in process degree because of the etching deep trench.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, any under technical staff in the technical field, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (26)
1. a semiconductor device is characterized in that, described semiconductor device comprises:
One substrate, one second doped region that has one first doped region and be located thereon, wherein said first and described second doped region have one first conduction type, and at least one second groove that has at least one first groove in wherein said second doped region and be adjacent;
One first epitaxial loayer is arranged in described first groove, and has one second conduction type;
One second epitaxial loayer is arranged in described second groove, and has described first conduction type, and wherein said second epitaxial loayer has a doping content greater than the doping content of described second doped region, and less than the doping content of described first doped region; And
One grid structure is arranged at described second groove top.
2. semiconductor device as claimed in claim 1, it is characterized in that, described second epitaxial loayer more comprises an extension, be positioned at and cover described second doped region in the described substrate, described extension has one the 3rd groove and exposes described first epitaxial loayer, and have the sidewall that one the 3rd doped region is adjacent to described the 3rd groove, described the 3rd doped region has described second conduction type.
3. semiconductor device as claimed in claim 2 is characterized in that, the doping content of described the 3rd doped region is greater than the doping content of described second doped region, and less than the doping content of described first doped region.
4. semiconductor device as claimed in claim 2 is characterized in that, described semiconductor device more comprises a dielectric materials layer, is arranged in described the 3rd groove.
5. semiconductor device as claimed in claim 4 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
6. semiconductor device as claimed in claim 1 is characterized in that, described first conduction type is N-type, and described second conduction type is the P type.
7. semiconductor device as claimed in claim 1 is characterized in that, described second doped region is made of an epitaxial loayer.
8. semiconductor device as claimed in claim 1 is characterized in that, described first groove and described second groove expose the interface between described first doped region and described second doped region.
9. semiconductor device as claimed in claim 1 is characterized in that, described first epitaxial loayer has a doping content greater than the doping content of described second doped region, and less than the doping content of described first doped region.
10. semiconductor device as claimed in claim 1 is characterized in that, the described first epitaxial loayer compliance is arranged on the sidewall and a bottom of described first groove, and the described second epitaxial loayer compliance is arranged on the sidewall and a bottom of described second groove.
11. semiconductor device as claimed in claim 1 is characterized in that, described semiconductor device more comprises a dielectric materials layer, is arranged in described first groove and described second groove.
12. semiconductor device as claimed in claim 11 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
13. the manufacture method of a semiconductor device is characterized in that, the manufacture method of described semiconductor device comprises:
One substrate is provided, one second doped region that has one first doped region and be located thereon, wherein said first and described second doped region have one first conduction type;
In described second doped region, form at least one first groove;
Insert one first epitaxial loayer in described first groove, wherein said first epitaxial loayer has one second conduction type;
In described second doped region, form at least one second groove adjacent with described first groove;
In described second groove, insert one second epitaxial loayer, wherein said second epitaxial loayer has described first conduction type, and described second epitaxial loayer has a doping content greater than the doping content of described second doped region, and less than the doping content of described first doped region; And
Above described second groove, form a grid structure.
14. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, the manufacture method of described semiconductor device more comprises:
In described second groove, extend described second epitaxial loayer in described substrate and cover described second doped region;
In described suprabasil described second epitaxial loayer, form one the 3rd groove and expose described first epitaxial loayer; And
Form one the 3rd doped region in described second epitaxial loayer, wherein said the 3rd doped region is adjacent to a sidewall of described the 3rd groove, and has described second conduction type.
15. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, the doping content of described the 3rd doped region is greater than the doping content of described second doped region, and less than the doping content of described first doped region.
16. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, the manufacture method of described semiconductor device more is included in and forms before described the 3rd doped region, forms an insulation liner layer in described the 3rd groove.
17. the manufacture method of semiconductor device as claimed in claim 14 is characterized in that, the manufacture method of described semiconductor device more is included in described the 3rd groove and inserts a dielectric materials layer.
18. the manufacture method of semiconductor device as claimed in claim 17 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
19. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, described first conduction type is N-type, and described second conduction type is the P type.
20. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, described second doped region is made of an epitaxial loayer.
21. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, described first groove and described second groove expose the interface between described first doped region and described second doped region.
22. the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, described first epitaxial loayer has a doping content greater than the doping content of described second doped region, and less than the doping content of described first doped region.
23. the manufacture method of semiconductor device as claimed in claim 13, it is characterized in that, the manufacture method of described semiconductor device more is included in to be inserted before described first epitaxial loayer, in described first groove, form an insulation liner layer, or before inserting described second epitaxial loayer, in described second groove, form an insulation liner layer.
24. the manufacture method of semiconductor device as claimed in claim 13, it is characterized in that, the described first epitaxial loayer compliance is formed on the sidewall and a bottom of described first groove, and the described second epitaxial loayer compliance is formed on the sidewall and a bottom of described second groove.
25. the manufacture method of semiconductor device as claimed in claim 24 is characterized in that, the manufacture method of described semiconductor device more is included in described first groove and described second groove and inserts a dielectric materials layer respectively.
26. the manufacture method of semiconductor device as claimed in claim 25 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020001636A1 (en) * | 2018-06-30 | 2020-01-02 | Jin Wei | Semiconductor device, semiconductor apparatus and method of manufacturing the same |
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|---|---|---|---|---|
| US20040238844A1 (en) * | 2001-09-19 | 2004-12-02 | Kenichi Tokano | Semiconductor device and method of manufacturing the same |
| JP2006294968A (en) * | 2005-04-13 | 2006-10-26 | Shindengen Electric Mfg Co Ltd | Semiconductor device and its manufacturing method |
| JP2008091450A (en) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | Semiconductor element |
| CN101950759A (en) * | 2010-08-27 | 2011-01-19 | 电子科技大学 | Super Junction VDMOS device |
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| US20040238844A1 (en) * | 2001-09-19 | 2004-12-02 | Kenichi Tokano | Semiconductor device and method of manufacturing the same |
| JP2006294968A (en) * | 2005-04-13 | 2006-10-26 | Shindengen Electric Mfg Co Ltd | Semiconductor device and its manufacturing method |
| JP2008091450A (en) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | Semiconductor element |
| CN101950759A (en) * | 2010-08-27 | 2011-01-19 | 电子科技大学 | Super Junction VDMOS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020001636A1 (en) * | 2018-06-30 | 2020-01-02 | Jin Wei | Semiconductor device, semiconductor apparatus and method of manufacturing the same |
| US11476325B2 (en) | 2018-06-30 | 2022-10-18 | Jin WEI | Semiconductor device |
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| CN103208509B (en) | 2015-08-12 |
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