CN103996708B - High-voltage semiconductor element and its manufacturing method - Google Patents
High-voltage semiconductor element and its manufacturing method Download PDFInfo
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- CN103996708B CN103996708B CN201310053083.6A CN201310053083A CN103996708B CN 103996708 B CN103996708 B CN 103996708B CN 201310053083 A CN201310053083 A CN 201310053083A CN 103996708 B CN103996708 B CN 103996708B
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- 238000000034 method Methods 0.000 claims description 45
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- 230000008569 process Effects 0.000 claims description 27
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- 238000005468 ion implantation Methods 0.000 claims description 13
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a kind of high-voltage semiconductor element and its manufacturing methods, wherein the high-voltage semiconductor element includes: semiconductor substrate, has one first conduction type；Grid structure, on one of the semiconductor substrate；A pair of of spacer, is respectively arranged in the one side wall of the grid structure, and wherein this is the compound spacer for including the first insulation spacer for contacting the grid structure, dummy structure and the second insulation spacer to one of spacer；Drift region is set in one of the semiconductor substrate and is located at one of the grid structure and the lower section to one of spacer, has the second conduction type in contrast to first conduction type；And a pair of of doped region, be respectively arranged in one of the semiconductor substrate of the opposite side of the grid structure, wherein this has second conduction type to doped region, and this to doped region first is that being set in the drift region.
Description
Technical Field
The present invention relates to semiconductor fabrication, and more particularly, to a high voltage semiconductor device and a method for fabricating the same.
Background
In recent years, as the demand for high voltage devices (high voltage devices) increases, the research on the technology of high voltage metal oxide semiconductor field effect transistors (high voltage MOSFETs) used in the high voltage devices has been increasing.
In many types of high voltage mosfet technology, it is common to use a double-diffused structure (double-diffused structure) at the source and drain of the mosfet. Such a double diffusion structure can make the MOSFET have a high breakdown voltage (high breakdown voltage). The mosfet with the double diffused drain structure can be used as a high voltage device with a high operating voltage such as 10V-30V.
However, with the trend of scaling in semiconductor manufacturing technology, the size of high voltage devices is also gradually scaled. Therefore, there is a need for a high voltage semiconductor device with a double diffused structure with a more scalable size to meet the trend and demand of device scaling. .
Disclosure of Invention
In view of the above, the present invention provides a high voltage semiconductor device and a method for fabricating the same, and provides a semiconductor device and a method for fabricating the same
According to one embodiment, the high voltage semiconductor device of the present invention comprises: a semiconductor substrate having a first conductivity type; a gate structure on a portion of the semiconductor substrate; a pair of spacers respectively disposed on a sidewall of the gate structure, wherein one of the spacers is a composite spacer, and the composite spacer includes a first insulating spacer contacting the gate structure, a dummy gate structure and a second insulating spacer; a first drift region disposed in a portion of the semiconductor substrate and located under a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite the first conductivity type; and a pair of doped regions disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, respectively, wherein the pair of doped regions have the second conductivity type and one of the pair of doped regions is disposed in the first drift region. According to another embodiment, a method for manufacturing a high voltage semiconductor device of the present invention comprises: providing a semiconductor substrate, wherein the semiconductor substrate has a first conductive type; forming a drift region in a portion of the semiconductor substrate, the drift region having a second conductivity type opposite the semiconductor substrate; forming a gate structure and a dummy gate structure on the semiconductor substrate, wherein the gate structure partially covers the drift region and the dummy gate structure is located above the drift region; forming a first insulating spacer and a pair of second insulating spacers, wherein the first insulating spacer is located between the gate structure and the dummy gate structure, and the second insulating spacers are respectively located on a sidewall of the dummy gate structure and a sidewall of the gate structure; performing an ion implantation process to form two doped regions in the semiconductor substrate adjacent to the second insulating spacers, wherein the doped regions have the second conductivity type and one of the doped regions is located in the drift region; and performing an annealing process.
According to another embodiment, a method for manufacturing a high voltage semiconductor device of the present invention comprises: providing a semiconductor substrate, wherein the semiconductor substrate has a first conductive type; forming a pair of drift regions in two different portions of the semiconductor substrate, the drift regions having a second conductivity type opposite the semiconductor substrate; forming a gate structure and a plurality of dummy gate structures on the semiconductor substrate, wherein the gate structure partially covers a portion of the drift regions, and the dummy gate structures are respectively located on one of the drift regions; forming a first insulating spacer and a pair of second insulating spacers, wherein the first insulating spacer is located between the gate structure and the dummy gate structures, and the second insulating spacers are located on one side wall of the dummy gate structures; performing an ion implantation process to form two doped regions in the semiconductor substrate adjacent to the second insulating spacers, wherein the doped regions have the second conductivity type and are respectively located in one of the drift regions; and performing an annealing process.
The high voltage semiconductor device and the related manufacturing method thereof in the embodiments of the invention have the advantages of shrinking the size of the device and reducing the manufacturing cost, and thus the related problems of shrinking the size and reducing the manufacturing cost of the high voltage semiconductor device in the prior art can be solved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic diagram illustrating a cross-sectional view of a high voltage semiconductor device according to an embodiment of the invention.
Fig. 2 is a schematic diagram illustrating a top view of the high voltage semiconductor device shown in fig. 1.
Fig. 3, 5, 7 and 9 are a series of schematic diagrams respectively illustrating cross-sectional views at different stages in a method for manufacturing a high voltage semiconductor device according to an embodiment of the present invention.
Fig. 4, 6, 8 and 10 are a series of schematic diagrams respectively illustrating top views at different stages in a method for manufacturing a high voltage semiconductor device according to an embodiment of the present invention.
FIG. 11 is a cross-sectional view of a high voltage semiconductor device according to another embodiment of the present invention.
Fig. 12 is a schematic diagram showing a top view of the high voltage semiconductor device shown in fig. 11.
FIG. 13 is a cross-sectional view of a high voltage semiconductor device according to another embodiment of the present invention.
Fig. 14 is a schematic diagram showing a top view of the high voltage semiconductor device shown in fig. 13.
FIG. 15 is a cross-sectional view of a high voltage semiconductor device according to another embodiment of the present invention.
Fig. 16 is a schematic diagram showing a top view of the high voltage semiconductor device shown in fig. 15.
FIG. 17 is a cross-sectional view of a high voltage semiconductor device according to another embodiment of the present invention.
Fig. 18 is a schematic diagram showing a top view of the high voltage semiconductor device shown in fig. 17.
FIG. 19 is a diagram illustrating electrical connections of a high voltage semiconductor device according to an embodiment of the present invention.
FIG. 20 is a cross-sectional view of a high voltage semiconductor device according to another embodiment of the present invention.
The reference numbers illustrate:
10-high voltage semiconductor device
12 to semiconductor substrate
13 to isolation structure
14 to gate dielectric layer
16-gate electrode layer
18-insulating spacer
20-drift region
22-doped region
100 to high voltage semiconductor device
102 to semiconductor substrate
104 to isolation structure
106 to drift region
108 to dielectric layer
110 to conductive layer
112 to insulating spacer
114 to insulating spacer
120-ion implantation process
122-doped region
200 to high voltage semiconductor device
202 to semiconductor substrate
204 to buried layer
206-epitaxial semiconductor layer
208 to the body region
210-drift region
212-doped region
214-doped region
216-doped region
218 dielectric layer
220 to conductive layer
222-insulating spacer
224 to insulating spacer
230-conductive contact
A1-active region
A2-active region
D1-distance
D2-distance
D3-distance
D4-distance
D5-distance
D6-distance
DD-double diffusion structure
S-grid structure
S1-grid structure
S2 false gate structure
C1-line width/feature size
C2-line width/feature size
P-pitch
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
Referring to fig. 1 and fig. 2, a top view and a cross-sectional view of a high voltage semiconductor device according to an embodiment of the invention are shown, wherein fig. 1 shows a cross-sectional view along line 1-1 in fig. 2. In the present embodiment, the high voltage semiconductor device has a double-diffused structure (double-diffused structure), and thus is suitable for a high voltage operation such as 10V-30V.
Referring to fig. 1 and 2, a high voltage semiconductor device 10 is shown, which includes a semiconductor substrate 12, a gate structure S disposed on a portion of the semiconductor substrate 12, a double diffusion structure DD disposed in the semiconductor substrate 12 under both sides of the gate structure S, and a conductive contact 30 disposed on a portion of the double diffusion structure DD.
With continued reference to fig. 1 and 2, an isolation structure 13 is disposed in the semiconductor substrate 12, wherein, in a top view, the isolation structure 13 (see fig. 2) surrounds a portion of the semiconductor substrate 12 and defines an active region a1 for disposing semiconductor devices, and the gate structure S is formed on the portion of the semiconductor substrate 12 in the active region a 1. Referring to fig. 1, the gate structure S includes a gate dielectric layer 14 and a gate electrode layer 16 sequentially stacked on a semiconductor substrate 12. Insulating spacers (insulating spacers) 18 are formed on opposite sides of the gate electrode layer 16 and the gate dielectric layer 14 of the gate structure S, and the double diffusion structures DD include a drift region (drift region)20 formed in the semiconductor substrate 12 and a doped region 22 disposed in a portion of the drift region 20, wherein the drift region 20 is partially disposed under the gate structure S, and the doped region 22 serves as a source/drain of the high voltage semiconductor device 10. In one embodiment, the semiconductor substrate 12 is a first conductive type substrate such as a P-type silicon substrate, and the drift region 20 and the doped region 22 are regions of a second conductive type opposite to the first conductive type, such as an N-type doped region, wherein the doped region 22 has a dopant concentration of the second conductive type more than 10 times that of the drift region 20. And a conductive contact 30 is formed on a portion of the doped region 22.
In the embodiment shown in fig. 1 and 2, the gate structure S, the doped region 22, the drift region 20 and the conductive contact 30 are formed by different photolithography processes (not shown) to form different patterned mask layers or photoresist layers (not shown) and an etching process or an ion implantation process (not shown). Therefore, in order to ensure that the high voltage semiconductor device 10 as shown in FIGS. 1 and 2 can have a high breakdown voltage behavior, such as between 10V-30V. Therefore, it is required to maintain a specific distance D1 between the doped region 22 and a sidewall of the gate structure S adjacent thereto and a specific distance D2 between the doped region 22 and a sidewall of the conductive contact 30 adjacent thereto during the design process, so as to control the accuracy of the photolithography process for forming the gate structure S, the doped region 22, the drift region 20 and the conductive contact 30, and thereby ensure the high breakdown voltage performance of the formed high voltage semiconductor device 10, and the doped region 22 and the drift region 20 in the high voltage semiconductor device 10 are formed by two different photolithography processes (not shown) to form different patterned mask layers or photoresist layers (not shown) and two different ion implantation processes (not shown), thereby increasing the manufacturing cost of the high voltage semiconductor device 10. Thus, the aforementioned specific spacings D1 and D2 and the associated fabrication of the doped region 22 and the drift region 20 are not conducive to the scaling of the high voltage semiconductor device 10 and the reduction of the manufacturing cost.
Referring to fig. 3 to 10, a method for manufacturing a high voltage semiconductor device 100 according to another embodiment of the present invention is shown, wherein fig. 3, 5, 7 and 9 respectively show cross sections of the high voltage semiconductor device 100 in different manufacturing stages, fig. 4, 6, 8 and 10 respectively show top views of the high voltage semiconductor device 100 in different manufacturing stages, and fig. 3, 5, 7 and 9 respectively show cross sections along line 3-3 in fig. 4, line 5-5 in fig. 6, line 7-7 in fig. 8 and line 9-9 in fig. 10. The high voltage semiconductor device 100 and the related manufacturing method thereof in the present embodiment have the advantages of shrinking the device size and reducing the manufacturing cost, so that the problems related to the shrinking size and the reduction of the manufacturing cost of the high voltage semiconductor device 10 shown in fig. 1 and 2 can be solved.
Referring to fig. 3 and 4, a semiconductor substrate 102, such as a first conductivity type semiconductor substrate of a P-type silicon substrate, is provided. Next, an isolation structure 104 is formed in a portion of the semiconductor substrate 102 by a process (not shown) such as shallow trench isolation (shallow trench isolation) or field oxidation (field oxidation). As shown in the top view of fig. 4, the isolation structure 104 has a top view that is generally rectangular, while the cross-section of fig. 3 shows two portions of the isolation structure 104. An active region a2 for forming a high voltage semiconductor device 100 (see fig. 9 and 10) is defined in the isolation structure 104 formed in a portion of the semiconductor substrate 102. Next, appropriate patterning of the mask layer and ion implantation (both not shown) are performed to form two drift regions 106 in the semiconductor substrate 102 in the active region a2, which are separated from the semiconductor substrate 102. In one embodiment, the drift regions 106 may be regions of a second conductivity type opposite to the first conductivity type, such as an N-type doped region.
Referring to fig. 5 and 6, a dielectric material layer and a conductive layer (both not shown) are sequentially formed overlying the semiconductor substrate 102 and then patterned, thereby obtaining a gate structure S1 and two dummy gate structures S2 on the semiconductor substrate 102 in the active region a2 as shown in fig. 5 and 6. As shown in fig. 5 and 6, the gate structures S1 are located on the semiconductor substrate 102 in the active region a2 and partially cover a portion of the drift regions 106 adjacent thereto, and the dummy gate structures S2 are located adjacent to a side of the gate structure S1 and on a portion of each drift region 106, respectively, and the gate structure S1 and the dummy gate structure S2 are a stripe structure in a top view. Here, the gate structures S1 and the dummy gate structure S2 respectively include a dielectric layer 108 and a conductive layer 110 patterned. In one embodiment, the dielectric layer 108 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, and the conductive layer 110 comprises a conductive material such as polysilicon or metal. Furthermore, the gate structure S1 and the dummy gate structure S2 have a line width or a feature size C1 and C2, respectively, and a ratio (C1: C2) between C1 and C2 is about 5:1 to 20:1, and a distance P between the dummy gate structure S2 and the gate structure S1 is about 5:1 to 20:1, respectively, and a ratio (C1: P) between the dummy gate structure S1 and the dummy gate structure S2 is about 5:1 to 20: 1. The gate structure S1 serves as the main gate of the high voltage semiconductor device, and the dummy gate structure S2 serves as a portion of a composite spacer (see fig. 7-10).
Referring to fig. 7 and 8, an insulating material (not shown) such as silicon oxide is deposited overlying the structure shown in fig. 5 and 6 and fills the space between the gate structure S1 and the dummy gate structure S2. An etching process (not shown) such as dry etching is then performed on the layer of insulating material to form an insulating spacer 112 between the gate structure S1 and the dummy gate structure S2 and another insulating spacer 114 on the sidewalls of the dummy gate structure S2. After the formation of the insulating spacers 112 and 114, the top surfaces of the gate structure S1 and the dummy gate structure S2 are exposed. Here, the insulating spacer 112 has a rectangular cross-sectional shape, and the insulating spacer 114 has a sector-like cross-sectional shape.
Next, an ion implantation process 120 is performed, and the gate structures S1 and the dummy gate structure S2 and the insulating spacers 112 and 114 are used as a layout mask, so as to form a self-aligned (self-aligned) doped region 122 on one side of the insulating spacer 114 in the drift region 106. The insulating spacer 112 formed between the gate structure S1 and the dummy gate structure S2 prevents the formation of another undesired doped region in the ion implantation process 120 in the drift region 106 located below and between the gate structure S1 and the dummy gate structure S2.
In one embodiment, the ion implantation process 120 uses dopants of the same second conductivity type as the drift region 106 to form a doped region having the same second conductivity type as the drift region 106, such as an N-type doped region, and the doped region 122 has a dopant concentration about 10 times higher than that of the drift region 106 to serve as a source region or a drain region.
Referring to fig. 9 and 10, after an annealing process (not shown) is performed, a high voltage semiconductor device 100 is obtained. As shown in fig. 9, after the anneal process is performed, the doped region 122 may further diffuse to the bottom of the insulating spacer 114. Next, a conductive contact 130 is formed on a portion of the doped region 122. In one embodiment, the conductive contacts 130 may be a metal material such as tungsten, aluminum, copper, and the like. Here, as shown in fig. 9, the dummy gate structure S2 and the insulating spacers 112 and 114 located at two sides of the gate structure S1 form a composite spacer for the high voltage semiconductor device 100, and the doped region 112 may be spaced apart from a sidewall of the gate structure S1 by a distance D3 and the doped region 112 may be spaced apart from a sidewall of the conductive contact 130 by a distance D4. Compared to the distance D1 between the gate structure S and the doped region 22 and the distance D2 between the doped region 22 and the conductive contact 30 in the structures shown in fig. 1 and 2, the sum (D3+ D4) of the distance D1 between the gate structure S1 and the doped region 122 and the distance D4 between the doped region 122 and the conductive contact 130 in the present embodiment is about 50% to 80% of the sum of the distances D1 and D2, so that the size of the active region S2 can be further reduced without changing the breakdown voltage performance of the high voltage semiconductor device 100, and the high voltage semiconductor device 100 can still maintain the breakdown voltage performance between about 10V to 30V. In one embodiment, the breakdown voltage of the high voltage semiconductor device 100 can be further increased by increasing the pitch P between the gate structure S1 and the dummy gate structure S2 (see fig. 5).
As shown in fig. 9 and 10, the present invention provides an improved high voltage semiconductor device 100, wherein the composite spacer (including the dummy gate structure S2 and the insulating spacers 112 and 114) is disposed such that the doped region 122 in the double diffused structure thereof can be closer to the adjacent gate structure S1 without affecting the breakdown voltage performance of the high voltage semiconductor device 100, thereby facilitating the scaling of the high voltage semiconductor device 100 and further reducing the size of the active region a2 used in the high voltage semiconductor device 100. Furthermore, since the doped region 122 in the high voltage semiconductor device 100 is formed by self-alignment instead of being defined by a photolithography process in combination with a patterned mask layer or a photoresist layer, a photomask and related photolithography processes and materials can be omitted, which is helpful for reducing the manufacturing cost of the high voltage semiconductor device 100.
Referring to fig. 11 and 12, a cross-sectional view and a top view of a high voltage semiconductor device 100 according to another embodiment of the invention are shown, respectively. Here, the high voltage semiconductor device 100 is obtained by modifying the high voltage semiconductor device 100 shown in fig. 9 and 10, and the same reference numerals in fig. 11 and 12 represent the same components, and only the differences between the two embodiments will be explained below for the sake of simplicity.
Referring to the top view of fig. 12, in the present embodiment, the dummy gate structure S2 located at the right side of the gate structure S1 is not a continuous stripe structure, but is composed of a plurality of stripe segments 110, and the cross-sectional view shown in fig. 9 can still be obtained along the line 9-9 in fig. 12, and the cross-sectional view shown in fig. 11 can be obtained along the line 11-11 in fig. 12, i.e., the right side of the gate structure S1 is shown to include a composite spacer composed of the insulating spacers 112 and 114. The high voltage semiconductor device 100 shown in fig. 11 and 12 still has the same technical effects and advantages as the high voltage semiconductor device 100 shown in fig. 9 and 10.
Referring to fig. 13 and 14, a cross-sectional view and a top view of a high voltage semiconductor device 100 according to another embodiment of the invention are shown, respectively. Here, the high voltage semiconductor device 100 is obtained by modifying the high voltage semiconductor device 100 shown in fig. 9 and 10, and the same reference numerals in fig. 13 and 14 represent the same components, and only the differences between the two embodiments will be explained below for the sake of simplicity.
As shown in fig. 13 and 14, in the present embodiment, more than one dummy gate structure S2, for example, two dummy gate structures S2, are disposed on opposite sides of the gate structure S1, and the cross-sectional view shown in fig. 13 can be obtained along the line 13-13 in fig. 14. In the present embodiment, the distance D5 between the doped region 122 and the gate structure S1 and the distance D6 between the doped region 122 and the adjacent conductive contact 130 are smaller than the distance D1 between the gate structure S and the doped region 22 and the distance D2 between the doped region 22 and the conductive contact 30 in the structures shown in fig. 1 and 2, and the sum of the distances D5 and D6 in the present embodiment is about 50% to 80% of the sum of the distances D1 and D2 in the foregoing embodiments, so that the size of the active region S2 can be reduced without changing the breakdown voltage performance of the high voltage semiconductor device 100, and the high voltage semiconductor device 100 can still maintain the breakdown voltage performance between about 10V to 30V. The high voltage semiconductor device 100 shown in fig. 13 and 14 still has the same technical effects and advantages as the high voltage semiconductor device 100 shown in fig. 9 to 12.
In the high voltage semiconductor devices 100 shown in fig. 9 and 10, 11 and 12, 13 and 14, the gate structure S1 is symmetrical, such as a composite spacer or a double diffusion structure. However, in other embodiments, there may be a component arrangement within the high voltage semiconductor device 100 that is asymmetric to the gate structure S1, such as the implementation shown in fig. 15 and 16, and 17 and 18.
Referring to fig. 15 and 16, a cross-sectional view and a top view of a high voltage semiconductor device 100 according to another embodiment of the invention are shown, respectively. Here, the high voltage semiconductor device 100 is obtained by modifying the high voltage semiconductor device 100 shown in fig. 9 and 10, and the same reference numerals in fig. 15 and 16 represent the same components, and only the differences between the two embodiments will be explained below for the sake of simplicity.
As shown in fig. 15 and 16, in the present embodiment, a dummy gate structure S2, a spacer insulator 112 and a drift region 106 are disposed on only one side (for example, the right side) of the gate structure S1, and an insulating spacer 114 and a doped region 122 are disposed on the other side (for example, the left side) of the gate structure S1 without the drift region 106. The doped region 122 disposed in the drift region 106 can serve as a drain of the high voltage semiconductor device 100. Thus, the distance D3 between the doped region 122 and the gate structure S1 on the right side of the gate structure S1 and in the drift region 106 and the distance D4 between the doped region 122 and the conductive contact 130 are still apart, and the sum (D3+ D4) of the distance D3 between the gate structure S and the doped region 122 and the distance D4 between the doped region 122 and the conductive contact 130 in the embodiment of the present invention can be about 50% to 80% of the sum (D8525 + D4) of the distances D1 and D2 in the embodiment of fig. 1 and 2, so that the size of the active region S2 can be further reduced without changing the breakdown voltage performance of the high voltage semiconductor device 100, and thus the high voltage semiconductor device 100 can still maintain the breakdown voltage performance between about 10V to 30V. The high voltage semiconductor device 100 shown in fig. 15 and 16 still has the same technical effects and advantages as the high voltage semiconductor device 100 shown in fig. 9 and 10.
Referring to fig. 17 and fig. 18, a cross-sectional view and a top view of a high voltage semiconductor device 100 according to another embodiment of the invention are respectively shown. Here, the high voltage semiconductor device 100 is obtained by modifying the high voltage semiconductor device 100 shown in fig. 13 and 14, and the same reference numerals in fig. 17 and 18 represent the same components, and only the differences between the two embodiments will be explained below for the sake of simplicity.
As shown in fig. 17 and 18, in the present embodiment, more than one dummy gate structures S2 (e.g., two dummy gate structures S2), a spacer insulator 112 and a drift region 106 are disposed on only one side (e.g., the right side) of the gate structure S1, and only the insulating spacer 114 and the doped region 122 are disposed on the other side (e.g., the left side) of the gate structure S1 without the drift region 106. The doped region 122 disposed in the drift region 106 can serve as a drain of the high voltage semiconductor device 100. Thus, the distance D5 between the doped region 122 located on the right side of the gate structure S1 and the drift region 106 and the gate structure S1 and the distance D6 between the doped region 122 and the conductive contact 130 do not change the breakdown voltage performance of the high voltage semiconductor device 100, so that the high voltage semiconductor device 100 can still maintain the breakdown voltage performance between about 10V-30V. The high voltage semiconductor device 100 shown in fig. 17 and 18 still has the same technical effects and advantages as the high voltage semiconductor device 100 shown in fig. 13 and 14.
For the sake of simplicity, the method for manufacturing the high voltage semiconductor device 100 having the asymmetric gate structure S1 shown in fig. 15, 16, 17, 18 and the like can be modified with reference to the method shown in fig. 3 to 10, and the related fabrication of the unnecessary components on the side where the gate structure S1 is omitted in the similar process can be completed, so that the description of the related fabrication and drawing will not be repeated here.
In the operation of the high voltage semiconductor device 100 shown in fig. 9-18, etc., the dummy gate structure S2 in the composite spacer adjacent to the drain side thereof may be floating (floating) with or without any voltage coupling, or a doped region 122 serving as the drain and a dummy gate structure S2 adjacent to the drain side may be coupled to a same operating voltage, such as a drain voltage Vd, by appropriate interconnection structures formed subsequently as shown in fig. 19. Similarly, in the operation of the high voltage semiconductor device 100 shown in fig. 9-18, the dummy gate structure S2 in the composite spacer adjacent to the source side thereof may be floating with or without any voltage coupling, or a doped region 122 as the source and a dummy gate structure S2 adjacent to the source side may be coupled to a same operating voltage, such as a source voltage Vs, by appropriate interconnection structures formed subsequently as shown in fig. 19. The high voltage semiconductor device shown in fig. 19 is the high voltage semiconductor device 100 shown in fig. 9 and 10, and the same electrical connection situation is also applicable to the high voltage semiconductor device 100 shown in fig. 11 to 18, and the description and drawings related implementation situations are not repeated here.
Referring to fig. 20, a cross-sectional view of a high voltage semiconductor device 200 according to another embodiment of the invention is shown. Here, the high voltage semiconductor device 200 in the present embodiment employs the composite spacer structure in the high voltage semiconductor device 100 as shown in fig. 9-18 on a drain side, and thus has the same technical effects and advantages as those of the high voltage semiconductor device 100 as shown in fig. 9-18.
As shown in fig. 20, the high voltage semiconductor device 200 is a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device, which includes a semiconductor substrate 202 having a first conductivity type (e.g., P-type), a doped region 204 embedded in a portion of the semiconductor substrate 202 and having a second conductivity type (e.g., N-type) opposite to the first conductivity type, and body regions 208 of the first conductivity type disposed in different regions of the semiconductor substrate 202. A doped region 216 of the first conductivity type and a doped region 214 of the second conductivity type are disposed in the body region 208, a doped region 212 of the second conductivity type is disposed in the semiconductor substrate 202 adjacent to one side of the body region 208, and a conductive contact 230 is disposed on each of the doped regions 212, 214, and 216. Furthermore, a gate structure is disposed on the epitaxial semiconductor layer 206, which includes a gate structure S1, a dummy gate structure S2, and a plurality of insulating spacers 222 and 224. Here, the doped region 212 serves as a drain and the doped region 214 serves as a source, the gate structure adjacent to the doped region 212 includes a composite spacer composed of the dummy gate structure S2 and the insulating spacers 222 and 224, and the gate structure adjacent to the doped region 214 includes only one spacer composed of the insulating spacer 224, the gate structure S1 and the dummy gate structure are composed of a dielectric layer 218 and a conductive layer 220. In the present embodiment, the related implementation of the doped regions 212 and 214, the gate structure S1, the dummy gate structure S2, the insulating spacers 222 and 224, and the related conductive contact 230 are similar to the related implementation of the doped regions 212 and 214, the gate structure S1, the dummy gate structure S2, the insulating spacers 222 and 224, and the related conductive contact 230 in the high voltage semiconductor device 100 shown in fig. 9 to 18, respectively, similar to the related implementation of the doped region 122, the gate structure S1, the dummy gate structure S2, the insulating spacers 112 and 114, and the related conductive contact 130 in the high voltage semiconductor device 100 shown in fig. 9 to 18. Therefore, the high voltage semiconductor device 200 may also have the same technical effects and advantages as the high voltage semiconductor device 100.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A high voltage semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a gate structure on a portion of the semiconductor substrate;
a pair of spacers respectively disposed on a sidewall of the gate structure, wherein one of the pair of spacers is a composite spacer, and the composite spacer includes a first insulating spacer contacting the gate structure, a dummy gate structure and a second insulating spacer;
a body region disposed in a portion of the semiconductor substrate and underlying a portion of the gate structure and one of the pair of spacers, having the first conductivity type; and
a pair of doped regions disposed within a portion of the semiconductor substrate on opposite sides of the gate structure, respectively, wherein the pair of doped regions have a second conductivity type and one of the pair of doped regions is disposed within the body region and the other of the pair of doped regions is disposed outside the body region;
a second doped region of said first conductivity type in said body region adjacent to one of said pair of doped regions in said body region; wherein,
the dummy gate structure is adjacent to one of the pair of doped regions disposed outside the body region, wherein the dummy gate structure and the one of the pair of doped regions disposed outside the body region are coupled to a same operating voltage, and the dummy gate structure is discontinuous in a top view.
2. The high voltage semiconductor device of claim 1, wherein the dummy gate structure has a stripe shape in a top view, and the dummy gate structure has a rectangular shape in a cross-sectional view.
3. The high voltage semiconductor device of claim 1, wherein the gate structure and the dummy gate structure comprise a dielectric layer and a conductive layer on the dielectric layer.
4. The high voltage semiconductor device of claim 1, wherein the other of said pair of spacers also includes said composite spacer contacting said first insulating spacer of said gate structure, said dummy gate structure and said second insulating spacer.
5. The high voltage semiconductor device of claim 1, wherein the composite spacer comprises a plurality of first insulating spacers contacting the gate structures, a plurality of dummy gate structures, and a second insulating spacer, wherein the first insulating spacers are respectively located between the dummy gate structures, between the dummy gate structures and the second insulating spacer, and between the dummy gate structures and the gate structures.
6. A method for manufacturing a high voltage semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first conduction type;
forming a body region in a portion of the semiconductor substrate, the body region having the first conductivity type;
forming a gate structure and a dummy gate structure on the semiconductor substrate, wherein the gate structure partially covers the body region, and the dummy gate structure is located on the semiconductor substrate outside the body region;
forming a first insulating spacer and a pair of second insulating spacers, wherein the first insulating spacer is located between the gate structure and the dummy gate structure, and the plurality of second insulating spacers are located on a sidewall of the dummy gate structure and a sidewall of the gate structure, respectively;
performing an ion implantation process to form two doped regions in the semiconductor substrate adjacent to the second insulating spacer, wherein the doped regions have a second conductivity type, and one of the doped regions is located in the body region and the other of the doped regions is located outside the body region, wherein the dummy gate structure is adjacent to one of the doped regions located outside the body region;
performing a second ion implantation process to form a second doped region in the body region adjacent to one of the doped regions in the body region, wherein the second doped region has the first conductivity type;
performing an annealing process; and
forming an interconnect structure such that the dummy gate structure and one of the doped regions outside the body region are coupled to a same operating voltage, and the dummy gate structure is discontinuous in a top view.
7. The method according to claim 6, wherein the dummy gate structure has a stripe shape in a top view, and the dummy gate structure has a rectangular shape in a cross-sectional view.
8. The method of claim 6, wherein the gate structure and the dummy gate structure comprise a dielectric layer and a conductive layer on the dielectric layer.
9. The method of claim 6, wherein the first insulating spacer, the dummy gate structure and the second insulating spacer form a composite spacer.
10. A method for manufacturing a high voltage semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first conduction type;
forming a body region in the semiconductor substrate, the body region having the first conductivity type;
forming a gate structure and a plurality of dummy gate structures on the semiconductor substrate, wherein the gate structure partially covers a portion of the body region, and the dummy gate structures are respectively located on the semiconductor substrate outside the body region;
forming a plurality of first insulating spacers and a pair of second insulating spacers, wherein the first insulating spacers are respectively located between the gate structures and the dummy gate structures and between the dummy gate structures, and the second insulating spacers are located on one side wall of the dummy gate structures;
performing an ion implantation process to form two doped regions in the semiconductor substrate adjacent to the second insulating spacer, wherein the doped regions have a second conductivity type and are respectively located inside and outside the body region, and wherein one of the dummy gate structures is adjacent to one of the doped regions located outside the body region;
performing a second ion implantation process to form a second doped region in the body region adjacent to one of the doped regions in the body region, wherein the second doped region has the first conductivity type; performing an annealing process; and
forming an interconnect structure such that one of the dummy gate structures and one of the doped regions are coupled to a same operating voltage and the dummy gate structure is discontinuous in a top view.
11. The method of claim 10, wherein the gate structure and the dummy gate structure comprise a dielectric layer and a conductive layer on the dielectric layer.
12. The method according to claim 10, wherein one of the first insulating spacers, one of the dummy gate structures and the second insulating spacer form a composite spacer, respectively.
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