CN103208459A - Production method of nand gate type flash storage device - Google Patents
Production method of nand gate type flash storage device Download PDFInfo
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- CN103208459A CN103208459A CN2012100651272A CN201210065127A CN103208459A CN 103208459 A CN103208459 A CN 103208459A CN 2012100651272 A CN2012100651272 A CN 2012100651272A CN 201210065127 A CN201210065127 A CN 201210065127A CN 103208459 A CN103208459 A CN 103208459A
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Abstract
The invention discloses a production method of a nand gate type flash storage device. First gate oxide layers are formed on a semiconductor substrate which is provided with a first area, a second area and a third area; first gate oxide layers which are corresponding to the first area and the second area are provided with first thicknesses; a first gate oxide layer which is corresponding to the third area is provided with a second thickness; a first grid layer and a second grid layer are respectively formed on first gate oxide layers of the second area and the third area; oxidation treatment is performed on a first gate oxide layer of the first area to form into a second gate oxide layer which is provided with a third thickness; a third grid layer and an inter-grid dielectric layer are sequentially formed on the second gate oxide layer; and a fourth grid layer, a fifth grid layer and a sixth grid layer are respectively formed on the first grid layer, the second grid layer and the inter-grid dielectric layer.
Description
Technical field
Present invention is directed to a kind of non-volatile memory, particularly relevant for the manufacture method of a kind of and not b gate type (NAND type) flash memory devices.
Background technology
Advantages such as flash memory has that area is little, power saving, high speed and low operating voltage, thereby apply to widely in the nonvolatile memory technology.And not b gate type (NAND type) flash memory is a type of flash memory, and it reaches the critical elements that advantage such as compact becomes digital still camera, mobile phone, printer, personal digital assistant products such as (PDA) less because having big capacity, impact resistance, noise.
In existing and not b gate type flash memory devices is made, for high pressure and the low voltage operated element (being transistor) of peripheral logic circuit are made the making that is integrated in memory cell array, the grid of high pressure and low voltage operated element and the floating grid of each memory cell must use the semiconductor layer of doping of same conductivity (for example, n type) as material.Thus, for the low voltage operated element of p-type, can reduce electrical characteristics and the usefulness of element itself.Moreover, because the thickness of the gate dielectric of low voltage operated element must be subject to the thickness of wearing tunnel oxidation (tunnel oxide) layer of memory cell.Thus, and can't come electrical characteristics and the usefulness of lift elements itself by the thickness of the gate dielectric that reduces low voltage operated element.
Therefore, be necessary to seek a kind of manufacture method of and not b gate type flash memory devices, it can improve or address the above problem.
Summary of the invention
One embodiment of the invention provides a kind of manufacture method of and not b gate type flash memory devices, comprising: the semiconductor substrate is provided, and it has one second district and one the 3rd district in one first district and adjacency first district; Form a first grid oxide layer at the semiconductor-based end, wherein the first grid oxide layer corresponding to first and second district has one first thickness, and has one second thickness greater than first thickness corresponding to the first grid oxide layer in the 3rd district; On the first grid oxide layer in second and third district, form a first grid floor and a second grid floor respectively, and expose the first grid oxide layer that is positioned at first district; The first grid oxide layer of exposing is carried out oxidation processes, have a second grid oxide layer of one the 3rd thickness with formation, wherein the 3rd thickness is different from first and second thickness; On the second grid oxide layer, form one the 3rd grid layer and a gate dielectric layer in regular turn; And on first grid layer, second grid layer and gate dielectric layer, form one the 4th grid layer, one the 5th grid layer and one the 6th grid layer respectively.
Description of drawings
Figure 1A to Fig. 1 J system shows the manufacture method generalized section of and not b gate type flash memory devices according to an embodiment of the invention.
The main element symbol description:
10～the first districts;
20a～second district;
20b～the 3rd district;
T1～first thickness;
T2～second thickness;
T3～the 3rd thickness;
100～semiconductor-based the end;
102,102a, 102b～first grid oxide layer;
104,122～semiconductor layer;
104a～first grid layer;
104b～second grid layer;
106～mask pattern layer;
108～mask clearance wall;
110～second grid oxide layer;
112～the 3rd grid layers;
112a～unadulterated semiconductor layer;
The semiconductor layer of 112b～doping;
114～rigid mask layer;
116,117～opening;
118～isolation structure;
120～dielectric layer;
122a～the 4th grid layer;
122b～the 5th grid layer;
122c～the 6th grid layer;
124,126,128～grid gap wall;
130,140,142～metal silicide layer
Embodiment
The manufacture method of the and not b gate type flash memory devices of the embodiment of the invention below is described.Yet, can understand embodiment provided by the present invention easily and only be used for explanation with the ad hoc approach making and use the present invention, be not in order to limit to scope of the present invention.
Figure 1A to Fig. 1 J system shows the manufacture method generalized section of and not b gate type flash memory devices according to an embodiment of the invention.Please refer to Figure 1A and Figure 1B, semiconductor substrate 100 is provided, for example a silicon base or other semiconductor base material.The semiconductor-based end 100, have one second district 20a and one the 3rd district 20b in one first district 10 and adjacency first district 10.In the present embodiment, first district can be used as a cell array (cell array) district of and not b gate type flash memory devices.Moreover the second district 20a and the 3rd district 20b can be used as a periphery circuit region of and not b gate type flash memory devices.In one embodiment, the second district 20a can be between first district 10 and the 3rd district 20b, and wherein the second district 20a can be low voltage operated element region, and the 3rd district 20b can be the operation with high pressure element region.
Then, 100 form a first grid oxide layer 102 at the semiconductor-based end, silicon oxide layer for example, and wherein the first grid oxide layer 102 corresponding to first district 10 and the second district 20a has one first thickness T 1.Moreover, have one second thickness T 2 greater than first thickness T 1 corresponding to the first grid oxide layer 102 of the 3rd district 20b, shown in Figure 1A.For instance, first thickness T 1 can be at 30 to 50 dusts
Scope, and second thickness T 2 can be in the scope of 300 to 500 dusts.
Next, forming semi-conductor layer 104 in first grid oxide layer 102, for example is unadulterated polysilicon layer or other suitable semiconductor material layers, for follow-up usefulness of making the grid of high pressure and low voltage operated element in periphery circuit region.Form a mask layer (not illustrating), for example silicon nitride layer at semiconductor layer 104.Then, utilize conventional photolithographic and etching technique to come the patterned mask layer, form a mask pattern floor 106 with the semiconductor layer 104 at the second district 20a and the 3rd district 20b, and expose the semiconductor layer 104 that is positioned at first district 10.
Next, please refer to Figure 1B, can utilize mask pattern layer 106 as etching mask, the semiconductor layer 104 that exposes with further removal, and expose the first grid oxide layer 102 that is positioned at first district 10, and on the first grid oxide layer 102 of the second district 20a and the 3rd district 20b, form a first grid floor 104a and a second grid floor 104b respectively.
Please refer to Fig. 1 C, compliance forms a mask layer (not illustrating), for example silicon nitride layer on the structure of Figure 1B.Mask layer is implemented an anisotropic (anisotropic) etching, form a mask clearance wall 108 with the sidewall at the semiconductor layer (being first grid floor 104a) of the second district 20a.Afterwards, the first grid oxide layer of exposing 102 is carried out oxidation processes, thermal oxidation for example, to form the second grid oxide layer 110 with one the 3rd thickness T 3 in first district 10, wherein the 3rd thickness T 3 is different from first thickness T 1 and second thickness T 2 (being shown in Figure 1A).In the present embodiment, the 3rd thickness T 3 is greater than first thickness T 1 and less than second thickness T 2.For instance, the 3rd thickness T 3 can be in the scope of 70 to 80 dusts.Second grid oxide layer 110 is oxidation (tunnel oxide) layer material then of wearing as each memory cell in the cell array region.Thus, the thickness of the first grid oxide layer 102 of the second district 20a (that is first thickness T 1) can not be subject to the thickness (that is the 3rd thickness T 3) of second grid oxide layer 110.
Next, please refer to Fig. 1 D, after the mask pattern layer 106 and mask clearance wall 108 in removing Fig. 1 C, form one the 3rd grid layer 112 in second grid oxide layer 110 (being tunneling oxide layer), for follow-up floating grid (floating gate, usefulness FG) of in cell array region, making memory cell.The 3rd grid layer 112 can be an individual layer or a sandwich construction.In one embodiment, can (for example on first grid layer 104a, second grid layer 104b and second grid oxide layer 110, form a unadulterated semiconductor layer 112a in regular turn, unadulterated polysilicon layer) and a semiconductor layer 112b (for example, n type doped polycrystalline silicon layer) who mixes.Afterwards, can utilize conventional photolithographic and etching technique to come patterning not doping semiconductor layer 112a and a semiconductor layer 112b who mixes, be positioned at the semiconductor layer 112b that the unadulterated semiconductor layer 112a and on first grid layer 104a, the second grid layer 104b mixes with removal, and form the 3rd grid layer 112 with sandwich construction in second grid oxide layer 110.
Please refer to Fig. 1 E, on first grid layer 104a, second grid layer 104b and the 3rd grid oxic horizon 112, form a rigid mask (hard mask) layer 114 and one photoresist layer (not illustrating) in regular turn.Afterwards, can see through conventional photolithographic and etch process, in rigid mask layer 114, form the opening 116 in order to define isolated area.Then, the grid layer of etching openings 116 belows (for example in regular turn, first grid layer 104a, second grid layer 104b and the 3rd grid oxic horizon 112), grid oxic horizon (for example, first grid oxide layer 102 and second grid oxide layer 110) and the semiconductor-based end 100, in the semiconductor-based end 100, to form plurality of openings 117.Opening 117 is the usefulness for follow-up formation isolation structure.Zone between opening 117 system as active region (active area, AA).Be noted that the section shown in Fig. 1 E is the bit line direction character line direction of each memory cell (or be parallel to) of vertical each memory cell.
Please refer to Fig. 1 F, after removing rigid mask layer 114, can see through conventional deposition technique, for example chemical vapour deposition (CVD) (chemical vapor deposition, CVD), in each opening 117 and above form a dielectric material, silica for example, (for example, shallow trench isolation is from (shallowtrench isol ation, STI)) to form isolation structure 118.Then, at the floating grid that is positioned at first district 10 (namely, the 3rd grid layer 112) upper surface and sidewall and the upper surface compliance that is positioned at the isolation structure 118 in first district 10 form a dielectric layer 120, with as dielectric between grid (inter-gate dielectric) layer.In one embodiment, dielectric layer 120 can comprise an oxide layer-nitride layer-oxide layer (oxide-nitride-oxide, ONO) structure.
Next, please refer to Fig. 1 G and Fig. 1 G-1, form semi-conductor layer 122 in the structure shown in Fig. 1 F, for example be unadulterated polysilicon layer or other suitable semiconductor material layers, in periphery circuit region, make the grid of high pressure and low voltage operated element and in cell array region, make control grid (control gate, usefulness CG) for follow-up.Be noted that herein the section shown in Fig. 1 G-1 is the bit line direction character line direction of each memory cell (or perpendicular to) of parallel each memory cell.
Next, please refer to Fig. 1 H, the section shown in it is the bit line direction character line direction of each memory cell (or perpendicular to) of parallel each memory cell.(for example can see through grid layer that conventional photolithographic and etch process come patterned semiconductor layer 122 and below thereof, first grid layer 104a, second grid layer 104b and the 3rd grid oxic horizon 112) and gate dielectric layer 120, on first grid layer 104a, second grid layer 104b and gate dielectric layer 120, to form one the 4th grid layer 122a, one the 5th grid layer 122b and one the 6th grid layer 122c respectively.In the present embodiment, the 6th grid layer 122c system is as the control grid, and the 3rd grid oxic horizon 112 of control grid below is as floating grid.
Afterwards, can remove the dielectric material on isolation structure 118 tops and (for example be positioned at grid layer, first grid layer 104a, second grid layer 104b and the 3rd grid oxic horizon 112) outside grid oxic horizon (for example, first grid oxide layer 102 and second grid oxide layer 110), to expose the surface at the semiconductor-based end 100.In the present embodiment, be positioned at first grid layer 104a and the 4th grid layer 122a system as the grid of low voltage operated element, the first grid layer 102a of first grid layer 104a below is then as the grid oxic horizon of low voltage operated element.Moreover, being positioned at second grid layer 104b and the 5th grid layer 122b system as the grid of operation with high pressure element, the first grid layer 102b of second grid layer 104b below is then as the grid oxic horizon of operation with high pressure element.
Next, please refer to Fig. 1 I, compliance forms a dielectric layer (not illustrating), for example silicon oxide layer on the structure of Fig. 1 H.Then, the anisotropic etching dielectric layer, with respectively in first district 10, the second district 20a and the 3rd district 20b form grid gap wall 124,126 and 128.
Next, please refer to Fig. 1 J, can carry out n type and/or p-type ion implantation to the structure of Fig. 1 I, in first district 10, the second district 20a and the 3rd district 20b, to form grid with required conductivity type and the source/drain (not illustrating) of corresponding these grids respectively.Thus, just finish the making of the and not b gate type flash memory devices of present embodiment.In other embodiments, can see through known metal silication processing procedure, corresponding formation one metal silicide layer 130 on the 4th grid layer 122a, the 5th grid layer 122 and the 6th grid layer 122c, and on the semiconductor-based end 100 in insulating gap wall 126 and 128 outsides, form metal silicide layer 140 and 142 respectively.Metal silicide layer can effectively reduce the contact resistance between element and the intraconnections.In one embodiment, metal silicide layer 130,140 and 142 can comprise cobalt silicide (CoSi
x).
According to above-described embodiment, owing to be different from the semiconductor layer of the doping of the floating grid of making memory cell for the manufacture of the semiconductor layer of the doping of the grid of low voltage operated element, therefore the grid of low voltage operated element can have different conductivity types with the floating grid of memory cell, and then avoids reducing electrical characteristics and the usefulness of low voltage operated element.Moreover, because the thickness of the grid oxic horizon of low voltage operated element can not be subject to the thickness of the tunnel oxide of memory cell, therefore can promote electrical characteristics and the usefulness of low voltage operated element by the thickness of the grid layer that reduces low voltage operated element.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing to change and retouching, thus protection scope of the present invention when with claim scope of the present invention the person of being defined be as the criterion.
Claims (10)
1. the manufacture method of an and not b gate type flash memory devices is characterized in that, described method comprises:
The semiconductor substrate is provided, and it has one first district and in abutting connection with one second district and one the 3rd district in this first district;
Form a first grid oxide layer at the described semiconductor-based end, wherein corresponding to described first and the described first grid oxide layer in described second district have one first thickness, and have one second thickness greater than described first thickness corresponding to the described first grid oxide layer in described the 3rd district;
Described second and the described first grid oxide layer in described the 3rd district on form a first grid floor and a second grid floor respectively, and expose the described first grid oxide layer that is positioned at described first district;
The described described first grid oxide layer of exposing is carried out oxidation processes, have a second grid oxide layer of one the 3rd thickness with formation, wherein said the 3rd thickness is different from described first and described second thickness;
On described second grid oxide layer, form one the 3rd grid layer and a gate dielectric layer in regular turn; And
On described first grid layer, described second grid layer and described gate dielectric layer, form one the 4th grid layer, one the 5th grid layer and one the 6th grid layer respectively.
2. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, described method more be included in the described the 4th, the described the 5th and described the 6th grid layer on the corresponding metal silicide layer that forms.
3. the manufacture method of and not b gate type flash memory devices as claimed in claim 1, it is characterized in that a cell array region of the described and not b gate type of described first fauna flash memory devices and described second and a periphery circuit region of the described and not b gate type of described the 3rd fauna flash memory devices.
4. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, form described first and the step of described second grid layer more comprise:
Form semi-conductor layer in described first grid oxide layer;
Described second and the described semiconductor layer in described the 3rd district form a mask pattern floor, to expose the described semiconductor layer that is positioned at described first district; And
Remove the described described semiconductor layer that exposes.
5. the manufacture method of and not b gate type flash memory devices as claimed in claim 4 is characterized in that, before carrying out described oxidation processes, more is included on the sidewall of described semiconductor layer in second district and forms a mask clearance wall.
6. the manufacture method of and not b gate type flash memory devices as claimed in claim 5 is characterized in that, described mask layer and described mask clearance wall system are made of silicon nitride.
7. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, described the 3rd thickness is greater than described first thickness and less than described second thickness.
8. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, described the 3rd grid layer comprises the semiconductor layer that mixes of doping semiconductor layer and not.
9. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, described gate dielectric layer comprises an oxide layer-nitride layer-oxide layer structure.
10. the manufacture method of and not b gate type flash memory devices as claimed in claim 1 is characterized in that, the described the 4th, the described the 5th and described the 6th grid layer constituted by the patterning semi-conductor layer.
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| CN201210065127.2A CN103208459B (en) | 2012-01-13 | 2012-01-13 | The manufacture method of not b gate type flash memory devices |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752357A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of storage |
| TWI615922B (en) * | 2017-05-26 | 2018-02-21 | 華邦電子股份有限公司 | Method of manufacturing semiconductor memory device |
| US10438958B2 (en) | 2017-05-26 | 2019-10-08 | Winbond Electronics Corp. | Method for manufacturing semiconductor memory device |
| CN116053274A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
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| CN101236921A (en) * | 2007-01-30 | 2008-08-06 | 力晶半导体股份有限公司 | Making method for semiconductor component with capacitor |
| CN101770989A (en) * | 2008-12-30 | 2010-07-07 | 华邦电子股份有限公司 | Forming method of semiconductor structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752357A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of storage |
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| TWI615922B (en) * | 2017-05-26 | 2018-02-21 | 華邦電子股份有限公司 | Method of manufacturing semiconductor memory device |
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| CN116053274A (en) * | 2023-01-28 | 2023-05-02 | 合肥晶合集成电路股份有限公司 | Semiconductor integrated device and manufacturing method thereof |
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