CN103199953B - Data transmission method and device, communication equipment - Google Patents
Data transmission method and device, communication equipment Download PDFInfo
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- CN103199953B CN103199953B CN201210004683.9A CN201210004683A CN103199953B CN 103199953 B CN103199953 B CN 103199953B CN 201210004683 A CN201210004683 A CN 201210004683A CN 103199953 B CN103199953 B CN 103199953B
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Abstract
The embodiment of the present invention provides a kind of data transmission method and device.The method comprises: generate the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block; Send 64B/66B encoding block.The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
Description
Technical field
The embodiment of the present invention relates to wireless communication field, and more specifically, relates to data transmission method and device, communication equipment.
Background technology
Shown by simulation study, the error rate of CPRI (CommonPublicRadioInterface, common public radio interface) link has larger impact to wireless transmission channel.Such as, when RB (ResourceBlock, Resource Block) is 1, the error rate of CPRI link does not have much affect to the performance that wireless channel transmits, less on performance loss impact.When RB quantity increases, CPRI link error rates is increasing on systematic function impact.As RB=50, CPRI link error rates is 1.0e-5, and performance loss is unacceptable, considers to compress when surplus simultaneously, can infer that obtaining CPRI link error rates is 1.0e-7, unacceptable on systematic function impact.
Therefore, physical link bottom needs a kind of error rate testing mechanism, effectively can identify CPRI link error rates magnitude, and when finding link error rates higher than particular value (such as 1.0e-7), carries out reporting warning.
Utilize base intraframe data information in prior art, the CRC (CyclicRedundancyCheck, cyclic redundancy check (CRC)) 16 carrying out each base frame verifies.But CRC protects unit to be base frame substantially, granularity comparatively large (such as, for the CPRI agreement of 10G speed, base frame sign is 2560 bits), accuracy of detection is poor, accurately cannot detect the problem of link error rates.
Summary of the invention
The embodiment of the present invention provides a kind of data transmission method and device, communication equipment, can solve the problem of error rate accuracy of detection difference.
On the one hand, provide a kind of data transmission method, comprising: generate the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block; Send 64B/66B encoding block.
On the other hand, provide a kind of data transmission method, comprising: receive the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of described 64B/66B encoding block; The payload of the parity information utilizing synchronous head to carry to 64B/66B encoding block verifies.
On the other hand, provide a kind of data transmission device, comprising: generation unit, for generating the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block; Transmitting element, for sending described 64B/66B encoding block.
On the other hand, provide a kind of data transmission device, comprising: receiving element, for receiving the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block; Verification unit, the payload of the parity information carried for utilizing synchronous head to 64B/66B encoding block verifies.
On the other hand, provide a kind of communication equipment, comprising: coding unit, for encoding to data, generate the payload of 64 bits, and generate the synchronous head of 2 bits, wherein said synchronous head carries the parity information of described payload; Scrambling unit, carries out scrambling for the payload generated described coding unit, obtains the payload after scrambling; Merge cells, the synchronous head for being generated by described coding unit adds the payload after described scrambling unit scrambling to, obtains the encoding block of 66 bits; Parallel serial conversion unit, for carrying out parallel-serial conversion process to described encoding block, to generate the encoding block of serial; Supply unit, for sending the encoding block of described serial.
On the other hand, provide a kind of communication equipment, comprising: receiving element, for receiving the encoding block of the serial of 66 bits, the synchronous head of described encoding block carries the parity information of the payload of described encoding block; Serioparallel exchange unit, for carrying out serioparallel exchange process to the encoding block of described serial; Separative element, for extracting the payload after the synchronous head of 2 bits and the scrambling of 64 bits in the encoding block after carrying out serioparallel exchange process from described serioparallel exchange unit; Descrambling unit, carries out scramble process to obtain described payload for the payload after the scrambling of extracting described separative element; Verification unit, the parity information entrained by the described synchronous head extracted for utilizing described separative element verifies the described payload that described Descrambling unit obtains.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the data transmission method of one embodiment of the invention.
Fig. 2 is the flow chart of the data transmission method of another embodiment of the present invention.
Fig. 3 is the schematic diagram of an example of the system of the application embodiment of the present invention.
Fig. 4 is the block diagram of the data transmission device of one embodiment of the invention.
Fig. 5 is the block diagram of the data transmission device of one embodiment of the invention.
Fig. 6 is the block diagram of the communication equipment of one embodiment of the invention.
Fig. 7 is the block diagram of the communication system of another embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Technical scheme of the present invention, various communication system can be applied to, such as: global system for mobile communications (GSM, GlobalSystemofMobilecommunication), code division multiple access (CDMA, CodeDivisionMultipleAccess) system, Wideband Code Division Multiple Access (WCDMA) (WCDMA, WidebandCodeDivisionMultipleAccessWireless), GPRS (GPRS, GeneralPacketRadioService), Long Term Evolution (LTE, LongTermEvolution) etc.
Subscriber equipment (UE, UserEquipment), also mobile terminal (MobileTerminal) can be referred to as, mobile subscriber equipment etc., can through wireless access network (such as, RAN, RadioAccessNetwork) communicate with one or more core net, subscriber equipment can be mobile terminal, as mobile phone (or being called " honeycomb " phone) and the computer with mobile terminal, such as, can be portable, pocket, hand-hold type, built-in computer or vehicle-mounted mobile device, they and wireless access network exchange language and/or data.
Base station, can be the base station (BTS in GSM or CDMA, BaseTransceiverStation), also can be the base station (NodeB) in WCDMA, can also be the evolved base station (eNB or e-NodeB, evolutionalNodeB) in LTE, the present invention limit, but for convenience of description, following embodiment is described for NodeB.
Fig. 1 is the flow chart of the data transmission method of one embodiment of the invention.The method of Fig. 1 is performed by the transmitting terminal (as base station, base station controller or other entities) of data.
101, generate the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block.
The 64B/66B encoding block meeting CPRI agreement has 66 bits, and the first two bit is synchronous head (SyncHead), after 64 bits be payload (Payload).
102, send this 64B/66B encoding block.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The verification protection unit of traditional C RC is base frame, granularity comparatively large (such as, for the CPRI agreement of 10G speed, base frame sign is 2560 bits); The verification protection unit of the embodiment of the present invention is 64B/66B encoding block, and size is 66 bits, less than the protection granularity of CRC, can improve error rate accuracy of detection.
In addition, the redundancy of the synchronous head of existing 64B/66B encoding block is used as parity check by the embodiment of the present invention, and the complexity of realization is also lower.Compared with the CRC check of the data bandwidth outside traditional occupying volume, the verification mode energy saving resource of the embodiment of the present invention.
Alternatively, as an embodiment, in a step 101, the payload of 64B/66B encoding block can be generated, and according to the parity information of payload, generate the first bit of synchronous head as check digit, generate the radix-minus-one complement of the second bit as this first bit of synchronous head.In other words, the synchronous head of the 64B/66B encoding block generated in a step 101 can ensure as " 10 " or " 01 ", like this can compatible existing 64B/66B coding protocol.
64B/66B encoding block comprises two types, i.e. superframe header (Hyperframe) or common encoding block.Alternatively, as another embodiment, the parity check pattern of the 64B/66B encoding block of two types can be different.Such as, in one example in which, according to the odd information of the payload of superframe header, the first bit of the synchronous head of superframe header can be generated as odd parity bit, generate the radix-minus-one complement of the second bit as the first bit of the synchronous head of superframe header; Now, can according to the even parity check information of the payload of common encoding block, the first bit generating the synchronous head of common encoding block, as even parity bit, generates the radix-minus-one complement of the second bit as the first bit of the synchronous head of common encoding block.
In another example, can according to the even parity check information of the payload of superframe header, generate the first bit of the synchronous head of superframe header as even parity bit, generate the radix-minus-one complement of the second bit as the first bit of the synchronous head of superframe header, and can according to the odd information of the payload of common encoding block, the first bit generating the synchronous head of common encoding block, as odd parity bit, generates the radix-minus-one complement of the second bit as the first bit of the synchronous head of common encoding block.Like this, namely encoding block synchronous head information carry the parity information of encoding block, realizes the protection to coded message, meanwhile, also do not produce illegal synchronous header, thus realize two kinds of function compatibilities.
Alternatively, as another embodiment, the synchronous head of superframe header can be " 10 ", and the payload of superframe header is " 78,50,50,50,50,50,50,50 ", like this can the recognition mechanism of superframe header of further compatible existing 64B/66B coding protocol defined.Receiving terminal identifiable design is encoded " 10 " synchronous head signal passed over, and whether the superframe header payload information identifying wherein meets the control word information " 78,50,50,50,50,50,50,50 " of expection.In this object lesson, the binary bits due to 78 is 01001110 (4 " 1 "), and the binary bits of 50 is 00110010 (3 " 1 "), so the payload of superframe header comprises 4+3 × 7=25 " 1 ".Therefore, synchronous head " 10 " is odd information, and the first bit (being " 1 " in the case) namely in synchronous head is odd parity bit.The synchronous head of common encoding block may be " 10 " or " 01 ", is even parity check information, and the first bit namely in synchronous head is even parity bit.
Certainly, the concrete form of the embodiment of the present invention to superframe header is not restricted.If the payload of superframe header is other numerical value and meets even parity check, then can determine that synchronous head " 10 " is for even parity check information.
Other mechanism of all right compatible existing 64B/66B coding protocol of the embodiment of the present invention, as scrambling mechanism, GearBox (speed changer) mechanism etc.Such as, parity check can be carried out to the payload of the non-scrambling of common encoding block, be defined as the synchronous head of common encoding block for " 10 " or " 01 ".Then motor synchronizing scrambling is carried out to payload, synchronous head adds and the process such as Gearbox, parallel-serial conversion, export the encoding block of 66 bits.Like this, only to the little improvement of 64B/66B encoding block, high-precision verification need can be realized, and compatible existing 64B/66B encoding-decoding process.
In addition, it is more that the embodiment of the present invention can detect error code type, because the unit of verification protection is 66 bits of encoded blocks, therefore can distinguish single-bit error code and the error burst more than 66 bits.
Fig. 2 is the flow chart of the data transmission method of another embodiment of the present invention.The method of Fig. 2 is performed by receiving terminal (as base station, base station controller or other entities).
201, receive the 64B/66B encoding block meeting CPRI agreement, wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block.
202, the payload of the parity information utilizing synchronous head to carry to 64B/66B encoding block verifies.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The method of Fig. 2 is corresponding with the method for Fig. 1, therefore will suitably omit detailed description.
Alternatively, as an embodiment, in step 202., the synchronous head of identifiable design 64B/66B encoding block, the first bit wherein in synchronous head is check digit, and the second bit in synchronous head is the radix-minus-one complement of the first bit.When the payload of 64B/66B encoding block meets check digit, determine verification succeeds; When the payload of 64B/66B encoding block does not meet check digit, determine to verify unsuccessfully.The synchronous head of such 64B/66B encoding block can ensure as " 10 " or " 01 ", can compatible existing 64B/66B coding protocol.So-called payload meets check digit, and refer to that the number of the bit " 1 " comprised in payload is consistent with the instruction of check digit, this is identical with the definition of parity check of the prior art.Such as, if check digit is odd parity bit, then when the number of the bit " 1 " that check digit is " 1 " and comprise in payload is odd number, or when check digit is " 0 " and the number of the bit " 1 " comprised in payload is even number, payload meets check digit; On the contrary, when check digit is " 0 " and the number of the bit " 1 " comprised in payload is odd number, or when check digit is " 1 " and the number of the bit " 1 " comprised in payload is even number, payload does not meet check digit.
On the other hand, if check digit is even parity bit, then when the number of the bit " 1 " that check digit is " 1 " and comprise in payload is even number, or when check digit is " 0 " and the number of the bit " 1 " comprised in payload is odd number, payload meets check digit; On the contrary, when check digit is " 0 " and the number of the bit " 1 " comprised in payload is even number, or when check digit is " 1 " and the number of the bit " 1 " comprised in payload is odd number, payload does not meet check digit.
Alternatively, as another embodiment, 64B/66B encoding block comprises superframe header or common encoding block.In step 202., the synchronous head of identifiable design superframe header or the synchronous head of common encoding block, the first bit in the synchronous head of wherein superframe header is odd parity bit, and the first bit in the synchronous head of common encoding block is even parity bit; Or the synchronous head of identifiable design superframe header or the synchronous head of common encoding block, the first bit in the synchronous head of wherein superframe header is even parity bit, and the first bit in the synchronous head of common encoding block is odd parity bit.Like this, namely encoding block synchronous head information carry the parity information of encoding block, realizes the protection to coded message, meanwhile, also do not produce illegal synchronous header, thus realize two kinds of function compatibilities.
Alternatively, as another embodiment, the synchronous head of superframe header can be " 10 ", and the payload of superframe header can be " 78,50,50,50,50,50,50,50 ".Like this can the recognition mechanism of superframe header of further compatible existing 64B/66B coding protocol defined.
Other mechanism of all right compatible existing 64B/66B coding protocol of the embodiment of the present invention, as descrambling is machine-processed, GearBox is machine-processed.Such as, the process such as serioparallel exchange, synchronous head separation, Gearbox and motor synchronizing descrambling can be carried out to the encoding block of 66 received bits, obtain the synchronous head of 2 bits and the payload of 64 bits, the parity information that recycling synchronous head carries verifies payload.Like this, only to the little improvement of 64B/66B encoding block, high-precision verification need can be realized, and compatible existing 64B/66B encoding-decoding process.
In addition, it is more that the embodiment of the present invention can detect error code type, because the unit of verification protection is 66 bits of encoded blocks, therefore can distinguish single-bit error code and the error burst more than 66 bits.
Fig. 3 is the schematic diagram of an example of the system of the application embodiment of the present invention.The system 30 of Fig. 3 comprises RE (RadioEquipment, radio-frequency apparatus) 31 and REC (RadioEquipmentControl, radio-frequency apparatus controller) 32.Connected by wired mode (such as optical fiber or cable) between RE31 and REC32.Logical links between RE31 and REC32 can support CPRI agreement.
RE31 and REC32 can be used as the executive agent of the method for Fig. 1 or Fig. 2, and coding obtains 64B/66B encoding block or decodes to 64B/66B encoding block.
In one example in which, RE31 is base station, and REC32 is base station controller.Communicate by CPRI link between base station and base station controller, can the embodiment of the present invention be applied.
In another example, RE31 is the Remote Radio Unit (RRU, RadioRemoteUnit) in distributed base station, and REC32 is the baseband processing unit (BBU, BaseBandUnit) in distributed base station.Communicate by CPRI link between RRU and BBU, can the embodiment of the present invention be applied.
The embodiment of the present invention is not limited to scene example listed above, and other entities utilizing CPRI link to carry out communicating also can apply the embodiment of the present invention.These application all fall in the scope of the embodiment of the present invention.
Fig. 4 is the block diagram of the data transmission device of one embodiment of the invention.The data transmission device 40 of Fig. 4 is the transmitting terminal of data, such as, RE31 or REC32 shown in Fig. 3, comprises generation unit 41 and transmitting element 42.
Generation unit 41 generates the 64B/66B encoding block meeting CPRI agreement, and wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block.Transmitting element 42 sends the 64B/66B encoding block that generation unit 41 generates.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The data transmission device 40 of Fig. 4 can perform the method for Fig. 1, therefore for avoiding repetition, is not described in detail.Generation unit 41 can be realized by processor, and transmitting element 42 can be realized by interface or transceiver.
Alternatively, as an embodiment, generation unit 41 can generate the payload of 64B/66B encoding block, and according to the parity information of payload, generate the first bit of synchronous head as check digit, generate the radix-minus-one complement of the second bit as described first bit of synchronous head.
Alternatively, as another embodiment, the 64B/66B encoding block that generation unit 41 generates comprises superframe header and this two class of common encoding block.Particularly, generation unit 41 can according to the odd information of the payload of superframe header, generate the first bit of the synchronous head of superframe header as odd parity bit, generate the radix-minus-one complement of the second bit as the first bit of the synchronous head of superframe header, and the even parity check information of the payload according to common encoding block, the first bit generating the synchronous head of common encoding block, as even parity bit, generates the radix-minus-one complement of the second bit as described first bit of the synchronous head of common encoding block.Or, generation unit 31 can according to the even parity check information of the payload of superframe header, generate the first bit of the synchronous head of superframe header as even parity bit, generate the radix-minus-one complement of the second bit as the first bit of the synchronous head of superframe header, and the odd information of the payload according to common encoding block, the first bit generating the synchronous head of common encoding block, as odd parity bit, generates the radix-minus-one complement of the second bit as the first bit of the synchronous head of common encoding block.
Alternatively, as another embodiment, the synchronous head of the superframe header that generation unit 41 generates can be " 10 ", and the payload of superframe header can be " 78,50,50,50,50,50,50,50 ".
Like this, the 64B/66B encoding block of the embodiment of the present invention can compatible existing coding protocol, realizes high-precision verification simultaneously.
Fig. 5 is the block diagram of the data transmission device of one embodiment of the invention.The data transmission device 50 of Fig. 5 is the receiving terminal of data, such as, RE31 or REC32 shown in Fig. 3, comprises receiving element 51 and verification unit 52.
Receiving element 51 receives the 64B/66B encoding block meeting CPRI agreement, and wherein the synchronous head of 64B/66B encoding block carries the parity information of the payload of 64B/66B encoding block.The payload of parity information to 64B/66B encoding block that the synchronous head of the 64B/66B encoding block that verification unit 52 utilizes receiving element 51 to receive carries verifies.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The data transmission device 50 of Fig. 5 can perform the method for Fig. 2, therefore for avoiding repetition, is not described in detail.Receiving element 51 can be realized by interface or transceiver, and verification unit 52 can be realized by processor.
Alternatively, as another embodiment, the synchronous head of verification unit 52 identifiable design 64B/66B encoding block, the first bit wherein in synchronous head is check digit, and the second bit in synchronous head is the radix-minus-one complement of the first bit; When the payload of 64B/66B encoding block meets check digit, determine verification succeeds; When the payload of 64B/66B encoding block does not meet check digit, determine to verify unsuccessfully.
Alternatively, as another embodiment, the 64B/66B encoding block that receiving element 51 receives comprises superframe header or this two class of common encoding block.In the case, the synchronous head of verification unit 52 identifiable design superframe header or the synchronous head of common encoding block, the first bit in the synchronous head of wherein superframe header is odd parity bit, and the first bit in the synchronous head of common encoding block is even parity bit; Or the synchronous head of verification unit 52 identifiable design superframe header or the synchronous head of common encoding block, the first bit in the synchronous head of wherein superframe header is even parity bit, and the first bit in the synchronous head of common encoding block is odd parity bit.
Alternatively, as another embodiment, the synchronous head of verification unit 52 identifiable design superframe header is " 10 ", and the payload of superframe header is " 78,50,50,50,50,50,50,50 ".
Like this, the 64B/66B encoding block of the embodiment of the present invention can compatible existing coding protocol, realizes high-precision verification simultaneously.
No matter be under low error rate or high bit-error condition, the modified model 64B/66B coding of the embodiment of the present invention can detect the physical link error rate (detect the error rate and approximate the actual error rate of link) well.And the error rate is lower, the error rate precision of modified model 64B/66B coding instruction is higher.Utilize the parity checking capability that modified model 64B/66B encodes, the Link Physical Layer error code information needed for report of user, supports the mechanism of user-defined code check alarm.Modified model coding is supported to identify various forms of error code, comprises the error burst of random error or short time outburst.
Method according to the embodiment of the present invention is tested.Within the 1s time interval, the number of statistics 1.536e8 64B/66B code error, measuring and calculating link error rates, test result has higher confidence level.
Fig. 6 is the block diagram of the communication equipment of one embodiment of the invention.The communication equipment 60 of Fig. 6 can be RE31 or REC32 shown in Fig. 3, as coding side and the transmitting terminal of data.Communication equipment 60 comprises coding unit 61, scrambling unit 62, merge cells 63, parallel serial conversion unit 64 and supply unit 65.
Coding unit 61 pairs of data are encoded, and generate the payload of 64 bits, and generate the synchronous head of 2 bits, wherein synchronous head carries the parity information of payload.Like this, coding unit 61 can generate synchronous head and the payload of the 64B/66B encoding block meeting CPRI agreement.
The payload that scrambling unit 62 pairs of coding units 61 generate carries out scrambling, obtains the payload after scrambling.The scrambling mechanism of scrambling unit 62 can refer to prior art, therefore repeats no more.Such as, as a nonrestrictive embodiment, scrambling unit 62 can generate binary pseudo-random sequence, and the payload of this pseudo random sequence and 64 bits is carried out mould 2 adds computing, realizes the scrambling to payload.
The synchronous head that coding unit 61 generates is added to the payload after scrambling unit 62 scrambling by merge cells 63, obtains the encoding block of 66 bits.Alternatively, merge cells 63 can also perform other additional operations of the prior art, as speed change (GearBox) process.
Parallel serial conversion unit 64 pairs of encoding blocks carry out parallel-serial conversion process, to generate the encoding block of serial.Supply unit 65 sends the encoding block of described serial.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The communication equipment 60 of Fig. 6 can perform the method for Fig. 1, therefore for avoiding repetition, is not described in detail.Alternatively, as an embodiment, coding unit 61 can generate the check digit of the first bit as payload of synchronous head, and generates the radix-minus-one complement of the second bit as the first bit of synchronous head.In other words, the synchronous head that coding unit 61 generates can ensure as " 10 " or " 01 ", like this can compatible existing 64B/66B coding protocol.
Existing 64B/66B encoding block comprises two types, i.e. superframe header or common encoding block.Alternatively, as another embodiment, coding unit 61 can generate the payload " 78,50,50,50; 50,50,50,50 " of 64 bits and carry the synchronous head " 10 " of 2 bits of odd information of payload " 78,50,50; 50,50,50,50,50 ", as superframe header.Like this can compatible existing synchronous head form.For common encoding block, on the other hand, coding unit 61 can generate the payload of common encoding block and carry the synchronous head of even parity check information of payload of common encoding block, as the synchronous head of this common encoding block.In other words, the synchronous head of common encoding block may be " 10 " or " 01 ", is even parity check information, and the first bit namely in synchronous head is even parity bit.Like this, namely encoding block synchronous head information carry the parity information of encoding block, realizes the protection to coded message, meanwhile, also do not produce illegal synchronous header, thus realize two kinds of function compatibilities.
The operation of scrambling unit 62, merge cells 63, parallel serial conversion unit 64 and supply unit 65 can be similar to the corresponding operating of existing 64B/66B functional module, less to the variation of existing communication equipment like this, while realizing high-precision verification, compatible existing 64B/66B encoding-decoding process.
Fig. 7 is the block diagram of the communication system of another embodiment of the present invention.The communication equipment 70 of Fig. 7 can be RE31 or REC32 shown in Fig. 3, as receiving terminal and the decoding end of data.Communication equipment 70 comprises receiving element 71, serioparallel exchange unit 72, separative element 73, Descrambling unit 74 and verification unit 75.
Receiving element 71 receives the encoding block of the serial of 66 bits.The synchronous head of this encoding block carries the parity information of the payload of encoding block.Such as, this encoding block can be the 64B/66B encoding block meeting CPRI agreement exported from the communication equipment 60 of Fig. 6, but the source of the present invention to encoding block is not restricted.
The encoding block of serioparallel exchange unit 72 pairs of serials carries out serioparallel exchange process.Separative element 73 extracts the payload after the synchronous head of 2 bits and the scrambling of 64 bits from the encoding block after serioparallel exchange unit 72 carries out serioparallel exchange process.Alternatively, if need to carry out speed change (GearBox) process, separative element 73 can have the ability of variable-speed processing.
Payload after the scrambling that Descrambling unit 74 pairs of separative elements 73 extract carries out scramble process to obtain payload.The descrambling mechanism of Descrambling unit 74 can refer to prior art, therefore repeats no more.Such as, the descrambling mechanism of Descrambling unit 74 can be corresponding with the scrambling mechanism of the scrambling unit 62 of Fig. 6.
The parity information entrained by synchronous head that verification unit 75 utilizes separative element 73 to extract verifies the payload that Descrambling unit 74 obtains.
The embodiment of the present invention utilizes the synchronous head of 64B/66B encoding block to carry parity information, and to verify the payload of 64 bits of 64B/66B encoding block, the granularity of verification protection is less, improves error rate accuracy of detection.
The communication equipment 70 of Fig. 7 can perform the method for Fig. 2, therefore for avoiding repetition, is not described in detail.Alternatively, as an embodiment, verification unit 74 can extract the first bit of synchronous head as check digit, and the second bit in this synchronous head is the radix-minus-one complement of the first bit.In other words, synchronous head can ensure as " 10 " or " 01 ", like this can compatible existing 64B/66B coding protocol.
When payload meets check digit, verification unit 74 determines verification succeeds; When payload does not meet check digit, verification unit 74 is determined to verify unsuccessfully.
64B/66B encoding block can comprise superframe header or this two class of common encoding block.Alternatively, as another embodiment, the encoding block of synchronous head " 10 " of 2 bits of the payload " 78,50,50,50; 50,50,50,50 " with 64 bits and the odd information of carrying payload " 78,50,50; 50,50,50,50,50 " can be identified as superframe header by verification unit 74.On the other hand, for common encoding block, the payload of even parity check information to common encoding block that verification unit 74 can utilize the synchronous head of common encoding block to carry verifies.In other words, the synchronous head of common encoding block may be " 10 " or " 01 ", is even parity check information, and the first bit namely in synchronous head is even parity bit.Like this, namely encoding block synchronous head information carry the parity information of encoding block, realizes the protection to coded message, meanwhile, also do not produce illegal synchronous header, thus realize two kinds of function compatibilities.
Receiving element 71, serioparallel exchange unit 72, separative element 73 and Descrambling unit 74 can be similar to the corresponding operating of existing 64B/66B functional module, less to the variation of existing communication equipment like this, while realizing high-precision verification, compatible existing 64B/66B encoding-decoding process.
Those of ordinary skill in the art can recognize, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with the combination of electronic hardware or computer software and electronic hardware.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
Those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the system of foregoing description, device and unit, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
In several embodiments that the application provides, should be understood that disclosed system, apparatus and method can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or unit or communication connection can be electrical, machinery or other form.
The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated.
If described function using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part of the part that technical scheme of the present invention contributes to prior art in essence in other words or this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection range of claim.
Claims (8)
1. a data transmission method, is characterized in that, comprising:
Generate the 64B/66B encoding block meeting common public radio interface CPRI agreement,
The synchronous head of wherein said 64B/66B encoding block carries the parity information of the payload of described 64B/66B encoding block; Described generation meets the 64B/66B encoding block of common public radio interface CPRI agreement, comprising: the payload generating described 64B/66B encoding block; According to the parity information of described payload, the first bit generating described synchronous head, as check digit, generates the radix-minus-one complement of the second bit as described first bit of described synchronous head;
Described 64B/66B encoding block comprises superframe header or common encoding block, the described parity information according to described payload, generate the first bit of described synchronous head as check digit, generate the radix-minus-one complement of the second bit as described first bit of described synchronous head, comprise: according to the odd information of the payload of described superframe header, generate the first bit of the synchronous head of described superframe header as odd parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described superframe header, and the even parity check information of the payload according to described common encoding block, generate the first bit of the synchronous head of described common encoding block as even parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described common encoding block, or, according to the even parity check information of the payload of described superframe header, generate the first bit of the synchronous head of described superframe header as even parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described superframe header, and the odd information of the payload according to described common encoding block, the first bit generating the synchronous head of described common encoding block, as odd parity bit, generates the radix-minus-one complement of the second bit as described first bit of the synchronous head of described common encoding block,
Send described 64B/66B encoding block.
2. the method for claim 1, is characterized in that, the synchronous head of described superframe header is " 10 ", and the payload of described superframe header is " 78,50,50,50,50,50,50,50 ".
3. a data transmission method, is characterized in that, comprising:
Receive the 64B/66B encoding block meeting common public radio interface CPRI agreement, the synchronous head of wherein said 64B/66B encoding block carries the parity information of the payload of described 64B/66B encoding block;
The payload of the parity information utilizing described synchronous head to carry to described 64B/66B encoding block verifies, the payload of the described parity information utilizing described synchronous head to carry to described 64B/66B encoding block verifies, comprise: the synchronous head identifying described 64B/66B encoding block, the first bit in wherein said synchronous head is check digit, and the second bit in described synchronous head is the radix-minus-one complement of described first bit; When the payload of described 64B/66B encoding block meets described check digit, determine verification succeeds; When the payload of described 64B/66B encoding block does not meet described check digit, determine to verify unsuccessfully;
Described 64B/66B encoding block comprises superframe header or common encoding block, the synchronous head of the described 64B/66B encoding block of described identification, the first bit in wherein said synchronous head is check digit, comprise: identify the synchronous head of described superframe header or the synchronous head of described common encoding block, the first bit in the synchronous head of wherein said superframe header is odd parity bit, and the first bit in the synchronous head of described common encoding block is even parity bit; Or identify the synchronous head of described superframe header or the synchronous head of described common encoding block, the first bit in the synchronous head of wherein said superframe header is even parity bit, and the first bit in the synchronous head of described common encoding block is odd parity bit.
4. method as claimed in claim 3, it is characterized in that, the synchronous head of described superframe header is " 10 ", and the payload of described superframe header is " 78,50,50,50,50,50,50,50 ".
5. a data transmission device, is characterized in that, comprising:
Generation unit, for generating the 64B/66B encoding block meeting common public radio interface CPRI agreement, the synchronous head of wherein said 64B/66B encoding block carries the parity information of the payload of described 64B/66B encoding block;
Described generation unit is specifically for generating the payload of described 64B/66B encoding block, and according to the parity information of described payload, the first bit generating described synchronous head, as check digit, generates the radix-minus-one complement of the second bit as described first bit of described synchronous head;
The 64B/66B encoding block that described generation unit generates comprises superframe header and common encoding block, described generation unit is specifically for the odd information of the payload according to described superframe header, generate the first bit of the synchronous head of described superframe header as odd parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described superframe header, and the even parity check information of the payload according to described common encoding block, generate the first bit of the synchronous head of described common encoding block as even parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described common encoding block, or, described generation unit is specifically for the even parity check information of the payload according to described superframe header, generate the first bit of the synchronous head of described superframe header as even parity bit, generate the radix-minus-one complement of the second bit as described first bit of the synchronous head of described superframe header, and the odd information of the payload according to described common encoding block, the first bit generating the synchronous head of described common encoding block, as odd parity bit, generates the radix-minus-one complement of the second bit as described first bit of the synchronous head of described common encoding block,
Transmitting element, for sending the 64B/66B encoding block that described generation unit generates.
6. a data transmission device, is characterized in that, comprising:
Receiving element, for receiving the 64B/66B encoding block meeting common public radio interface CPRI agreement, the synchronous head of wherein said 64B/66B encoding block carries the parity information of the payload of described 64B/66B encoding block;
Verification unit, the payload of parity information to described 64B/66B encoding block that the synchronous head of the 64B/66B encoding block received for utilizing described receiving element carries verifies;
Described verification unit is specifically for identifying the synchronous head of described 64B/66B encoding block, and the first bit in wherein said synchronous head is check digit, and the second bit in described synchronous head is the radix-minus-one complement of described first bit; When the payload of described 64B/66B encoding block meets described check digit, determine verification succeeds; When the payload of described 64B/66B encoding block does not meet described check digit, determine to verify unsuccessfully;
The 64B/66B encoding block that described receiving element receives comprises superframe header or common encoding block, described verification unit is specifically for the synchronous head of the synchronous head or described common encoding block that identify described superframe header, the first bit in the synchronous head of wherein said superframe header is odd parity bit, and the first bit in the synchronous head of described common encoding block is even parity bit; Or, described verification unit is specifically for the synchronous head of the synchronous head or described common encoding block that identify described superframe header, the first bit in the synchronous head of wherein said superframe header is even parity bit, and the first bit in the synchronous head of described common encoding block is odd parity bit.
7. a communication equipment, is characterized in that, comprising:
Coding unit, for encoding to data, generate the payload of 64 bits, and generate the synchronous head of 2 bits, wherein said synchronous head carries the parity information of described payload;
Described coding unit specifically for generating the check digit of the first bit as described payload of described synchronous head, and generates the radix-minus-one complement of the second bit as described first bit of described synchronous head;
Described coding unit is specifically for generating the payload " 78,50,50,50,50,50,50,50 " of 64 bits and carrying the synchronous head " 10 " of 2 bits of odd information of payload " 78,50,50,50,50,50,50,50 ", as superframe header; Or described coding unit is specifically for generating the payload of common encoding block and carrying the synchronous head of even parity check information of payload of described common encoding block, as described common encoding block;
Scrambling unit, carries out scrambling for the payload generated described coding unit, obtains the payload after scrambling;
Merge cells, the synchronous head for being generated by described coding unit adds the payload after described scrambling unit scrambling to, obtains the encoding block of 66 bits;
Parallel serial conversion unit, for carrying out parallel-serial conversion process to described encoding block, to generate the encoding block of serial;
Supply unit, for sending the encoding block of described serial.
8. a communication equipment, is characterized in that, comprising:
Receiving element, for receiving the encoding block of the serial of 66 bits, the synchronous head of described encoding block carries the parity information of the payload of described encoding block;
Serioparallel exchange unit, for carrying out serioparallel exchange process to the encoding block of described serial;
Separative element, for extracting the payload after the synchronous head of 2 bits and the scrambling of 64 bits in the encoding block after carrying out serioparallel exchange process from described serioparallel exchange unit;
Descrambling unit, carries out scramble process to obtain described payload for the payload after the scrambling of extracting described separative element;
Verification unit, the parity information entrained by the described synchronous head extracted for utilizing described separative element verifies the described payload that described Descrambling unit obtains;
Described verification unit is specifically for extracting the first bit of described synchronous head as check digit, and the second bit in described synchronous head is the radix-minus-one complement of described first bit; When described payload meets described check digit, determine verification succeeds; When described payload does not meet described check digit, determine to verify unsuccessfully;
Described verification unit is specifically for being identified as superframe header by the encoding block of synchronous head " 10 " of 2 bits of the payload " 78,50,50,50,50; 50,50,50 " with 64 bits and the odd information of carrying payload " 78,50,50; 50,50,50,50,50 "; Or described verification unit verifies specifically for the payload of even parity check information to described common encoding block utilizing the synchronous head of common encoding block and carry.
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| WO2018103083A1 (en) * | 2016-12-09 | 2018-06-14 | 华为技术有限公司 | Protocol conversion method and device |
| CN114584260B (en) * | 2017-07-27 | 2024-02-13 | 苹果公司 | Scrambling of Physical Broadcast Channel (PBCH) |
| CN109672507A (en) * | 2019-01-04 | 2019-04-23 | 烽火通信科技股份有限公司 | The detection method and system of the bit error rate in a kind of network |
| CN113242243A (en) * | 2021-05-12 | 2021-08-10 | 江苏亨鑫众联通信技术有限公司 | Super-bandwidth signal transmission method and system |
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| CN1881866A (en) * | 2005-06-16 | 2006-12-20 | 联咏科技股份有限公司 | Data transmission fault monitoring and correcting method and its structure |
| CN101267210A (en) * | 2007-03-12 | 2008-09-17 | 华为技术有限公司 | Data decoding and coding and receiving/transmission method and device |
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| CN1881866A (en) * | 2005-06-16 | 2006-12-20 | 联咏科技股份有限公司 | Data transmission fault monitoring and correcting method and its structure |
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Effective date of registration: 20210421 Address after: Unit 3401, unit a, building 6, Shenye Zhongcheng, No. 8089, Hongli West Road, Donghai community, Xiangmihu street, Futian District, Shenzhen, Guangdong 518040 Patentee after: Honor Device Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |