CN103199953A - Method and device for data transmission and communication equipment - Google Patents
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Abstract
An embodiment of the invention provides a method and a device for data transmission. The method includes the following steps that a 64B / 66B code block fitting with a common public radio interface (CPRI) protocol is generated, wherein a synchronous head of the 64B / 66B code block carries odd-even check information of effective loads of the 64B / 66B code block; and the 64B / 66B code block is sent. According to the method and the device, the odd-even check information is carried by the synchronous head of the 64B / 66B code block to check the 64-bit effective load of the 64B / 66B code block, the particle size of check protection is small, and error code rate detection precision is improved.
Description
Technical Field
The embodiment of the invention relates to the field of wireless communication, in particular to a data transmission method and device and a communication device.
Background
Simulation research shows that the bit error rate of a Common Public Radio Interface (CPRI) link has a large influence on a wireless transmission channel. For example, when RB (resource block) is 1, the error rate of the CPRI link has no great influence on the performance of wireless channel transmission, and has little influence on performance loss. As the number of RBs increases, the CPRI link error rate has an increasing impact on system performance. When RB is 50, the CPRI link error rate is 1.0e-5, the performance loss is unacceptable, and meanwhile, the CPRI link error rate is 1.0e-7, which can be estimated to have unacceptable influence on the system performance, by considering the compression ratio and the margin.
Therefore, the physical link bottom layer needs an error rate detection mechanism, which can effectively identify the error rate magnitude of the CPRI link and report an alarm when the error rate of the link is found to be higher than a specific value (e.g. 1.0 e-7).
In the prior art, a Cyclic Redundancy Check (CRC) 16 Check is performed on each base frame by using data information in the base frame. However, the basic unit of CRC protection is a base frame, the granularity is large (for example, for a CPRI protocol with a rate of 10G, the size of the base frame is 2560 bits), the detection accuracy is poor, and the error rate of the link cannot be accurately detected.
Disclosure of Invention
The embodiment of the invention provides a data transmission method, a data transmission device and communication equipment, which can solve the problem of poor error rate detection precision.
In one aspect, a data transmission method is provided, including: generating a 64B/66B coding block which conforms to the CPRI protocol, wherein the synchronous head of the 64B/66B coding block carries the parity check information of the payload of the 64B/66B coding block; the 64B/66B encoded block is sent.
In another aspect, a data transmission method is provided, including: receiving a 64B/66B coding block which conforms to a CPRI protocol, wherein a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block; the payload of the 64B/66B encoded block is checked using the parity information carried by the sync header.
In another aspect, a data transmission apparatus is provided, including: a generating unit, configured to generate a 64B/66B coding block compliant with the CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity information of a payload of the 64B/66B coding block; and the sending unit is used for sending the 64B/66B coding block.
In another aspect, a data transmission apparatus is provided, including: a receiving unit, configured to receive a 64B/66B coding block that conforms to a CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity information of a payload of the 64B/66B coding block; and the checking unit is used for checking the payload of the 64B/66B coding block by using the parity check information carried by the synchronous head.
In another aspect, a communication device is provided, including: the encoding unit is used for encoding data, generating a 64-bit payload and generating a 2-bit synchronization header, wherein the synchronization header carries parity check information of the payload; the scrambling unit is used for scrambling the effective load generated by the coding unit to obtain the scrambled effective load; a merging unit, configured to add the synchronization header generated by the encoding unit to the payload scrambled by the scrambling unit, so as to obtain a 66-bit encoded block; the parallel-serial conversion unit is used for carrying out parallel-serial conversion processing on the coding blocks to generate serial coding blocks; and the conveying unit is used for transmitting the serial coding blocks.
In another aspect, a communication device is provided, including: a receiving unit, configured to receive a 66-bit serial coding block, where a synchronization header of the coding block carries parity information of a payload of the coding block; a serial-to-parallel conversion unit, configured to perform serial-to-parallel conversion processing on the serial coding blocks; a separation unit, configured to extract a 2-bit synchronization header and a 64-bit scrambled payload from the coding block subjected to the serial-to-parallel conversion by the serial-to-parallel conversion unit; a descrambling unit, configured to perform descrambling processing on the scrambled payload extracted by the separation unit to obtain the payload; and the checking unit is used for checking the effective load obtained by the descrambling unit by using the parity check information carried by the synchronous head extracted by the separation unit.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present invention.
Fig. 2 is a flowchart of a data transmission method according to another embodiment of the present invention.
FIG. 3 is a schematic diagram of one example of a system to which embodiments of the invention are applied.
Fig. 4 is a block diagram of a data transmission apparatus according to an embodiment of the present invention.
Fig. 5 is a block diagram of a data transmission apparatus according to an embodiment of the present invention.
Fig. 6 is a block diagram of a communication device of one embodiment of the present invention.
Fig. 7 is a block diagram of a communication system of another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical scheme of the invention can be applied to various communication systems, such as: global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), General Packet Radio Service (GPRS), Long Term Evolution (LTE), and the like.
User Equipment (UE), also referred to as mobile terminal (mobile terminal), mobile User Equipment, etc., may communicate with one or more core networks via a Radio access network (e.g., RAN), and may be mobile terminals, such as mobile phones (or "cellular" phones) and computers having mobile terminals, such as portable, pocket, hand-held, computer-included, or vehicle-mounted mobile devices, that exchange language and/or data with the Radio access network.
The Base Station may be a Base Transceiver Station (BTS) in GSM or CDMA, a Base Station (NodeB) in WCDMA, or an evolved Node B (eNB or e-NodeB) in LTE, but the present invention is not limited thereto, and for convenience of description, the Node B is taken as an example in the following embodiments.
Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present invention. The method of fig. 1 is performed by a transmitting end of data, such as a base station, base station controller, or other entity.
And 101, generating a 64B/66B coding block conforming to the CPRI protocol, wherein the synchronous head of the 64B/66B coding block carries the parity check information of the payload of the 64B/66B coding block.
The 64B/66B coding block conforming to the CPRI protocol has 66 bits, the first two bits are a synchronization header (SyncHead), and the last 64 bits are a Payload (Payload).
And 102, transmitting the 64B/66B coding block.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The conventional CRC check protection unit is a base frame, and the granularity is large (for example, for a CPRI protocol with a 10G rate, the base frame size is 2560 bits); the check protection unit of the embodiment of the invention is a 64B/66B coding block, the size is 66 bits, the granularity is smaller than the protection granularity of CRC, and the error rate detection precision can be improved.
In addition, the embodiment of the invention uses the redundancy of the synchronous head of the existing 64B/66B coding block as parity check, and the complexity of realization is lower. Compared with the traditional CRC check which occupies extra data bandwidth, the check mode of the embodiment of the invention can save resources.
Optionally, as an embodiment, in step 101, a payload of the 64B/66B encoded block may be generated, and according to parity information of the payload, a first bit of the synchronization header may be generated as a check bit, and a second bit of the synchronization header may be generated as an inverse code of the first bit. In other words, the sync header of the 64B/66B encoded block generated in step 101 can be guaranteed to be "10" or "01", which enables compatibility with existing 64B/66B encoding protocols.
The 64B/66B coding blocks include two types, i.e., super frame header (superframe) or normal coding block. Alternatively, as another embodiment, the parity check patterns for the two types of 64B/66B encoded blocks may be different. For example, in one example, a first bit of the synchronization header of the super-frame header may be generated as an odd parity bit and a second bit of the synchronization header of the super-frame header may be generated as an inverse of the first bit based on odd parity information of the payload of the super-frame header; at this time, a first bit of the sync header of the normal coding block may be generated as an even parity bit and a second bit of the sync header of the normal coding block may be generated as an inverse of the first bit, based on the even parity information of the payload of the normal coding block.
In another example, a first bit of the sync header of the super-frame header may be generated as an even parity bit and a second bit of the sync header of the super-frame header may be generated as an inverse of the first bit based on even parity information of the payload of the super-frame header, and the first bit of the sync header of the normal coding block may be generated as an odd parity bit and the second bit of the sync header of the normal coding block may be generated as an inverse of the first bit based on odd parity information of the payload of the normal coding block. Therefore, the coded block synchronous header information carries the parity check information of the coded block, the coded information is protected, meanwhile, the illegal synchronous header information is not generated, and the compatibility of two functions is realized.
Alternatively, as another embodiment, the synchronization header of the superframe header may be "10", and the payload of the superframe header is "78, 50, 50, 50, 50, 50, 50", so that the identification mechanism of the superframe header specified by the existing 64B/66B coding protocol can be further compatible. The receiving end can recognize the '10' sync header signal transmitted by the code and recognize whether the superframe header payload information therein corresponds to the expected control word information '78, 50, 50, 50, 50, 50, 50, 50'. In this specific example, since the binary bit of 78 is 01001110(4 "1"), and the binary bit of 50 is 00110010(3 "1"), the payload of the superframe header includes 25 "1" s, 4+3 × 7. Thus, the sync header "10" is odd parity information, i.e., the first bit in the sync header (in this case, "1") is an odd parity bit. The synchronization header of a normal coding block may be "10" or "01", and both are even parity information, i.e. the first bit in the synchronization header is an even parity bit.
Of course, the specific format of the superframe header is not limited in the embodiments of the present invention. If the payload of the super-frame header is other values and satisfies the even parity, the sync header "10" may be determined to be even parity information.
The embodiment of the invention can also be compatible with other mechanisms of the existing 64B/66B coding protocol, such as a scrambling mechanism, a GearBox (transmission) mechanism and the like. For example, the unscrambled payload of the normal encoded block may be parity checked to determine whether the sync header of the normal encoded block is "10" or "01". Then, the payload is processed by self-synchronization scrambling, synchronization header addition and Gearbox, parallel-serial conversion and the like, and a 66-bit coding block is output. Therefore, the high-precision check can be realized only by small improvement on the 64B/66B coding block, and the method is compatible with the existing 64B/66B coding and decoding process.
In addition, the embodiment of the invention can detect more error code types, and the unit of check protection is a 66-bit coding block, so that single-bit error codes and burst error codes exceeding 66 bits can be distinguished.
Fig. 2 is a flowchart of a data transmission method according to another embodiment of the present invention. The method of fig. 2 is performed by a receiving end (e.g., a base station controller, or other entity).
And 201, receiving a 64B/66B coding block conforming to the CPRI protocol, wherein the synchronous head of the 64B/66B coding block carries the parity check information of the payload of the 64B/66B coding block.
The payload of the 64B/66B encoded block is checked 202 using the parity information carried by the sync header.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The method of fig. 2 corresponds to the method of fig. 1, and thus detailed description will be appropriately omitted.
Optionally, as an embodiment, in step 202, a sync header of the 64B/66B encoded block may be identified, wherein a first bit in the sync header is a parity bit and a second bit in the sync header is an inverse of the first bit. When the payload of the 64B/66B coding block accords with the check bit, determining that the check is successful; the check is determined to fail when the payload of the 64B/66B encoded block does not conform to the check bits. Thus, the synchronous head of the 64B/66B coding block can be guaranteed to be 10 or 01, and the existing 64B/66B coding protocol can be compatible. By payload conforming to a parity bit, it is meant that the number of bits "1" contained in the payload is consistent with the indication of the parity bit, which is the same definition as parity in the prior art. For example, if the parity bit is an odd parity bit, the payload conforms to the parity bit when the parity bit is "1" and the number of bits "1" included in the payload is an odd number, or when the parity bit is "0" and the number of bits "1" included in the payload is an even number; in contrast, when the parity is "0" and the number of bits "1" included in the payload is an odd number, or when the parity is "1" and the number of bits "1" included in the payload is an even number, the payload does not conform to the parity.
On the other hand, if the parity bit is an even parity bit, the payload conforms to the parity bit when the parity bit is "1" and the number of bits "1" included in the payload is an even number, or when the parity bit is "0" and the number of bits "1" included in the payload is an odd number; in contrast, when the parity is "0" and the number of bits "1" included in the payload is an even number, or when the parity is "1" and the number of bits "1" included in the payload is an odd number, the payload does not conform to the parity.
Optionally, as another embodiment, the 64B/66B coding block includes a super-frame header or a normal coding block. In step 202, a synchronization header of a super frame header or a synchronization header of a normal coding block can be identified, wherein a first bit in the synchronization header of the super frame header is an odd parity bit, and a first bit in the synchronization header of the normal coding block is an even parity bit; or, the synchronization header of the super frame header or the synchronization header of the ordinary coding block can be identified, wherein the first bit in the synchronization header of the super frame header is an even check bit, and the first bit in the synchronization header of the ordinary coding block is an odd check bit. . Therefore, the coded block synchronous header information carries the parity check information of the coded block, the coded information is protected, meanwhile, the illegal synchronous header information is not generated, and the compatibility of two functions is realized.
Alternatively, as another embodiment, the sync header of the superframe header may be "10" and the payload of the superframe header may be "78, 50, 50, 50, 50, 50, 50, 50". This further allows for compatibility with existing header identification mechanisms specified by the 64B/66B coding protocol.
The embodiment of the invention can also be compatible with other mechanisms of the existing 64B/66B coding protocol, such as a descrambling mechanism, a GearBox mechanism and the like. For example, the received 66-bit coding block may be subjected to serial-to-parallel conversion, sync header separation, georbox and self-sync descrambling, etc., to obtain a 2-bit sync header and a 64-bit payload, and then the payload may be checked by using parity information carried by the sync header. Therefore, the high-precision check can be realized only by small improvement on the 64B/66B coding block, and the method is compatible with the existing 64B/66B coding and decoding process.
In addition, the embodiment of the invention can detect more error code types, and the unit of check protection is a 66-bit coding block, so that single-bit error codes and burst error codes exceeding 66 bits can be distinguished.
FIG. 3 is a schematic diagram of one example of a system to which embodiments of the invention are applied. The system 30 of fig. 3 includes an RE (Radio Equipment) 31 and an REC (Radio Equipment controller) 32. The RE 31 and the REC 32 are connected by wire (e.g., fiber or cable). The logical link between the RE 31 and the REC 32 may support the CPRI protocol.
The RE 31 and the REC 32 can be used as the execution bodies of the methods of FIG. 1 or FIG. 2, and the encoding is carried out to obtain a 64B/66B coding block or to decode the 64B/66B coding block.
In one example, the RE 31 is a base station and the REC 32 is a base station controller. The base station and the base station controller can communicate through a CPRI link, and the embodiment of the invention can be applied.
In another example, the RE 31 is a Radio Remote Unit (RRU) in a distributed Base station, and the REC 32 is a baseband processing Unit (BBU) in the distributed Base station. The RRU and the BBU can communicate through a CPRI link, and the embodiment of the invention can be applied.
The embodiments of the present invention are not limited to the above-mentioned scenario examples, and other entities using the CPRI link for communication may also apply the embodiments of the present invention. Such applications fall within the scope of embodiments of the present invention.
Fig. 4 is a block diagram of a data transmission apparatus according to an embodiment of the present invention. The data transmission apparatus 40 of fig. 4 is a transmitting end of data, such as the RE 31 or REC 32 shown in fig. 3, and includes a generating unit 41 and a transmitting unit 42.
The generation unit 41 generates a 64B/66B coded block conforming to the CPRI protocol, wherein the sync header of the 64B/66B coded block carries parity information of the payload of the 64B/66B coded block. The transmission unit 42 transmits the 64B/66B encoded block generated by the generation unit 41.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The data transmission device 40 of fig. 4 may perform the method of fig. 1, and thus, in order to avoid repetition, will not be described in detail. The generating unit 41 may be implemented by a processor and the transmitting unit 42 may be implemented by an interface or a transceiver.
Alternatively, as an embodiment, the generating unit 41 may generate the payload of the 64B/66B encoded block, and generate the first bit of the sync header as the check bit and the second bit of the sync header as the complement of the first bit according to the parity information of the payload.
Optionally, as another embodiment, the 64B/66B coding blocks generated by the generating unit 41 include both super frame headers and normal coding blocks. Specifically, the generating unit 41 may generate a first bit of the sync header of the super-frame header as an odd parity bit and a second bit of the sync header of the super-frame header as an inverse of the first bit according to odd parity information of the payload of the super-frame header, and generate a first bit of the sync header of the normal coding block as an even parity bit and a second bit of the sync header of the normal coding block as an inverse of the first bit according to even parity information of the payload of the normal coding block. Alternatively, the generating unit 31 may generate a first bit of the sync header of the super-frame header as an even parity bit and a second bit of the sync header of the super-frame header as an inverse of the first bit according to the even parity information of the payload of the super-frame header, and generate the first bit of the sync header of the normal coding block as an odd parity bit and the second bit of the sync header of the normal coding block as an inverse of the first bit according to the odd parity information of the payload of the normal coding block.
Alternatively, as another embodiment, the sync header of the super frame header generated by the generation unit 41 may be "10", and the payload of the super frame header may be "78, 50, 50, 50, 50, 50, 50.
Thus, the 64B/66B coding block of the embodiment of the invention can be compatible with the existing coding protocol, and meanwhile, high-precision verification is realized.
Fig. 5 is a block diagram of a data transmission apparatus according to an embodiment of the present invention. The data transmission apparatus 50 of fig. 5 is a receiving end of data, such as the RE 31 or REC 32 shown in fig. 3, and includes a receiving unit 51 and a checking unit 52.
The receiving unit 51 receives a 64B/66B coded block conforming to the CPRI protocol, wherein a sync header of the 64B/66B coded block carries parity information of a payload of the 64B/66B coded block. The checking unit 52 checks the payload of the 64B/66B encoded block using the parity information carried by the sync header of the 64B/66B encoded block received by the receiving unit 51.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The data transmission device 50 of fig. 5 may perform the method of fig. 2, and thus, in order to avoid repetition, will not be described in detail. The receiving unit 51 may be implemented by an interface or a transceiver and the checking unit 52 may be implemented by a processor.
Optionally, as another embodiment, the checking unit 52 may identify a sync header of the 64B/66B encoded block, wherein a first bit in the sync header is a check bit and a second bit in the sync header is an inverse of the first bit; when the payload of the 64B/66B coding block accords with the check bit, determining that the check is successful; the check is determined to fail when the payload of the 64B/66B encoded block does not conform to the check bits.
Optionally, as another embodiment, the 64B/66B coding blocks received by the receiving unit 51 include both super frame headers and normal coding blocks. In this case, the verification unit 52 may identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an odd parity bit and a first bit in the synchronization header of the normal coding block is an even parity bit; alternatively, the checking unit 52 may identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an even check bit and a first bit in the synchronization header of the normal coding block is an odd check bit.
Alternatively, as another embodiment, the checking unit 52 may identify that the synchronization header of the super frame header is "10" and the payload of the super frame header is "78, 50, 50, 50, 50, 50, 50".
Thus, the 64B/66B coding block of the embodiment of the invention can be compatible with the existing coding protocol, and meanwhile, high-precision verification is realized.
The improved 64B/66B coding of the embodiment of the invention can well detect the error rate of the physical link (the detected error rate is approximately equal to the actual error rate of the link) under the conditions of low error rate and high error rate. And the lower the bit error rate, the higher the bit error rate accuracy indicated by the modified 64B/66B encoding. And reporting the error code information of a link physical layer required by a user by using the parity check capability of the improved 64B/66B code, and supporting a mechanism of code rate alarm defined by the user. Improved coding supports the identification of various forms of errors, including random errors or short bursts of burst errors.
Tests were performed according to the method of the present invention. And in the 1s time interval, counting 1.536e8 64B/66B coding errors, measuring and calculating the link error rate, wherein the test result has higher confidence.
Fig. 6 is a block diagram of a communication device of one embodiment of the present invention. The communication device 60 of fig. 6 may be the RE 31 or REC 32 shown in fig. 3 as an encoding end and a transmitting end of data. The communication apparatus 60 includes an encoding unit 61, a scrambling unit 62, a merging unit 63, a parallel-serial conversion unit 64, and a conveying unit 65.
The encoding unit 61 encodes the data, generates a 64-bit payload, and generates a 2-bit synchronization header, which carries parity information of the payload. In this way, the encoding unit 61 can generate a sync header and payload of a 64B/66B encoded block conforming to the CPRI protocol.
The scrambling unit 62 scrambles the payload generated by the encoding unit 61, and obtains a scrambled payload. The scrambling mechanism of the scrambling unit 62 can refer to the prior art, and thus is not described in detail. For example, as a non-limiting example, scrambling unit 62 may generate a binary pseudorandom sequence and perform a modulo-2 addition of the pseudorandom sequence to a 64-bit payload to achieve scrambling of the payload.
The merging unit 63 adds the synchronization header generated by the encoding unit 61 to the payload scrambled by the scrambling unit 62, and obtains a 66-bit encoded block. Alternatively, the merging unit 63 may also perform other additional operations in the related art, such as a variable speed (GearBox) process.
The parallel-to-serial conversion unit 64 performs a parallel-to-serial conversion process on the encoded blocks to generate serial encoded blocks. The transport unit 65 transmits the serial encoded blocks.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The communication device 60 of fig. 6 may perform the method of fig. 1 and therefore will not be described in detail to avoid repetition. Alternatively, as an embodiment, the encoding unit 61 may generate a first bit of the synchronization header as a parity bit of the payload, and generate a second bit of the synchronization header as an inverse code of the first bit. In other words, the sync header generated by the encoding unit 61 can be guaranteed to be "10" or "01", which enables compatibility with the existing 64B/66B encoding protocol.
The existing 64B/66B coding blocks include two types, i.e., super-frame headers or normal coding blocks. Alternatively, as another embodiment, the encoding unit 61 may generate 64-bit payload "78, 50, 50, 50, 50, 50, 50" and 2-bit synchronization header "10" carrying odd parity information of the payload "78, 50, 50, 50, 50, 50, 50" as the super-frame header. This enables compatibility with existing sync header formats. For a normal coding block, on the other hand, the encoding unit 61 may generate the payload of the normal coding block and a synchronization header carrying even parity information of the payload of the normal coding block as the synchronization header of the normal coding block. In other words, the sync header of a normal coding block may be "10" or "01", both being even parity information, i.e. the first bit in the sync header is an even parity bit. Therefore, the coded block synchronous header information carries the parity check information of the coded block, the coded information is protected, meanwhile, the illegal synchronous header information is not generated, and the compatibility of two functions is realized.
The operations of the scrambling unit 62, the merging unit 63, the parallel-serial conversion unit 64 and the conveying unit 65 can be similar to the corresponding operations of the existing 64B/66B functional module, so that the change of the existing communication equipment is small, and the existing 64B/66B coding and decoding processes are compatible while high-precision verification is realized.
Fig. 7 is a block diagram of a communication system of another embodiment of the present invention. The communication device 70 of fig. 7 may be the RE 31 or REC 32 shown in fig. 3 as a receiving end and a decoding end of data. The communication apparatus 70 includes a receiving unit 71, a serial-parallel conversion unit 72, a separation unit 73, a descrambling unit 74, and a verification unit 75.
The receiving unit 71 receives a 66-bit serial encoded block. The sync header of the coding block carries parity information for the payload of the coding block. For example, the coding block may be a 64B/66B coding block conforming to the CPRI protocol output from the communication device 60 of fig. 6, but the source of the coding block is not limited by the present invention.
The serial-parallel conversion unit 72 performs serial-parallel conversion processing on the serial coded blocks. The separation unit 73 extracts a 2-bit sync header and a 64-bit scrambled payload from the coded block subjected to the serial-parallel conversion processing by the serial-parallel conversion unit 72. Alternatively, the separation unit 73 may have a capacity of a variable speed process if a variable speed (GearBox) process is required.
The descrambling unit 74 performs descrambling processing on the scrambled payload extracted by the separation unit 73 to obtain a payload. The descrambling mechanism of the descrambling unit 74 can be referred to in the prior art, and therefore, will not be described in detail. For example, the descrambling mechanism of descrambling unit 74 may correspond to the scrambling mechanism of scrambling unit 62 of fig. 6.
The verification unit 75 verifies the payload obtained by the descrambling unit 74 using the parity information carried by the sync header extracted by the separation unit 73.
The embodiment of the invention utilizes the synchronous head of the 64B/66B coding block to carry parity check information to check the 64-bit effective load of the 64B/66B coding block, the check protection granularity is smaller, and the error rate detection precision is improved.
The communication device 70 of fig. 7 may perform the method of fig. 2 and therefore will not be described in detail to avoid repetition. Optionally, as an embodiment, the checking unit 74 may extract a first bit of the synchronization header as a check bit, and a second bit of the synchronization header is an inverse code of the first bit. In other words, the sync header can be guaranteed to be "10" or "01", which enables compatibility with existing 64B/66B encoding protocols.
When the payload conforms to the check bits, the check unit 74 determines that the check is successful; when the payload does not conform to the parity bits, the parity element 74 determines that the parity failed.
The 64B/66B coding blocks may include both super-frame headers and normal coding blocks. Alternatively, as another embodiment, the checking unit 74 may recognize the coded block of the 2-bit sync header "10" having the payload "78, 50, 50, 50, 50, 50" of 64 bits and the odd check information carrying the payload "78, 50, 50, 50, 50, 50, 50" as the super frame header. On the other hand, for the normal coding block, the checking unit 74 may check the payload of the normal coding block by using even checking information carried by the synchronization header of the normal coding block. In other words, the sync header of a normal coding block may be "10" or "01", both being even parity information, i.e. the first bit in the sync header is an even parity bit. Therefore, the coded block synchronous header information carries the parity check information of the coded block, the coded information is protected, meanwhile, the illegal synchronous header information is not generated, and the compatibility of two functions is realized.
The receiving unit 71, the serial-parallel conversion unit 72, the separation unit 73 and the descrambling unit 74 can operate similarly to the existing 64B/66B functional module, so that the existing communication equipment has small change, and the existing 64B/66B coding and decoding processes are compatible while high-precision verification is realized.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (20)
1. A method of data transmission, comprising:
generating a 64B/66B coding block which conforms to a Common Public Radio Interface (CPRI) protocol, wherein a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;
and sending the 64B/66B coding block.
2. The method of claim 1, wherein generating a 64B/66B coded block compliant with a common public radio interface, CPRI, protocol comprises:
generating a payload of the 64B/66B encoded block;
and generating a first bit of the synchronous head as a check bit and a second bit of the synchronous head as an inverse code of the first bit according to the parity check information of the payload.
3. The method of claim 2, wherein the 64B/66B coding blocks comprise super-frame headers or normal coding blocks,
the generating a first bit of the synchronization header as a check bit and a second bit of the synchronization header as an inverse of the first bit according to the parity information of the payload includes:
generating a first bit of a synchronization head of the super frame header as an odd check bit and a second bit of the synchronization head of the super frame header as an inverse code of the first bit according to odd check information of a payload of the super frame header, and generating a first bit of the synchronization head of the common coding block as an even check bit and a second bit of the synchronization head of the common coding block as an inverse code of the first bit according to even check information of the payload of the common coding block; or,
generating a first bit of a synchronization head of the super frame header as an even check bit and a second bit of the synchronization head of the super frame header as an inverse code of the first bit according to even check information of a payload of the super frame header, and generating the first bit of the synchronization head of the common coding block as an odd check bit and the second bit of the synchronization head of the common coding block as an inverse code of the first bit according to odd check information of the payload of the common coding block.
4. The method of claim 3, wherein the sync header of the super-frame header is "10" and the payload of the super-frame header is "78, 50, 50, 50, 50, 50, 50, 50".
5. A method of data transmission, comprising:
receiving a 64B/66B coding block which conforms to a Common Public Radio Interface (CPRI) protocol, wherein a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;
and checking the payload of the 64B/66B coding block by using the parity check information carried by the synchronization head.
6. The method of claim 5, wherein said checking the payload of the 64B/66B encoded block with parity information carried by the sync header comprises:
identifying a synchronization header of the 64B/66B encoded block, wherein a first bit in the synchronization header is a parity bit and a second bit in the synchronization header is an inverse of the first bit;
when the payload of the 64B/66B coding block conforms to the check bit, determining that the check is successful; determining that the check failed when the payload of the 64B/66B encoded block does not conform to the check bits.
7. The method of claim 6, wherein the 64B/66B coding blocks comprise super-frame headers or normal coding blocks,
the identifying the sync header of the 64B/66B coding block, wherein a first bit in the sync header is a parity bit, comprises:
identifying a synchronization header of the super frame header or a synchronization header of the common coding block, wherein a first bit in the synchronization header of the super frame header is an odd parity bit, and a first bit in the synchronization header of the common coding block is an even parity bit; or,
and identifying the synchronization head of the super frame header or the synchronization head of the common coding block, wherein the first bit in the synchronization head of the super frame header is an even check bit, and the first bit in the synchronization head of the common coding block is an odd check bit.
8. The method of claim 7, wherein the sync header of the super-frame header is "10" and the payload of the super-frame header is "78, 50, 50, 50, 50, 50, 50, 50".
9. A data transmission apparatus, comprising:
a generating unit, configured to generate a 64B/66B coding block compliant with a common public radio interface CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity information of a payload of the 64B/66B coding block;
and the transmitting unit is used for transmitting the 64B/66B coding block generated by the generating unit.
10. The apparatus as claimed in claim 9, wherein the generating unit is specifically configured to generate a payload of the 64B/66B encoded block, and to generate a first bit of the synchronization header as a check bit and a second bit of the synchronization header as an inverse of the first bit based on parity information of the payload.
11. The apparatus according to claim 9 or 10, wherein the 64B/66B coding blocks generated by the generating unit include super frame headers and normal coding blocks,
the generating unit is specifically configured to generate a first bit of a synchronization header of the super-frame header as an odd parity bit according to odd parity information of a payload of the super-frame header, generate a second bit of the synchronization header of the super-frame header as an inverse code of the first bit, generate a first bit of the synchronization header of the normal coding block as an even parity bit according to even parity information of the payload of the normal coding block, and generate a second bit of the synchronization header of the normal coding block as an inverse code of the first bit; or,
the generating unit is specifically configured to generate a first bit of a synchronization header of the super-frame header as an even parity bit, generate a second bit of the synchronization header of the super-frame header as an inverse of the first bit, generate the first bit of the synchronization header of the normal coding block as an odd parity bit, and generate the second bit of the synchronization header of the normal coding block as an inverse of the first bit, according to the odd parity information of the payload of the normal coding block.
12. A data transmission apparatus, comprising:
a receiving unit, configured to receive a 64B/66B coding block that conforms to a common public radio interface CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;
and the checking unit is used for checking the payload of the 64B/66B coding block by using the parity information carried by the synchronous head of the 64B/66B coding block received by the receiving unit.
13. The apparatus as claimed in claim 12, wherein said check unit is specifically configured to identify a synchronization header of said 64B/66B encoded block, wherein a first bit in said synchronization header is a check bit and a second bit in said synchronization header is an inverse of said first bit; when the payload of the 64B/66B coding block conforms to the check bit, determining that the check is successful; determining that the check failed when the payload of the 64B/66B encoded block does not conform to the check bits.
14. The apparatus according to claim 12 or 13, wherein the 64B/66B coding blocks received by the receiving unit include super frame headers or normal coding blocks,
the check unit is specifically configured to identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an odd check bit, and a first bit in the synchronization header of the normal coding block is an even check bit; or,
the check unit is specifically configured to identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an even check bit, and a first bit in the synchronization header of the normal coding block is an odd check bit.
15. A communication device, comprising:
the encoding unit is used for encoding data, generating a 64-bit payload and generating a 2-bit synchronization header, wherein the synchronization header carries parity check information of the payload;
the scrambling unit is used for scrambling the effective load generated by the coding unit to obtain the scrambled effective load;
a merging unit, configured to add the synchronization header generated by the encoding unit to the payload scrambled by the scrambling unit, so as to obtain a 66-bit encoded block;
the parallel-serial conversion unit is used for carrying out parallel-serial conversion processing on the coding blocks to generate serial coding blocks;
and the conveying unit is used for transmitting the serial coding blocks.
16. The communication device of claim 15, wherein the encoding unit is specifically configured to generate a first bit of the synchronization header as a check bit of the payload and to generate a second bit of the synchronization header as an inverse of the first bit.
17. The communication device according to claim 15 or 16, wherein the encoding unit is specifically configured to generate a 64-bit payload "78, 50, 50, 50, 50, 50, 50" and a 2-bit synchronization header "10" carrying odd parity information of the payload "78, 50, 50, 50, 50, 50, 50" as a superframe header; or,
the encoding unit is specifically configured to generate a payload of a normal encoding block and a synchronization header carrying even parity information of the payload of the normal encoding block, as the synchronization header of the normal encoding block.
18. A communication device, comprising:
a receiving unit, configured to receive a 66-bit serial coding block, where a synchronization header of the coding block carries parity information of a payload of the coding block;
a serial-to-parallel conversion unit, configured to perform serial-to-parallel conversion processing on the serial coding blocks;
a separation unit, configured to extract a 2-bit synchronization header and a 64-bit scrambled payload from the coding block subjected to the serial-to-parallel conversion by the serial-to-parallel conversion unit;
a descrambling unit, configured to perform descrambling processing on the scrambled payload extracted by the separation unit to obtain the payload;
and the checking unit is used for checking the effective load obtained by the descrambling unit by using the parity check information carried by the synchronous head extracted by the separation unit.
19. The communications device of claim 18, wherein the check unit is specifically configured to extract a first bit of the synchronization header as a check bit, and a second bit of the synchronization header is an inverse of the first bit; when the payload conforms to the check bit, determining that the check is successful; determining that the verification failed when the payload does not conform to the parity bit.
20. The communication device according to claim 18 or 19, wherein the check unit is specifically configured to identify as a superframe header a coded block of a 2-bit sync header "10" having a 64-bit payload "78, 50, 50, 50, 50, 50, 50" and odd check information carrying the payload "78, 50, 50, 50, 50, 50, 50"; or
The check unit is specifically configured to check the payload of the common coding block using even check information carried by a synchronization header of the common coding block.
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Effective date of registration: 20210421 Address after: Unit 3401, unit a, building 6, Shenye Zhongcheng, No. 8089, Hongli West Road, Donghai community, Xiangmihu street, Futian District, Shenzhen, Guangdong 518040 Patentee after: Honor Device Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |