CN103199953A - Method and device for data transmission and communication equipment - Google Patents

Abstract

Embodiments of the present invention provide a data transmission method and device. The method includes: generating a 64B/66B coded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B coded block carries the parity information of the payload of the 64B/66B coded block; and sending the 64B/66B coded block. The embodiment of the present invention uses the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

Description

Data transmission method and device, communication equipment

technical field

The embodiments of the present invention relate to the field of wireless communication, and more specifically, to a data transmission method and device, and a communication device.

Background technique

The simulation research shows that the bit error rate of the CPRI (Common Public Radio Interface, Common Public Radio Interface) link has a great influence on the wireless transmission channel. For example, when RB (ResourceBlock, resource block) is 1, the bit error rate of the CPRI link has little impact on the performance of wireless channel transmission, and has little impact on performance loss. When the number of RBs increases, the bit error rate of the CPRI link has a greater impact on system performance. When RB=50, the bit error rate of the CPRI link is 1.0e-5, and the performance loss is unacceptable. Considering the compression ratio and margin at the same time, it can be inferred that the bit error rate of the CPRI link is 1.0e-7. The performance impact is unacceptable.

Therefore, the bottom layer of the physical link needs a bit error rate detection mechanism, which can effectively identify the magnitude of the bit error rate of the CPRI link, and when the bit error rate of the link is found to be higher than a specific value (for example, 1.0e-7), the Report to the police.

In the prior art, the data information in the base frame is used to perform CRC (Cyclic Redundancy Check, Cyclic Redundancy Check) 16 check of each base frame. However, the basic protection unit of CRC is the base frame, which has a large granularity (for example, for the 10G rate CPRI protocol, the size of the base frame is 2560 bits), the detection accuracy is poor, and the link bit error rate cannot be accurately detected.

Contents of the invention

Embodiments of the present invention provide a data transmission method and device, and communication equipment, which can solve the problem of poor detection accuracy of a bit error rate.

On the one hand, a data transmission method is provided, comprising: generating a 64B/66B coded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B coded block carries the parity information of the payload of the 64B/66B coded block; sending 64B /66B encoded blocks.

On the other hand, a data transmission method is provided, comprising: receiving a 64B/66B encoded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B encoded block carries the parity information of the payload of the 64B/66B encoded block ; Check the payload of the 64B/66B encoded block by using the parity information carried by the sync header.

On the other hand, a data transmission device is provided, including: a generating unit, configured to generate a 64B/66B encoded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B encoded block carries the parity of the payload of the 64B/66B encoded block Check information; a sending unit, configured to send the 64B/66B coded block.

On the other hand, a data transmission device is provided, including: a receiving unit, configured to receive a 64B/66B encoded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B encoded block carries the parity of the payload of the 64B/66B encoded block check information; a check unit, configured to check the payload of the 64B/66B encoded block by using the parity check information carried by the synchronization header.

In another aspect, a communication device is provided, including: an encoding unit, configured to encode data, generate a 64-bit payload, and generate a 2-bit synchronization header, wherein the synchronization header carries the parity of the payload verification information; a scrambling unit, configured to scramble the payload generated by the coding unit to obtain a scrambled payload; a merging unit, configured to add the synchronization header generated by the coding unit to the scrambling The payload after the scrambling unit is scrambled to obtain a 66-bit coded block; the parallel-serial conversion unit is used to perform parallel-serial conversion processing on the coded block to generate a serial coded block; the transmission unit is used to send the coded block Serial encoding blocks.

In another aspect, a communication device is provided, including: a receiving unit, configured to receive a 66-bit serial encoding block, the synchronization header of the encoding block carries the parity information of the payload of the encoding block; the serial The parallel conversion unit is used to perform serial-to-parallel conversion processing on the serial coding block; the separation unit is used to extract a 2-bit synchronous header and 64 A scrambled payload of bits; a descrambling unit, configured to descramble the scrambled payload extracted by the separation unit to obtain the payload; a check unit, configured to use the separation unit The extracted parity information carried by the synchronization header is used to check the payload obtained by the descrambling unit.

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present invention.

Fig. 2 is a flowchart of a data transmission method according to another embodiment of the present invention.

Fig. 3 is a schematic diagram of an example of a system applying an embodiment of the present invention.

Fig. 4 is a block diagram of a data transmission device according to an embodiment of the present invention.

Fig. 5 is a block diagram of a data transmission device according to an embodiment of the present invention.

Fig. 6 is a block diagram of a communication device according to one embodiment of the present invention.

Fig. 7 is a block diagram of a communication system according to another embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The technical scheme of the present invention can be applied to various communication systems, such as: Global System for Mobile Communications (GSM, Global System of Mobile communication), Code Division Multiple Access (CDMA, Code Division Multiple Access) system, Wideband Code Division Multiple Access (WCDMA , Wideband Code Division Multiple Access Wireless), General Packet Radio Service (GPRS, General Packet Radio Service), Long Term Evolution (LTE, Long Term Evolution), etc.

User equipment (UE, User Equipment), also called mobile terminal (MobileTerminal), mobile user equipment, etc., can communicate with one or more core networks via a radio access network (for example, RAN, Radio AccessNetwork). The devices may be mobile terminals, such as mobile telephones (or "cellular" telephones) and computers with mobile terminals, such as portable, pocket, hand-held, built-in computer, or vehicle-mounted mobile devices, which communicate with wireless interfaces. Access the network to exchange language and/or data.

The base station can be a base station (BTS, Base Transceiver Station) in GSM or CDMA, a base station (NodeB) in WCDMA, or an evolved base station (eNB or e-NodeB, evolutional Node B) in LTE. The present invention is not limited, but for the convenience of description, the following embodiments take Node B as an example for illustration.

Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present invention. The method in FIG. 1 is executed by a data sending end (such as a base station, a base station controller or other entities).

101. Generate a 64B/66B encoded block conforming to the CPRI protocol, where a synchronization header of the 64B/66B encoded block carries parity information of a payload of the 64B/66B encoded block.

The 64B/66B encoding block conforming to the CPRI protocol has 66 bits, the first two bits are a synchronization header (SyncHead), and the latter 64 bits are a payload (Payload).

102. Send the 64B/66B encoded block.

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The verification protection unit of the traditional CRC is the base frame, and the granularity is relatively large (for example, for the CPRI protocol of 10G rate, the base frame size is 2560 bits); the verification protection unit of the embodiment of the present invention is a 64B/66B coded block, the size It is 66 bits, which is smaller than the protection granularity of CRC, and can improve the detection accuracy of bit error rate.

In addition, the embodiment of the present invention uses the redundancy of the synchronization header of the existing 64B/66B coding block as a parity check, and the implementation complexity is also low. Compared with the traditional CRC check that takes up extra data bandwidth, the check method in the embodiment of the present invention can save resources.

Optionally, as an embodiment, in step 101, the payload of the 64B/66B encoded block can be generated, and according to the parity information of the payload, the first bit of the synchronization header is generated as a check bit, and the synchronization header is generated The second bit of is used as the inverse code of the first bit. In other words, the synchronization header of the 64B/66B encoded block generated in step 101 can be guaranteed to be "10" or "01", which is compatible with the existing 64B/66B encoding protocol.

The 64B/66B coding block includes two types, namely a hyperframe header (Hyperframe) or a normal coding block. Optionally, as another embodiment, the parity check modes of the two types of 64B/66B coded blocks may be different. For example, in one example, according to the odd parity information of the payload of the superframe header, the first bit of the synchronization header of the superframe header can be generated as the odd parity bit, and the second bit of the synchronization header of the superframe header can be generated as the odd parity bit. The inverse code of the first bit; at this time, according to the even parity information of the payload of the common coding block, the first bit of the synchronous header of the common coding block can be generated as the even parity bit, and the first bit of the synchronous header of the common coding block can be generated Two bits are used as the inverse code of the first bit.

In another example, according to the even parity information of the payload of the superframe header, the first bit of the synchronization header of the superframe header can be generated as the even parity bit, and the second bit of the synchronization header of the superframe header can be generated as the second bit. The inverse code of one bit, and according to the odd parity information of the payload of the ordinary encoding block, the first bit of the synchronization header of the ordinary encoding block can be generated as the odd parity bit, and the second bit of the synchronization header of the ordinary encoding block can be generated as the odd parity bit. Inverse of the first bit. In this way, the coded block synchronization header information carries the parity check information of the coded block to protect the coded information, and at the same time, no illegal synchronization header information is generated, so that the two functions are compatible.

Optionally, as another embodiment, the synchronization header of the superframe header can be "10", and the payload of the superframe header is "78, 50, 50, 50, 50, 50, 50, 50", which can further It is compatible with the identification mechanism of the superframe header stipulated in the existing 64B/66B encoding protocol. The receiving end can identify the "10" sync header signal transmitted by encoding, and identify whether the payload information of the superframe header in it conforms to the expected control word information "78, 50, 50, 50, 50, 50, 50, 50". In this specific example, since the binary bits of 78 are 01001110 (4 "1") and the binary bits of 50 are 00110010 (3 "1"), the payload of the superframe header includes 4+3*7=25 a "1". Therefore, the sync header "10" is odd parity information, that is, the first bit ("1" in this case) in the sync header is an odd parity bit. The sync header of an ordinary coding block may be "10" or "01", both of which are even parity information, that is, the first bit in the sync header is an even parity bit.

Certainly, the embodiment of the present invention does not limit the specific format of the superframe header. If the payload of the superframe header is other values and satisfies even parity, it can be determined that the synchronization header "10" is even parity information.

The embodiment of the present invention can also be compatible with other mechanisms of the existing 64B/66B encoding protocol, such as a scrambling mechanism, a GearBox (transmission) mechanism, and the like. For example, the parity check may be performed on the unscrambled payload of the common coded block, and it is determined that the synchronization header of the common coded block is "10" or "01". Then the payload is processed by self-synchronization scrambling, synchronization header addition, Gearbox, and parallel-to-serial conversion, and a 66-bit coded block is output. In this way, only a small improvement to the 64B/66B encoding block is required to achieve high-precision verification, and it is compatible with the existing 64B/66B encoding and decoding process.

In addition, the embodiment of the present invention can detect more types of bit errors, and since the unit of verification protection is a 66-bit coding block, single bit errors and burst errors exceeding 66 bits can be distinguished.

Fig. 2 is a flowchart of a data transmission method according to another embodiment of the present invention. The method in FIG. 2 is executed by the receiving end (such as a base station, a base station controller or other entities).

201. Receive a 64B/66B encoded block conforming to the CPRI protocol, where a synchronization header of the 64B/66B encoded block carries parity information of a payload of the 64B/66B encoded block.

202. Check the payload of the 64B/66B encoded block by using the parity check information carried in the synchronization header.

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The method of FIG. 2 corresponds to the method of FIG. 1 , and thus detailed description will be appropriately omitted.

Optionally, as an embodiment, in step 202, the synchronization header of the 64B/66B encoded block can be identified, wherein the first bit in the synchronization header is a parity bit, and the second bit in the synchronization header is the first bit inverse code. When the payload of the 64B/66B encoded block conforms to the check digit, it is determined that the verification is successful; when the payload of the 64B/66B encoded block does not conform to the check digit, it is determined that the verification fails. In this way, the synchronization header of the 64B/66B encoding block can be guaranteed to be "10" or "01", which is compatible with the existing 64B/66B encoding protocol. The so-called payload conforming to the parity bit means that the number of bits "1" contained in the payload is consistent with the indication of the parity bit, which is the same as the definition of parity in the prior art. For example, if the parity bit is an odd parity bit, when the parity bit is "1" and the number of bits "1" contained in the payload is odd, or when the parity bit is "0" and the payload contains When the number of "1" bits contained is even, the payload conforms to the parity bit; conversely, when the parity bit is "0" and the number of "1" bits contained in the payload is odd, or when the parity bit When it is "1" and the number of bits "1" contained in the payload is even, the payload does not match the check digit.

On the other hand, if the parity bit is an even parity bit, when the parity bit is "1" and the number of bits "1" contained in the payload is even, or when the parity bit is "0" and valid When the number of bits "1" contained in the payload is odd, the payload conforms to the parity bit; conversely, when the parity bit is "0" and the number of bits "1" contained in the payload is even, or when the parity bit is When the parity bit is "1" and the number of bits "1" contained in the payload is an odd number, the payload does not match the parity bit.

Optionally, as another embodiment, the 64B/66B coding block includes a superframe header or a common coding block. In step 202, the synchronous header of the superframe header or the synchronous header of the ordinary coded block can be identified, wherein the first bit in the synchronous header of the superframe header is an odd parity bit, and the first bit in the synchronous header of the ordinary encoded block is an even parity bit; or, it can identify the synchronous header of the superframe header or the synchronous header of the ordinary coded block, wherein the first bit in the synchronous header of the superframe header is an even parity bit, and the first bit in the synchronous header of the ordinary coded block is The first bit is the odd parity bit. . In this way, the coded block synchronization header information carries the parity check information of the coded block to protect the coded information, and at the same time, no illegal synchronization header information is generated, so that the two functions are compatible.

Optionally, as another embodiment, the synchronization header of the superframe header may be "10", and the payload of the superframe header may be "78, 50, 50, 50, 50, 50, 50, 50". In this way, it can be further compatible with the identification mechanism of the superframe header stipulated in the existing 64B/66B encoding protocol.

The embodiment of the present invention can also be compatible with other mechanisms of the existing 64B/66B encoding protocol, such as a descrambling mechanism, a GearBox mechanism, and the like. For example, serial-to-parallel conversion, synchronization header separation, Gearbox and self-synchronization descrambling can be performed on the received 66-bit encoded block to obtain a 2-bit synchronization header and a 64-bit payload, and then use the parity carried by the synchronization header The verification information verifies the payload. In this way, only a small improvement to the 64B/66B encoding block is required to achieve high-precision verification, and it is compatible with the existing 64B/66B encoding and decoding process.

In addition, the embodiment of the present invention can detect more types of bit errors, and since the unit of verification protection is a 66-bit coding block, single bit errors and burst errors exceeding 66 bits can be distinguished.

Fig. 3 is a schematic diagram of an example of a system applying an embodiment of the present invention. The system 30 in FIG. 3 includes RE (Radio Equipment, radio frequency equipment) 31 and REC (Radio Equipment Control, radio frequency equipment controller) 32. The RE 31 and the REC 32 are connected by wired means (such as optical fiber or cable). The logical link between RE 31 and REC 32 can support the CPRI protocol.

RE 31 and REC 32 can be used as the execution subject of the method in Fig. 1 or Fig. 2, and encode to obtain a 64B/66B coded block or decode a 64B/66B coded block.

In one example, RE 31 is a base station and REC 32 is a base station controller. The base station and the base station controller can communicate through a CPRI link, and this embodiment of the present invention can be applied.

In another example, RE 31 is a remote radio unit (RRU, RadioRemote Unit) in the distributed base station, and REC 32 is a baseband processing unit (BBU, Base BandUnit) in the distributed base station. The RRU and the BBU can communicate through the CPRI link, and this embodiment of the present invention can be applied.

The embodiment of the present invention is not limited to the scenario examples listed above, and other entities that use the CPRI link for communication may also apply the embodiment of the present invention. These applications all fall within the scope of the embodiments of the present invention.

Fig. 4 is a block diagram of a data transmission device according to an embodiment of the present invention. The data transmission device 40 in FIG. 4 is a data sending end, such as RE 31 or REC 32 shown in FIG. 3 , including a generating unit 41 and a sending unit 42.

The generating unit 41 generates a 64B/66B coded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B coded block carries the parity information of the payload of the 64B/66B coded block. The transmitting unit 42 transmits the 64B/66B encoded block generated by the generating unit 41 .

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The data transmission device 40 in FIG. 4 can execute the method in FIG. 1 , so to avoid repetition, no detailed description is given here. The generating unit 41 may be implemented by a processor, and the sending unit 42 may be implemented by an interface or a transceiver.

Optionally, as an embodiment, the generation unit 41 may generate the payload of the 64B/66B encoded block, and generate the first bit of the synchronization header as a check bit according to the parity information of the payload, and generate the first bit of the synchronization header as the check bit, and generate the first bit of the synchronization header. Two bits are used as the inverse code of the first bit.

Optionally, as another embodiment, the 64B/66B coded blocks generated by the generating unit 41 include superframe headers and common coded blocks. Specifically, the generation unit 41 can generate the first bit of the synchronization header of the superframe header as the odd parity bit according to the odd parity information of the payload of the superframe header, and generate the second bit of the synchronization header of the superframe header as the second bit of the synchronization header of the superframe header. One-bit inverse code, and according to the even parity information of the payload of the common coding block, the first bit of the synchronization header of the normal coding block is generated as the even parity bit, and the second bit of the synchronization header of the normal coding block is generated as the The inverse of the first bit described above. Or, generating unit 31 can generate the first bit of the synchronization header of the superframe header as the even parity bit according to the even parity information of the payload of the superframe header, and generate the second bit of the synchronization header of the superframe header as the first bit. The inverse code of the bit, and according to the odd parity information of the payload of the ordinary encoding block, the first bit of the synchronization header of the ordinary encoding block is generated as the odd parity bit, and the second bit of the synchronization header of the ordinary encoding block is generated as the first bit One's complement of bits.

Optionally, as another embodiment, the synchronization header of the superframe header generated by the generating unit 41 may be "10", and the payload of the superframe header may be "78, 50, 50, 50, 50, 50, 50, 50".

In this way, the 64B/66B encoding block in the embodiment of the present invention can be compatible with existing encoding protocols, and at the same time realize high-precision verification.

Fig. 5 is a block diagram of a data transmission device according to an embodiment of the present invention. The data transmission device 50 of FIG. 5 is a data receiving end, such as RE 31 or REC 32 shown in FIG. 3 , including a receiving unit 51 and a checking unit 52.

The receiving unit 51 receives the 64B/66B coded block conforming to the CPRI protocol, wherein the synchronization header of the 64B/66B coded block carries the parity information of the payload of the 64B/66B coded block. The checking unit 52 checks the payload of the 64B/66B encoded block by using the parity information carried in the synchronization header of the 64B/66B encoded block received by the receiving unit 51 .

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The data transmission device 50 in FIG. 5 can execute the method in FIG. 2 , so to avoid repetition, no detailed description is given here. The receiving unit 51 may be implemented by an interface or a transceiver, and the checking unit 52 may be implemented by a processor.

Optionally, as another embodiment, the verification unit 52 can identify the synchronization header of the 64B/66B encoded block, wherein the first bit in the synchronization header is a check bit, and the second bit in the synchronization header is the first bit. Inverse code; when the payload of the 64B/66B encoding block matches the check digit, it is determined that the verification is successful; when the payload of the 64B/66B encoding block does not meet the check digit, it is determined that the verification fails.

Optionally, as another embodiment, the 64B/66B coded blocks received by the receiving unit 51 include superframe headers or common coded blocks. In this case, the check unit 52 can identify the sync header of the superframe header or the sync header of the common coding block, wherein the first bit in the sync header of the superframe header is an odd parity bit, and the sync header of the common coding block The first bit of is an even parity bit; or, the checking unit 52 can identify the synchronous header of the superframe header or the synchronous header of the common coding block, wherein the first bit in the synchronous header of the superframe header is an even parity bit, The first bit in the sync header of an ordinary coded block is an odd parity bit.

Optionally, as another embodiment, the verification unit 52 can identify that the synchronization header of the superframe header is "10", and the payload of the superframe header is "78, 50, 50, 50, 50, 50, 50, 50 ".

In this way, the 64B/66B encoding block in the embodiment of the present invention can be compatible with existing encoding protocols, and at the same time realize high-precision verification.

No matter under the condition of low bit error rate or high bit error rate, the improved 64B/66B coding of the embodiment of the present invention can well detect the bit error rate of the physical link (the detected bit error rate is approximately equal to the actual link error rate). code rate). And the lower the bit error rate, the higher the accuracy of the bit error rate indicated by the improved 64B/66B encoding. Utilize the parity check capability of the improved 64B/66B code, report the link physical layer error information required by the user, and support the user-defined code rate alarm mechanism. Improved encoding supports the identification of various types of errors, including random errors or bursts of short bursts.

Test according to the method of the embodiment of the present invention. In the time interval of 1s, the number of 1.536e8 64B/66B encoding errors is counted, and the bit error rate of the link is calculated. The test results have a high degree of confidence.

Fig. 6 is a block diagram of a communication device according to one embodiment of the present invention. The communication device 60 of Fig. 6 can be RE 31 or REC 32 shown in Fig. 3, as the coding end and the sending end of data. The communication device 60 includes an encoding unit 61 , a scrambling unit 62 , a combining unit 63 , a parallel-to-serial conversion unit 64 and a transmission unit 65 .

The encoding unit 61 encodes the data, generates a 64-bit payload, and generates a 2-bit synchronization header, wherein the synchronization header carries parity information of the payload. In this way, the encoding unit 61 can generate a synchronization header and a payload of a 64B/66B encoded block conforming to the CPRI protocol.

The scrambling unit 62 scrambles the payload generated by the encoding unit 61 to obtain a scrambled payload. For the scrambling mechanism of the scrambling unit 62, reference may be made to the prior art, so details are not repeated here. For example, as a non-limiting embodiment, the scrambling unit 62 may generate a binary pseudo-random sequence, and perform a modulo 2 addition operation on the pseudo-random sequence and the 64-bit payload to implement scrambling of the payload.

The merging unit 63 adds the synchronization header generated by the encoding unit 61 to the payload scrambled by the scrambling unit 62 to obtain a 66-bit encoding block. Optionally, the merging unit 63 may also perform other additional operations in the prior art, such as GearBox processing.

The parallel-to-serial conversion unit 64 performs parallel-to-serial conversion processing on the encoded blocks to generate serial encoded blocks. The transport unit 65 transmits the serial encoded blocks.

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The communication device 60 in FIG. 6 can execute the method in FIG. 1 , so it will not be described in detail to avoid repetition. Optionally, as an embodiment, the encoding unit 61 may generate the first bit of the synchronization header as a check bit of the payload, and generate the second bit of the synchronization header as an inverse code of the first bit. In other words, the synchronization header generated by the encoding unit 61 can be guaranteed to be "10" or "01", which is compatible with the existing 64B/66B encoding protocol.

Existing 64B/66B coded blocks include two types, ie superframe headers or common coded blocks. Optionally, as another embodiment, the encoding unit 61 may generate a 64-bit payload "78, 50, 50, 50, 50, 50, 50, 50" and carry a payload "78, 50, 50, 50, 50, 50, 50, 50" and the 2-bit sync header "10" of the odd parity information is used as the superframe header. This enables compatibility with existing sync header formats. For a normal coded block, on the other hand, the coding unit 61 may generate a payload of the normal coded block and a synchronization header carrying even parity information of the payload of the normal coded block as the synchronization header of the normal coded block. In other words, the sync header of an ordinary coding block may be "10" or "01", both of which are even parity information, that is, the first bit in the sync header is an even parity bit. In this way, the coded block synchronization header information carries the parity check information of the coded block to protect the coded information, and at the same time, no illegal synchronization header information is generated, so that the two functions are compatible.

The operations of the scrambling unit 62, the merging unit 63, the parallel-to-serial conversion unit 64 and the delivery unit 65 can be similar to the corresponding operations of the existing 64B/66B functional modules, so that the changes to the existing communication equipment are small, and the high-precision While verifying, it is compatible with the existing 64B/66B codec process.

Fig. 7 is a block diagram of a communication system according to another embodiment of the present invention. The communication device 70 of Fig. 7 can be RE 31 or REC 32 shown in Fig. 3, as the receiving end and the decoding end of data. The communication device 70 includes a receiving unit 71 , a serial-to-parallel converting unit 72 , a separating unit 73 , a descrambling unit 74 and a checking unit 75 .

The receiving unit 71 receives 66-bit serial coded blocks. The sync header of the encoded block carries parity information for the payload of the encoded block. For example, the encoded block may be a 64B/66B encoded block output from the communication device 60 in FIG. 6 conforming to the CPRI protocol, but the present invention does not limit the source of the encoded block.

The serial-to-parallel conversion unit 72 performs serial-to-parallel conversion processing on serial encoded blocks. The separation unit 73 extracts a 2-bit sync header and a 64-bit scrambled payload from the coded block after the serial-to-parallel conversion process by the serial-to-parallel conversion unit 72 . Optionally, if GearBox processing is required, the separating unit 73 may have the capability of GearBox processing.

The descrambling unit 74 descrambles the scrambled payload extracted by the separating unit 73 to obtain the payload. The descrambling mechanism of the descrambling unit 74 can refer to the prior art, so it will not be described again. For example, the descrambling mechanism of the descrambling unit 74 may correspond to the scrambling mechanism of the scrambling unit 62 in FIG. 6 .

The checking unit 75 checks the payload obtained by the descrambling unit 74 by using the parity information carried in the sync header extracted by the separating unit 73 .

The embodiment of the present invention utilizes the synchronization header of the 64B/66B code block to carry the parity check information to check the 64-bit payload of the 64B/66B code block, the granularity of the check protection is small, and the bit error rate detection accuracy is improved.

The communication device 70 in FIG. 7 can execute the method in FIG. 2 , so to avoid repetition, no detailed description is given. Optionally, as an embodiment, the checking unit 74 may extract the first bit of the synchronization header as the check bit, and the second bit in the synchronization header is an inverse code of the first bit. In other words, the sync header can be guaranteed to be "10" or "01", which is compatible with the existing 64B/66B encoding protocol.

When the payload matches the check digit, the check unit 74 determines that the check is successful; when the payload does not match the check digit, the check unit 74 determines that the check fails.

The 64B/66B coded blocks may include superframe headers or ordinary coded blocks. Optionally, as another embodiment, the verification unit 74 can combine the 64-bit payload "78, 50, 50, 50, 50, 50, 50, 50" and the payload "78, 50, 50, 50, 50, 50, 50, 50" of the odd-parity information and the 2-bit sync header "10" coded blocks are identified as superframe headers. On the other hand, for a normal coded block, the verification unit 74 may use the even parity information carried in the sync header of the normal coded block to verify the payload of the normal coded block. In other words, the sync header of an ordinary coding block may be "10" or "01", both of which are even parity information, that is, the first bit in the sync header is an even parity bit. In this way, the coded block synchronization header information carries the parity check information of the coded block to protect the coded information, and at the same time, no illegal synchronization header information is generated, so that the two functions are compatible.

The receiving unit 71, the serial-to-parallel conversion unit 72, the separation unit 73 and the descrambling unit 74 can be similar to the corresponding operations of the existing 64B/66B functional modules, so that the changes to the existing communication equipment are small, and the high-precision verification can be realized. At the same time, it is compatible with the existing 64B/66B codec process.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (20)

1. A method of data transmission, comprising:

generating a 64B/66B coding block which conforms to a Common Public Radio Interface (CPRI) protocol, wherein a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;

and sending the 64B/66B coding block.

2. The method of claim 1, wherein generating a 64B/66B coded block compliant with a common public radio interface, CPRI, protocol comprises:

generating a payload of the 64B/66B encoded block;

and generating a first bit of the synchronous head as a check bit and a second bit of the synchronous head as an inverse code of the first bit according to the parity check information of the payload.

3. The method of claim 2, wherein the 64B/66B coding blocks comprise super-frame headers or normal coding blocks,

the generating a first bit of the synchronization header as a check bit and a second bit of the synchronization header as an inverse of the first bit according to the parity information of the payload includes:

generating a first bit of a synchronization head of the super frame header as an odd check bit and a second bit of the synchronization head of the super frame header as an inverse code of the first bit according to odd check information of a payload of the super frame header, and generating a first bit of the synchronization head of the common coding block as an even check bit and a second bit of the synchronization head of the common coding block as an inverse code of the first bit according to even check information of the payload of the common coding block; or,

generating a first bit of a synchronization head of the super frame header as an even check bit and a second bit of the synchronization head of the super frame header as an inverse code of the first bit according to even check information of a payload of the super frame header, and generating the first bit of the synchronization head of the common coding block as an odd check bit and the second bit of the synchronization head of the common coding block as an inverse code of the first bit according to odd check information of the payload of the common coding block.

4. The method of claim 3, wherein the sync header of the super-frame header is "10" and the payload of the super-frame header is "78, 50, 50, 50, 50, 50, 50, 50".

5. A method of data transmission, comprising:

receiving a 64B/66B coding block which conforms to a Common Public Radio Interface (CPRI) protocol, wherein a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;

and checking the payload of the 64B/66B coding block by using the parity check information carried by the synchronization head.

6. The method of claim 5, wherein said checking the payload of the 64B/66B encoded block with parity information carried by the sync header comprises:

identifying a synchronization header of the 64B/66B encoded block, wherein a first bit in the synchronization header is a parity bit and a second bit in the synchronization header is an inverse of the first bit;

when the payload of the 64B/66B coding block conforms to the check bit, determining that the check is successful; determining that the check failed when the payload of the 64B/66B encoded block does not conform to the check bits.

7. The method of claim 6, wherein the 64B/66B coding blocks comprise super-frame headers or normal coding blocks,

the identifying the sync header of the 64B/66B coding block, wherein a first bit in the sync header is a parity bit, comprises:

identifying a synchronization header of the super frame header or a synchronization header of the common coding block, wherein a first bit in the synchronization header of the super frame header is an odd parity bit, and a first bit in the synchronization header of the common coding block is an even parity bit; or,

and identifying the synchronization head of the super frame header or the synchronization head of the common coding block, wherein the first bit in the synchronization head of the super frame header is an even check bit, and the first bit in the synchronization head of the common coding block is an odd check bit.

8. The method of claim 7, wherein the sync header of the super-frame header is "10" and the payload of the super-frame header is "78, 50, 50, 50, 50, 50, 50, 50".

9. A data transmission apparatus, comprising:

a generating unit, configured to generate a 64B/66B coding block compliant with a common public radio interface CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity information of a payload of the 64B/66B coding block;

and the transmitting unit is used for transmitting the 64B/66B coding block generated by the generating unit.

10. The apparatus as claimed in claim 9, wherein the generating unit is specifically configured to generate a payload of the 64B/66B encoded block, and to generate a first bit of the synchronization header as a check bit and a second bit of the synchronization header as an inverse of the first bit based on parity information of the payload.

11. The apparatus according to claim 9 or 10, wherein the 64B/66B coding blocks generated by the generating unit include super frame headers and normal coding blocks,

the generating unit is specifically configured to generate a first bit of a synchronization header of the super-frame header as an odd parity bit according to odd parity information of a payload of the super-frame header, generate a second bit of the synchronization header of the super-frame header as an inverse code of the first bit, generate a first bit of the synchronization header of the normal coding block as an even parity bit according to even parity information of the payload of the normal coding block, and generate a second bit of the synchronization header of the normal coding block as an inverse code of the first bit; or,

the generating unit is specifically configured to generate a first bit of a synchronization header of the super-frame header as an even parity bit, generate a second bit of the synchronization header of the super-frame header as an inverse of the first bit, generate the first bit of the synchronization header of the normal coding block as an odd parity bit, and generate the second bit of the synchronization header of the normal coding block as an inverse of the first bit, according to the odd parity information of the payload of the normal coding block.

12. A data transmission apparatus, comprising:

a receiving unit, configured to receive a 64B/66B coding block that conforms to a common public radio interface CPRI protocol, where a synchronization header of the 64B/66B coding block carries parity check information of a payload of the 64B/66B coding block;

and the checking unit is used for checking the payload of the 64B/66B coding block by using the parity information carried by the synchronous head of the 64B/66B coding block received by the receiving unit.

13. The apparatus as claimed in claim 12, wherein said check unit is specifically configured to identify a synchronization header of said 64B/66B encoded block, wherein a first bit in said synchronization header is a check bit and a second bit in said synchronization header is an inverse of said first bit; when the payload of the 64B/66B coding block conforms to the check bit, determining that the check is successful; determining that the check failed when the payload of the 64B/66B encoded block does not conform to the check bits.

14. The apparatus according to claim 12 or 13, wherein the 64B/66B coding blocks received by the receiving unit include super frame headers or normal coding blocks,

the check unit is specifically configured to identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an odd check bit, and a first bit in the synchronization header of the normal coding block is an even check bit; or,

the check unit is specifically configured to identify a synchronization header of the super-frame header or a synchronization header of the normal coding block, where a first bit in the synchronization header of the super-frame header is an even check bit, and a first bit in the synchronization header of the normal coding block is an odd check bit.

15. A communication device, comprising:

the encoding unit is used for encoding data, generating a 64-bit payload and generating a 2-bit synchronization header, wherein the synchronization header carries parity check information of the payload;

the scrambling unit is used for scrambling the effective load generated by the coding unit to obtain the scrambled effective load;

a merging unit, configured to add the synchronization header generated by the encoding unit to the payload scrambled by the scrambling unit, so as to obtain a 66-bit encoded block;

the parallel-serial conversion unit is used for carrying out parallel-serial conversion processing on the coding blocks to generate serial coding blocks;

and the conveying unit is used for transmitting the serial coding blocks.

16. The communication device of claim 15, wherein the encoding unit is specifically configured to generate a first bit of the synchronization header as a check bit of the payload and to generate a second bit of the synchronization header as an inverse of the first bit.

17. The communication device according to claim 15 or 16, wherein the encoding unit is specifically configured to generate a 64-bit payload "78, 50, 50, 50, 50, 50, 50" and a 2-bit synchronization header "10" carrying odd parity information of the payload "78, 50, 50, 50, 50, 50, 50" as a superframe header; or,

the encoding unit is specifically configured to generate a payload of a normal encoding block and a synchronization header carrying even parity information of the payload of the normal encoding block, as the synchronization header of the normal encoding block.

18. A communication device, comprising:

a receiving unit, configured to receive a 66-bit serial coding block, where a synchronization header of the coding block carries parity information of a payload of the coding block;

a serial-to-parallel conversion unit, configured to perform serial-to-parallel conversion processing on the serial coding blocks;

a separation unit, configured to extract a 2-bit synchronization header and a 64-bit scrambled payload from the coding block subjected to the serial-to-parallel conversion by the serial-to-parallel conversion unit;

a descrambling unit, configured to perform descrambling processing on the scrambled payload extracted by the separation unit to obtain the payload;

and the checking unit is used for checking the effective load obtained by the descrambling unit by using the parity check information carried by the synchronous head extracted by the separation unit.

19. The communications device of claim 18, wherein the check unit is specifically configured to extract a first bit of the synchronization header as a check bit, and a second bit of the synchronization header is an inverse of the first bit; when the payload conforms to the check bit, determining that the check is successful; determining that the verification failed when the payload does not conform to the parity bit.

20. The communication device according to claim 18 or 19, wherein the check unit is specifically configured to identify as a superframe header a coded block of a 2-bit sync header "10" having a 64-bit payload "78, 50, 50, 50, 50, 50, 50" and odd check information carrying the payload "78, 50, 50, 50, 50, 50, 50"; or

The check unit is specifically configured to check the payload of the common coding block using even check information carried by a synchronization header of the common coding block.

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