CN103187965B - 具有数字地的栅极驱动器 - Google Patents

具有数字地的栅极驱动器 Download PDF

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Publication number
CN103187965B
CN103187965B CN201210478559.6A CN201210478559A CN103187965B CN 103187965 B CN103187965 B CN 103187965B CN 201210478559 A CN201210478559 A CN 201210478559A CN 103187965 B CN103187965 B CN 103187965B
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China
Prior art keywords
gate drivers
input buffer
ground
connectors
coupled
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Expired - Fee Related
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CN201210478559.6A
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CN103187965A (zh
Inventor
鲁克·范戴克
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
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Abstract

各种示范性实施例涉及对寄生电感进行补偿的栅极驱动器电路。将所述栅极驱动器中的输入缓冲器接地到暴露的管芯焊盘。接地可以包括向下结合或者导电胶。

Description

具有数字地的栅极驱动器
技术领域
这里公开的各种示范性实施例通常涉及对寄生电感进行补偿的栅极驱动器电路。
背景技术
栅极驱动器电路可以用于驱动功率金属氧化物半导体场效应晶体管(MOSFET)或则会绝缘栅双极晶体管(IGBT)。
栅极驱动器可以用于两沟道器件，也称作双沟道器件。这些器件可以驱动具有低侧和高侧的功率器件。称作S0-8的普通集成电路(IC)封装可以使用具有8个连接器的芯片。这些连接器也可以称作管脚。
传统的栅极驱动器可以具有伴随着印刷电路板(PCB)上寄生电感的问题。这些寄生电感可以引起参考电压的不需要的电压偏移，大于或者小于接地电平。
另一个问题可能包括针对栅极驱动器的输入一侧的参考电压的不稳定性。因为这种参考是嘈杂的，输入电平可以表征为被不需要的触发而加以表征。
图1说明了针对栅极驱动器电路的传播延迟定义。传播延迟tpd是针对栅极驱动器电路的重要特征。如图1所示，传播延迟的一般定义包括当输入信号上升到50％电平以上时的初始时间和当输出信号上升到10％电平以上时的后续时间之间的时间差，即tpd(L-LG)on至tpd(H-HG)on。第二传播延迟定义包括输入信号下降到50％电平以下时的初始时间和当输出信号下降到90％电平以下时的后续时间之间的时间差，即tpd(L-LG)off至tpd(H-HG)off。
图2说明了使用输入滤波器208/209示范性现有技术栅极驱动器200的实施例。栅极驱动器200包括高输入缓冲器202、低输入缓冲器203、高欠压监测器204、低欠压监测器205、高输出驱动器206和低输出驱动器207。高输入滤波器208和低输入滤波器209分别耦合至高输入缓冲器202和低输入缓冲器203的输入侧。
微控制器240包括与高输入滤波器208耦合的高输入线220和与低输入滤波器209耦合的低输入线230。现有技术的实施例假设不需要的电压偏移只发生有限的时间段。因此，现有技术器件可以在输入缓冲器202/203之前添加相应的输入缓冲器208/209，以防止不需要的电压偏移的传播。然而，因为其向H路径和L路径两者都添加了延迟，这种方案具有明显的缺点。因此，需要一种改进的栅极驱动器电路。
发明内容
提出了各种示范性实施例的简要概括。在以下概括中可以进行一些简化和省略，其目的是为了突出和介绍各种示范实施例的一些方面，而不是限制本发明的范围。随后的部分中将是优选示范实施例的详细描述，适用于允许本领域普通技术人员实现和使用本发明的概念。
各种示范实施例涉及一种用于电源的系统，所述系统包括：栅极驱动器，所述栅极驱动器包括至少一个输入缓冲器、至少一个欠压监测器、至少一个输出驱动器以及暴露的管芯焊盘，其中所述至少一个输入缓冲器的地耦合至所述暴露的管芯焊盘；微控制器，耦合至所述栅极驱动器；第一地，耦合至所述暴露的管芯焊盘和所述微控制器；，其中所述地对所述至少一个输入缓冲器的寄生电感进行补偿；以及第二地，耦合至所述栅极驱动器的连接器。
在一些实施例中，硅和所述暴露的管芯焊盘之间的向下结合可以提供所述第一地。在其他实施例中，硅和所述暴露的管芯焊盘之间的导电胶可以提供所述第一地。
各种示范性实施例还涉及至少一个输入缓冲器，所述至少一个输入缓冲器可以包括高输入缓冲器和低输入缓冲器两者。所述高输入缓冲器和所述低输入缓冲器两者的地可以耦合至所述第一地。
在各种示范性实施例中，所述系统可以只具有8个连接器。所述8个连接器可以是H、L、HC、HG、HS、LC、LG和LS连接器。所述微控制器可以耦合至所述H连接器和所述L连接器两者。
各种示范性实施例还涉及至少一个输出缓冲器，所述至少一个输出缓冲器包括分别耦合至HG和LG连接器的高输出缓冲器和低输出缓冲器。第一晶体管可以耦合至所述HG连接器，而第二晶体管可以耦合至所述LG连接器。
在一些实施例中，所述第一地可以是数字地，而所述第二地可以是模拟地。
各种示范性实施例涉及一种栅极驱动器，所述栅极驱动器包括：至少一个输入缓冲器；至少一个欠压监测器；暴露的管芯焊盘，所述暴露的管芯焊盘提供数字地；至少一个输出驱动器，其中所述至少一个输入缓冲器的地耦合至所述暴露的管芯焊盘；以及输出连接器，所述输出连接器提供模拟地。
在一些实施例中，所述栅极驱动器的硅和所述暴露的管芯焊盘之间的向下结合可以提供所述数字地。在其他实施例中，所述栅极驱动器的硅和所述暴露的管芯焊盘之间的导电胶可以提供所述数字地。
在各种示范性实施例中，所述至少一个输入缓冲器还可以包括高输入缓冲器和低输入缓冲器。所述高输入缓冲器和所述低输入缓冲器两者的地可以耦合至所述数字地。
在各种示范性实施例中，所述至少一个输出缓冲器还可以包括高输出缓冲器和低输出缓冲器。所述高输出缓冲器和所述低输出缓冲器可以分别耦合至HG和LG连接器。
在各种示范性实施例中，所述栅极驱动器可以在只具有8个连接器的集成电路(IC)上实现。所述8个连接器可以是H、L、HC、HG、HS、LC、LG和LS连接器。
附图说明
为了更好地理解各种示范性实施例，对附图进行参考，其中：
图1说明了传播延迟定义；
图2说明了使用输入滤波器的现有技术栅极驱动器；
图3说明了栅极驱动器的实施例；
图4说明了针对图3的栅极驱动器的管芯图；
图5说明了管芯焊盘连接的第一实施例；以及
图6说明了管芯焊盘连接的第二实施例。
具体实施方式
现在参考附图，其中相似的数字表示相似的部件或步骤，公开了各种示范性实施例的宽广的方面。
本领域普通技术人员应该理解的是这里的任意方框图表示实现本发明实施例原理的说明性电路的概念图。
图3说明了栅极驱动器300的实施例。所述栅极驱动器300可以包括高输入缓冲器302、低输入缓冲器303、高欠压监测器304低欠压监测器305、高输出驱动器306和低输出缓冲器307。高输入缓冲器302和低输入缓冲器303两者可以耦合至地310。如下面更加详细所述的地310)，可以是暴露的管芯焊盘DP。栅极驱动器也可以具有8个外部连接器。所述8个连接器可以是H、L、HC、HG、HS、LC、LG和LS连接器。
微控制器340可以具有耦合至高输入缓冲器302的高输入线320以及耦合至高输入缓冲器303的低输入线330。微控制器340可以是数字信号处理器(DSP)。微控制器340的电压参考可以与地310相同。微控制器340可以耦合至H连接器和L连接器两者。晶体管360和晶体管370可以分别通过其栅极耦合至HG连接器和LG连接器。
如图3所示，地310可以不包含附加的连接器或者管脚。代替地，暴露的管芯焊盘DP可以用作第九连接。
在示范性实施例中，输入缓冲器302/303的电压参考和微控制器340的电压参考之间的连接可以通过输入缓冲器电压参考和暴露的管芯焊盘DP之间的结合引线来实现。因此，地310可以用作两个电压参考。地310也可以看作是数字地。
也可以暴露的管芯焊盘和微控制器340的电压参考之间的印刷电路板(PCB)上存在连接。
栅极驱动器300的LS连接器可以与地350相连，所述地350与地310分离。地350可以看作是模拟地或者功率地。地310与地350的分离可以提供各种益处。
尽管与传统的8一连接器封装相比所述器件可以具有附加的连接，实际的连接器数量可以不增加。
第一优势包括对于LS连接器上的噪声瞬变的高免疫性。LS连接器的电压参考可以从输入缓冲器302/303的电压参考去耦合。第二优势可以包括避免了传播延迟。第三优势可以包含与公共连接器以及封装要求的兼容。尽管存在第九连接，总的连接器数量保持是8.同样，在板空间或者封装成本方面也没有增加。
图4说明了针对图3的栅极驱动器电路300的管芯图。
如图4所示，示范性测试芯片400可以在管芯图的上半部分中的HSgateOFF 402、LSgateOFF 403、HSpulseP 404和LSpulseP 405。HSpulseN406和LSpulseN 407可以出现于管芯图的左侧和右侧上，位于HSpulseP404和LSpulseP 405下面。
测试芯片400的上半部分可以包括在其左侧上的一对LC节点410.成对的LG节点412和LS节点414可以出现于其右侧。
继续测试芯片400的下半部分，成对的HC节点420、HG节点422以及HC节点424可以存在于其左侧。成对的L/LSgateON节点430和H/HSgateON节点432可以出现于所述左侧上。DATAIN/工refTest节点440可以出现于测试芯片400的左侧上的底部附近，而GND节点450可以出现于测试芯片400右侧上的底部附近。
四个节点可以沿测试芯片400的底部一侧出现。CLK节点460可以在最左边，在DATAIN节点440附近。节点isr pwrok 470、VBG 480和vddalv8 490可以沿测试芯片400的底部一侧顺序出现。
图5说明了管芯焊盘连接的第一实施例。如图5所示，PGND连接500可以包括硅510、不导电胶520和暴露的管芯焊盘530。结合引线540可以将硅510耦合至导线550。相反，向下结合560可以将硅510耦合至管芯焊盘530。
图6说明了管芯焊盘连接的第二实施例。如图6所示，PGND连接600可以包括硅610、导电胶620和暴露的管芯焊盘630。结合引线640可以将硅610耦合至导线650。不存在向下结合。在第二实施例中，导电胶620可以提供管芯焊盘630和硅620之间的连接。
尽管具体参考一定的示范性方面详细地描述了各种示范性实施例，应该理解的是本发明能够实现实施例，并且其细节能够在各个方面进行修改。如对于本领域普通技术人员明白的是，可以在保持处于本发明精神和范围的情况下进行各种变化和修改。因此，前述公开、描述和附图只是为了说明性的目的，而不是在任何方面限制本发明，本发明只由权利要求限定。

Claims (20)

1.一种用于电源的系统，所述系统包括：
栅极驱动器，所述栅极驱动器包括至少一个输入缓冲器、至少一个欠压监测器、至少一个输出驱动器以及暴露的管芯焊盘，其中所述至少一个输入缓冲器的地耦合至所述暴露的管芯焊盘；
微控制器，耦合至所述栅极驱动器；
第一地，耦合至所述暴露的管芯焊盘和所述微控制器两者，其中所述地对所述至少一个输入缓冲器的寄生电感进行补偿；以及
第二地，耦合至所述栅极驱动器的连接器；
所述栅极驱动器采用S0-8封装。
2.根据权利要求1所述的系统，还包括：
硅和所述暴露的管芯焊盘之间的向下结合，所述向下结合提供所述第一地。
3.根据权利要求1所述的系统，还包括：
硅和所述暴露的管芯焊盘之间的导电胶，所述导电胶提供所述第一地。
4.根据权利要求1所述的系统，其中所述至少一个输入缓冲器包括高输入缓冲器和低输入缓冲器两者。
5.根据权利要求4所述的系统，其中所述高输入缓冲器和所述低输入缓冲器两者的地耦合至所述第一地。
6.根据权利要求1所述的系统，其中所述系统只具有8个连接器。
7.根据权利要求6所述的系统，其中所述8个连接器是H、L、HC、HG、HS、LC、LG和LS连接器。
8.根据权利要求7所述的系统，其中所述微控制器耦合至所述H连接器和所述L连接器两者。
9.根据权利要求1所述的系统，其中所述至少一个输出驱动器还包括：
分别耦合至HG和LG连接器的高输出驱动器和低输出驱动器。
10.根据权利要求9所述的系统，还包括：
第一晶体管，耦合至所述HG连接器；以及
第二晶体管，耦合至所述LG连接器。
11.根据权利要求1所述的系统，其中所述第一地是数字地，而所述第二地是模拟地。
12.一种栅极驱动器，包括：
至少一个输入缓冲器；
至少一个欠压监测器；
暴露的管芯焊盘，所述暴露的管芯焊盘提供数字地；
至少一个输出驱动器，其中所述至少一个输入缓冲器的地耦合至所述暴露的管芯焊盘；以及
输出连接器，所述输出连接器提供模拟地；
所述栅极驱动器采用S0-8封装。
13.根据权利要求12所述的栅极驱动器，其中所述栅极驱动器的硅和所述暴露的管芯焊盘之间的向下结合提供所述数字地。
14.根据权利要求12所述的栅极驱动器，其中所述栅极驱动器的硅和所述暴露的管芯焊盘之间的导电胶提供所述数字地。
15.根据权利要求12所述的栅极驱动器，其中所述至少一个输入缓冲器还包括：
高输入缓冲器；以及
低输入缓冲器。
16.根据权利要求15所述的栅极驱动器，其中所述高输入缓冲器和所述低输入缓冲器两者的地耦合至所述数字地。
17.根据权利要求12所述的栅极驱动器，其中所述至少一个输出驱动器还包括：
高输出驱动器；以及
低输出驱动器。
18.根据权利要求17所述的栅极驱动器，其中所述高输出驱动器和所述低输出驱动器分别耦合至HG和LG连接器。
19.根据权利要求12所述的栅极驱动器，其中所述栅极驱动器在只具有8个连接器的集成电路IC上实现。
20.根据权利要求19所述的栅极驱动器，其中所述8个连接器是H、L、HC、HG、HS、LC、LG和LS连接器。
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CN101414447A (zh) * 2007-10-16 2009-04-22 冲电气工业株式会社 驱动电路装置

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CN103187965A (zh) 2013-07-03
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