CN103187939B - A kind of trsanscondutor of high stability - Google Patents

Abstract

The invention discloses a kind of trsanscondutor of high stability, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the first auxiliary inverter, the second auxiliary inverter, the 3rd auxiliary inverter, the 4th auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output.The present invention adopts two inverters to form input and output, and access main inverter and auxiliary inverter between the two outputs, auxiliary inverter is made to offset the admittance of the main inverter of its correspondence, considerably reduce trsanscondutor output impedance to tuning voltage sensitivity and noise sensitivity, improve the stability of filter, and high cmrr and low tuning voltage sensitivity can be realized simultaneously.The present invention can be widely used in integrated circuit as a kind of trsanscondutor of high stability of function admirable.

Description

A kind of trsanscondutor of high stability

Technical field

The present invention relates to integrated circuit fields.Particularly relate to a kind of trsanscondutor of the high stability for filter.

Background technology

Along with the development of integrated circuit technique, for radio frequency transceiver intermediate-frequency filter oneself be extensively integrated in CMOS chip, with the function providing Channel assignment and mirror image to suppress.Due to deviation and the mismatch of integrated circuit technology, the impact of layout design and variations in temperature and the factor such as aging, on sheet there is deviation in the original paper parameter of integrated filter and design load, this not only affects frequency characteristic of filter, more affect the stability of filter, filter can be caused to produce vibration, therefore, the stability of filter must be improved.

Main employing is Gm-C filter at present, the integrator that Gm-C filter is made up of trsanscondutor Gm and electric capacity C is formed, by the cut-off frequency regulating the transconductance value Gm of trsanscondutor to regulate filter, by increasing the DC output resistance of trsanscondutor, change the Q value of integrator, thus regulate the shape of filter freguency response curve.

Show current a kind of Nauta structure trsanscondutor usual in high frequency, low-voltage integrated filter in Fig. 1, it is made up of 6 identical inverters, is respectively Invl, Inv2, Inv3, Inv4, Inv5 and Inv6.Wherein, inverter Invl and Inv2 provides transconductance value to output node Vout+ and Vout-; The common mode electrical level of Inv3 ~ Inv6 tetra-inverter controlling output nodes and regulation output impedance.The control voltage Vdd that the transconductance value of all inverters can be accessed by its control end or Vddl regulates its transconductance value, and its pass is:

$\mathrm{gm}=K\frac{W}{L}(\mathrm{Vdd}-\mathrm{Vth})$

Or

$\mathrm{gm}=K\frac{W}{L}(\mathrm{Vdd}1-\mathrm{Vth})$

Wherein.K is technological parameter, for the length-width ratio of inverter, i.e. the size of inverter, Vth is the thresholds voltage sum of inverter two metal-oxide-semiconductors.

Inverter Inv4 and Inv5 is connected respectively to output end vo ut+ and Vout-with diode ten thousand formula, and be equivalent to the resistance that two are connected to output and common-mode point, resistance is respectively with inverter Inv3 and lnv6, to output node Injection Current, is equivalent to the negative resistance being connected in parallel on output node.Therefore, at Vout+ and Vout-two output nodes, inverter Inv3 ~ Inv6 is respectively the impedance that common mode electrical level shows with the impedance that differential mode level meter reveals is respectively with meanwhile, because all inverters all exist fixing output resistance, its total output resistance is set to ro, and therefore, at output node, for output end vo ut+, total differential-mode output impedance is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+\mathrm{gm}4-\mathrm{gm}3}$

Vdd and vddl is two control voltages that the filter automatic tuning circuit residing for trsanscondutor exports, a differential signal can be regarded as, filter automatic tuning circuit passes through loop adjustment, make when these two control voltage differences are Δ V, trsanscondutor output impedance reaches infinitely great, and the condition that now can obtain meeting is:

$\mathrm{gm}4-\mathrm{gm}3=K\frac{W}{L}\mathrm{\ΔV}=-\frac{1}{\mathrm{ro}}$

Thus the infinitely-great DC current gain of trsanscondutor in situation of can realizing ideal.

Owing to there is random DC maladjustment and noise in the tuning circuit of reality, and always there is process mismatch in tuning circuit and filter, like this, output Vdd and Vddl two control voltages of tuning circuit can depart from ideal value Δ V randomly:

Vdd mono-Vddl=Δ V ten δ V

Wherein, Δ V is tuning circuit when there is not DC maladjustment and noise, the difference of two control voltage Vdd and Vddl, and δ V represents the random quantity that DC maladjustment and noise are introduced.Now the differential-mode output impedance of trsanscondutor is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+\mathrm{gm}4-\mathrm{gm}3}=\frac{1}{\frac{1}{\mathrm{ro}}+K\frac{W}{L}*(\mathrm{\ΔV}+\mathrm{\δV})}=\frac{1}{K\frac{W}{L}\mathrm{\δV}}$

Therefore, by there will be two kinds of situations: when δ V is negative, the output impedance of trsanscondutor is negative, is easy to the situation that there will be vibration in high q-factor filter, what the appearance of filter freguency response curve was very large upwarps spike; When δ V is positive number, trsanscondutor output impedance is no longer infinitely great, if integrator Q value declines, filter freguency response curve will be caused to stay.In side circuit, be just enough to cause upwarping and staying of filter freguency response curved corner frequency place scholar lOdB when δ V reaches scholar 3mV.This significantly can reduce the yield of integrated circuit, substantially increases the cost of chip.Therefore, need to reduce trsanscondutor output impedance to the susceptibility of tuning voltage.

Reduce the impact of DC maladjustment, noise and the process mismatch between tuning circuit and filter, make still can obtain larger output impedance under the impact of δ V, the size of inverter Inv3 ~ Inv6 can be reduced but in order to the common mode electrical level of stable output node, if gm1=gm2, then the gain of touching altogether of trsanscondutor is less than 1, then have

$\frac{1}{\mathrm{gm}3+\mathrm{gm}4}=\frac{1}{\mathrm{gm}5+\mathrm{gm}6}<1$

Therefore, can obtain:

Gm3 ten gm4 > gm1

And

Gm5 ten gm6 > gml

Therefore, when the size of inverter Inv3 ~ Inv6 is equal, its size can only narrow down to about 0.6 times of inverter Invl and Inv2, to leave certain surplus.

The common-mode rejection ratio of trsanscondutor can be expressed as:

$\mathrm{CMRR}=\frac{\mathrm{gm}3+\mathrm{gm}4}{\mathrm{gm}3-\mathrm{gm}4}=\frac{\mathrm{gm}6+\mathrm{gm}5}{\mathrm{gm}6-\mathrm{gm}5}$

Due to filter be operated in ideally time, have under the effect of tuning voltage

$\mathrm{gm}3-\mathrm{gm}4=\mathrm{gm}6-\mathrm{gm}5=\frac{1}{\mathrm{ro}}$

Then the common-mode rejection ratio of trsanscondutor is

$\mathrm{CMRR}=\frac{\mathrm{gm}3+\mathrm{gm}4}{\frac{1}{\mathrm{ro}}}=\frac{\mathrm{gm}6+\mathrm{gm}5}{\frac{1}{\mathrm{ro}}}$

Therefore, the size reducing inverter lnv3 ~ Inv6 will reduce the common-mode rejection ratio of trsanscondutor.

As can be seen here, the shortcoming that current Nauta structure trsanscondutor is main is: too high to the susceptibility of noise and tuning voltage DC maladjustment, and current Nauta structure trsanscondutor, if turn down, trsanscondutor is lacked of proper care to tuning voltage DC, the susceptibility of mismatch and noise, will cause the reduction of common-mode rejection ratio.

Summary of the invention

In order to solve above-mentioned technical problem, the object of this invention is to provide a kind of trsanscondutor that simultaneously can realize high cmrr and low tuning voltage sensitivity of high stability.

The technical solution adopted for the present invention to solve the technical problems is:

A trsanscondutor for high stability, comprising: the first input inverter, the second input inverter, the first main inverter.Second main inverter, the 3rd main inverter, the 4th main inverter, the first auxiliary inverter, the second auxiliary inverter, the 3rd auxiliary inverter, the 4th auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end, the output of described first input inverter is connected with reversed-phase output, the input of described second input inverter is connected with inverting input, the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output; the output of described first main inverter is connected with in-phase output end; the input of the described first auxiliary inverter is all connected with in-phase output end with output, and the control end of described first main inverter and the first auxiliary inverter all accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output; the input of the described second auxiliary inverter is connected with reversed-phase output; the output of the described second auxiliary inverter is connected with in-phase output end, and the control end of described second main inverter and the second auxiliary inverter all accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output; the input of the described 3rd auxiliary inverter is connected with in-phase output end; the output of the described 3rd auxiliary inverter is connected with reversed-phase output, and the control end of described 3rd main inverter and the 3rd auxiliary inverter all accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, the output of described 4th main inverter is connected with reversed-phase output, the input of the described 4th auxiliary inverter is all connected with reversed-phase output with output, and the control end of described 4th main inverter and the 4th auxiliary inverter all accesses the first control voltage.

Further; the size of described first input inverter is equal with the size of the second input inverter; the size of described first main inverter is equal with the size of the 4th main inverter; the size of described second main inverter is equal with the size of the 3rd main inverter; the size of the described first auxiliary inverter is equal with the size of the 4th auxiliary inverter, and the size of the described second auxiliary inverter is equal with the size of the 3rd auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

Further; described first main inverter, the second main inverter, the first auxiliary inverter and second assist the size sum of inverter to be greater than the size of the first input inverter, and described 3rd main inverter, the 4th main inverter, the 3rd auxiliary inverter and the 4th assist the size sum of inverter to be greater than the size of the second input inverter;

The size of described first main inverter is greater than the size of the first auxiliary inverter, the size of described second main inverter is greater than the size of the second auxiliary inverter, the size of described 3rd main inverter is greater than the size of the 3rd auxiliary inverter, and the size of described 4th main inverter is greater than the size of the 4th auxiliary inverter.

The present invention solves another technical scheme that its technical problem adopts:

A trsanscondutor for high stability, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the first auxiliary inverter, the 4th auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end; the output of described first input inverter is connected with reversed-phase output; the input of described second input inverter is connected with inverting input; the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output; the output of described first main inverter is connected with in-phase output end; the input of the described first auxiliary inverter is all connected with in-phase output end with output, and the control end of described first main inverter and the first auxiliary inverter all accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output, and the control end of described second main inverter accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output, and the control end of described 3rd main inverter accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, the output of described 4th main inverter is connected with reversed-phase output, the input of the described 4th auxiliary inverter is all connected with reversed-phase output with output, and the control end of described 4th main inverter and the 4th auxiliary inverter all accesses the first control voltage.

Further; the size of described first input inverter is equal with the size of the second input inverter; the size of described first main inverter is equal with the size of the 4th main inverter; the size of described second main inverter is equal with the size of the 3rd main inverter, and the size of the described first auxiliary inverter is equal with the size of the 4th auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

Further; the size sum of described first main inverter, the second main inverter and the first auxiliary inverter is greater than the size of the first input inverter, and the size sum of described 3rd main inverter, the 4th main inverter and the 4th auxiliary inverter is greater than the size of the second input inverter;

The size of described first main inverter is greater than the size of the first auxiliary inverter, and the size of described 4th main inverter is greater than the size of the 4th auxiliary inverter.

The present invention solves another technical scheme that its technical problem adopts:

A trsanscondutor for high stability, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the second auxiliary inverter, the 3rd auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end; the output of described first input inverter is connected with reversed-phase output; the input of described second input inverter is connected with inverting input; the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output, and the output of described first main inverter is connected with in-phase output end, and the control end of described first main inverter accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output; the input of the described second auxiliary inverter is connected with reversed-phase output; the output of the described second auxiliary inverter is connected with in-phase output end, and the control end of described second main inverter and the second auxiliary inverter all accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output; the input of the described 3rd auxiliary inverter is connected with in-phase output end; the output of the described 3rd auxiliary inverter is connected with reversed-phase output, and the control end of described 3rd main inverter and the 3rd auxiliary inverter all accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, and the output of described 4th main inverter is connected with reversed-phase output, and the control end of described 4th main inverter accesses the first control voltage.

Further; the size of described first input inverter is equal with the size of the second input inverter; the size of described first main inverter is equal with the size of the 4th main inverter; the size of described second main inverter is equal with the size of the 3rd main inverter, and the size of the described second auxiliary inverter is equal with the size of the 3rd auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

Further; the size sum of described first main inverter, the second main inverter and the second auxiliary inverter is greater than the size of the first input inverter, and the size sum of described 3rd main inverter, the 3rd auxiliary inverter and the 4th main inverter is greater than the size of the second input inverter;

The size of described second main inverter is greater than the size of the second auxiliary inverter, and the size of described 3rd main inverter is greater than the size of the 3rd auxiliary inverter.

The invention has the beneficial effects as follows: the trsanscondutor of a kind of high stability of the present invention, two inverters are adopted to form input and output, and access main inverter and auxiliary inverter between the two outputs, auxiliary inverter is made to offset the admittance of the main inverter of its correspondence, considerably reduce trsanscondutor output impedance to tuning voltage sensitivity and noise sensitivity, improve the stability of filter, and high cmrr and low tuning voltage sensitivity can be realized simultaneously.

Accompanying drawing explanation

Below in conjunction with drawings and Examples, the invention will be further described.

Fig. 1 is the circuit diagram of the Nauta structure trsanscondutor of current techniques;

Fig. 2 is the circuit diagram of the first embodiment of the trsanscondutor of a kind of high stability of the present invention;

Fig. 3 is the circuit diagram of the second embodiment of the trsanscondutor of a kind of high stability of the present invention;

Fig. 4 is the circuit diagram of the 3rd embodiment of the trsanscondutor of a kind of high stability of the present invention.

Embodiment

With reference to Fig. 2, the first embodiment of the trsanscondutor of a kind of high stability of the present invention is as follows:

A trsanscondutor for high stability, comprising: the first input inverter lnvl, the second input inverter Inv2, the first main inverter Inv3, the second main inverter Inv4, the 3rd main inverter Inv5, the 4th main inverter Inv6, the first auxiliary inverter Inv3', the second auxiliary inverter Inv4', the 3rd auxiliary inverter Inv5', the 4th auxiliary inverter Inv6', in-phase input end Vin+', inverting input Vin-', in-phase output end Vout+ and reversed-phase output Vout-;

The input of described first input inverter Invl is connected with in-phase input end Vin+'; the output of described first input inverter Invl is connected with reversed-phase output Vout-; the input of described second input inverter Inv2 is connected with inverting input Vin-'; the output of described second input inverter lnv2 is connected with in-phase output end Vout+, and the control end of described first input inverter Invl and the second input inverter Inv2 all accesses the first control voltage;

The input of described first main inverter Inv3 is connected with reversed-phase output Vout-; the output of described first main inverter Inv3 is connected with in-phase output end Vout+; the input of the described first auxiliary inverter Inv3' is all connected with in-phase output end Vout+ with output, and the control end of the auxiliary inverter Inv3' of described first main inverter Inv3 and first all accesses the first control voltage;

The input of described second main inverter Inv4 is all connected with in-phase output end Vout+ with output; the input of the described second auxiliary inverter Inv4' is connected with reversed-phase output Vout-; the output of the described second auxiliary inverter Inv4' is connected with in-phase output end Vout+, and the control end of the auxiliary inverter Inv4' of described second main inverter Inv4 and second all accesses the second control voltage;

The input of described 3rd main inverter Inv5 is all connected with reversed-phase output Vout-with output; the input of the described 3rd auxiliary inverter Inv5' is connected with in-phase output end Vout+; the output of the described 3rd auxiliary inverter Inv5' is connected with reversed-phase output Vout-, and the control end of the auxiliary inverter Inv5' of described 3rd main inverter Inv5 and the 3rd all accesses the second control voltage;

The input of described 4th main inverter Inv6 is connected with in-phase output end Vout+, the output of described 4th main inverter Inv6 is connected with reversed-phase output Vout-, the input of the described 4th auxiliary inverter Inv6' is all connected with reversed-phase output Vout-with output, and the control end of the auxiliary inverter Inv6' of described 4th main inverter Inv6 and the 4th all accesses the first control voltage.

Described inverter all has identical structure: comprise a NMOS tube and a PMOS, as the input of inverter after the grid of described NMOS tube is connected with the grid of PMOS, as the output of inverter after the drain electrode of described NMOS tube is connected with the drain electrode of PMOS, the source electrode of described PMOS is the control end of inverter, and the source electrode of described NMOS tube is the earth terminal of inverter.

Be further used as preferred embodiment.The size of described first input inverter Invl is equal with the size of the second input inverter Inv2; the size of described first main inverter Inv3 is equal with the size of the 4th main inverter lnv6; the size of described second main inverter lnv4 is equal with the size of the 3rd main inverter lnv5; the size of the described first auxiliary inverter Inv3' is equal with the size of the 4th auxiliary inverter Inv6', and the size of the described second auxiliary inverter Inv4' is equal with the size of the 3rd auxiliary inverter Inv5';

Wherein, described size refers to the length-width ratio of inverter.

Be further used as preferred embodiment.The size sum of described first main inverter Inv3, the second main inverter Inv4, the auxiliary inverter Inv4' of the first auxiliary inverter Inv3' and second is greater than the size of the first input inverter Invl, and the size sum of described 3rd main inverter Inv5, the 4th main inverter Inv6, the auxiliary inverter Inv6' of the 3rd auxiliary inverter Inv5' and the 4th is greater than the size of the second input inverter Inv2;

The size of described first main inverter Inv3 is greater than the size of the first auxiliary inverter Inv3', the size of described second main inverter Inv4 is greater than the size of the second auxiliary inverter Inv4', the size of described 3rd main inverter Inv5 is greater than the size of the 3rd auxiliary inverter Inv5', and the size of described 4th main inverter lnv6 is greater than the size of the 4th auxiliary inverter Inv6'.

Present composition graphs 2 describes the operation principle of the present embodiment, as shown in FIG., first input inverter Inv] and the second input inverter Inv2 provide mutual conductance to output, the input of the first input inverter lnvl is connected to in-phase input end Vin+ and its output is connected to inverting input Vin-', and the input of the second input inverter Inv2 is connected to inverting input Vin-' and its output is connected to in-phase output end Vout+.Inverter lnv3, lnv4, lnv5 and lnv6 are main inverter, inverter Inv3', and " Inv4', Inv5' and Inv6' assist inverter one to one with main inverter Inv3 ~ Inv6 successively.

The control end of inverter Inv3 accesses the first control voltage Vdd, and input is connected to reversed-phase output Vout-, and output is connected to in-phase output end Vout+, for in-phase output end Vout+ provides negative resistance.The control end of inverter Inv3' accesses the first control voltage Vdd, and input and output are all connected to in-phase output end Vout+, just hinders for in-phase output end Vout+ provides.

The control end of inverter Inv4 accesses the second control voltage Vddl, and input and output are all connected to in-phase output end Vout+, just hinders for in-phase output end Vout+ provides.The control end of inverter Inv4' accesses the second control voltage Vddl, and input is connected to reversed-phase output Vout-, and output is connected to in-phase output end Vout+, for in-phase output end Vout+ provides negative resistance.

The control end of inverter Inv5 accesses the second control voltage Vddl, and input and output are all connected to reversed-phase output Vout-, just hinders for reversed-phase output Vout-provides.The control end of inverter Inv5' accesses the second control voltage Vddl, and input is connected to in-phase output end Vout+, and output is connected to reversed-phase output Vout-, for reversed-phase output Vout-provides negative resistance.

The control end of inverter Inv6 accesses the first control voltage Vdd, and input is connected to in-phase output end Vout+, and output is connected to reversed-phase output Vout-, for reversed-phase output Vout-provides negative resistance.The control end of inverter Inv6' accesses the first control voltage Vdd, and input and output are all connected to reversed-phase output Vout-, just hinders for reversed-phase output Vout-provides.

It can thus be appreciated that corresponding main inverter and the control end of auxiliary inverter all access same control voltage, and the main inverter of correspondence and auxiliary inverter respectively between the output impedance that provides symbol contrary of the same output of trsanscondutor.

With gml, gm2, gm3, gm4, gm5, gm6, gm3', gm4'.Gm5' and gm6' represents the transconductance value of inverter Invl, Inv2, Inv3, Inv4, Inv5, Inv6, Inv3', Inv4', Inv5' and Inv6' successively.

In this programme, the size of all main inverters is all greater than the size of the auxiliary inverter of its correspondence, the size of inverter Inv3 is greater than the size of inverter Inv3', the size of inverter Inv4 is greater than the size of inverter Inv4', the size of inverter Inv5 is greater than the size of inverter Inv5', and the size of inverter Inv6 is greater than the size of inverter lnv6'.Therefore, for in-phase output end Vout+, Vdd control differential mode bear admittance be gm3-gm3', Vddl control the positive admittance of differential mode be gm4-gm4'.For reversed-phase output Vout-, Vdd control differential mode bear admittance be gm6-gm6', Vddl control the positive admittance of differential mode be gm5-gm5'.Therefore, the mode that the positive admittance controlled by same control voltage and negative admittance are cancelled out each other, significantly can reduce the value of the admittance that tuning voltage controls, make when tuning voltage exists DC maladjustment, random noise or process mismatch and departs from tuning ideal value, trsanscondutor still can maintain larger output impedance.

In the present embodiment, by changing the dimension scale of main inverter and auxiliary inverter, the first control voltage Vdd aligns admittance tuning voltage susceptibility to the tuning voltage susceptibility of negative admittance and the second control voltage Vddl can be changed neatly.Such as, increase the dimension difference of main inverter and auxiliary inverter, tuning voltage susceptibility can be increased, and reduce the dimension difference of main inverter and auxiliary inverter, tuning voltage susceptibility can be reduced.Meanwhile, when the auxiliary inverter size of access control voltage Vdd or Vddl narrows down to 0, when namely removing these inverters from circuit, can circuit complexity be reduced, and same circuit function can be realized.Such as, the size of auxiliary inverter Inv4' and Inv5' can be narrowed down to 0, namely from circuit, inverter Inv4' and Inv5' is removed, second control voltage Vddl is only linked into inverter Inv4 and Inv5, now by regulating the size of inverter Inv4 and Inv5 to change the tuning voltage susceptibility that Vddl aligns admittance, concrete condition is as described in the second embodiment of the present invention.Another kind of mode is, the size of auxiliary inverter Inv3' and lnv6' is narrowed down to 0, namely from circuit, Inv3' and Inv6' is removed, first control voltage Vdd is only linked into Inv3 and Inv6, now by regulating the size of Inv3 and Inv6 to change the tuning voltage susceptibility that Vddl aligns admittance, concrete condition is as described in the third embodiment of the present invention.

The common-mode rejection ratio of the trsanscondutor of the present embodiment is:

$\mathrm{CMRR}=\frac{(\mathrm{gm}3+\mathrm{gm}{3}^{\&prime;})+(\mathrm{gm}4+\mathrm{gm}{4}^{\&prime;})}{(\mathrm{gm}3-\mathrm{gm}{3}^{\&prime;})-(\mathrm{gm}4-\mathrm{gm}{4}^{\&prime;})}=\frac{(\mathrm{gm}6+\mathrm{gm}{6}^{\&prime;})+(\mathrm{gm}5+\mathrm{gm}{5}^{\&prime;})}{(\mathrm{gm}6-\mathrm{gm}{6}^{\&prime;})-(\mathrm{gm}5-\mathrm{gm}{5}^{\&prime;})}$

Make circuit working when perfect condition, the negative admittance that gm3 ~ gm6 and gm3' ~ gm6' is formed the just positive admittance that formed of the original output resistance of bucking circuit output, namely has:

$(\mathrm{gm}3-\mathrm{gm}{3}^{\&prime;})-(\mathrm{gm}4-\mathrm{gm}{4}^{\&prime;})=(\mathrm{gm}6-\mathrm{gm}{6}^{\&prime;})-(\mathrm{gm}5-\mathrm{gm}{5}^{\&prime;})=\frac{1}{\mathrm{ro}}$

Therefore, the common-mode rejection ratio of the trsanscondutor of the present embodiment can be expressed as:

$\mathrm{CMRR}=\frac{(\mathrm{gm}3+\mathrm{gm}{3}^{\&prime;})+(\mathrm{gm}4+\mathrm{gm}{4}^{\&prime;})}{\frac{1}{\mathrm{ro}}}=\frac{(\mathrm{gm}6+\mathrm{gm}{6}^{\&prime;})+(\mathrm{gm}5+\mathrm{gm}{5}^{\&prime;})}{\frac{1}{\mathrm{ro}}}$

For in-phase output end Vout+, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+(\mathrm{gm}4-\mathrm{gm}{4}^{\&prime;})-(\mathrm{gm}3-\mathrm{gm}{3}^{\&prime;})}=\frac{1}{\frac{1}{\mathrm{ro}}+(\mathrm{gm}4-\mathrm{gm}3)-(\mathrm{gm}{4}^{\&prime;}-\mathrm{gm}{3}^{\&prime;})}$

In balanced differential design, the relation of the transconductance value of inverter Invl and the transconductance value of inverter Inv2 is: gml=gm2, in order to stable common mode output voltage, and gm3, gm4, gm3', gm4' sum must be greater than gml, and gm5, gm6, gm5', gm6' sum must be greater than gm2, namely must be greater than gml.And in order to have impedance-tumed function, gm3 > gm3' must be met, gm4 > gm4', gm5 > gm5', gm6 > gm6', therefore.The size of each main inverter must be greater than the size of the auxiliary inverter of its correspondence.

Make the size of Inv3, Inv4, Inv5 and Inv6 equal, and be a times of inverter Invl, the size with seasonal inverter lnv3', Inv4', Inv5' and Inv6' is equal, and is b times of inverter Invl, therefore, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+(\mathrm{gm}4-\mathrm{gm}3)-(\mathrm{gm}{4}^{\&prime;}-\mathrm{gm}{3}^{\&prime;})}=\frac{1}{\frac{1}{\mathrm{ro}}+\mathrm{Ka}\frac{W}{L}(\mathrm{\&Delta;V}+\mathrm{\&delta;V})-\mathrm{Kb}\frac{W}{L}(\mathrm{\&Delta;V}+\mathrm{\&delta;V})}$

$=\frac{1}{\frac{1}{\mathrm{ro}}+K(a-b)\frac{W}{L}\mathrm{\&Delta;V}+K(a-b)\frac{W}{L}\mathrm{\&delta;V}}$

Wherein, Δ V is ideally, and trsanscondutor output impedance reaches infinitely great, across seek device reach infinitely-great DC current gain time, the voltage difference of the first control voltage Vdd and the second control voltage Vddl.Owing to there is random DC maladjustment and noise in the tuning circuit of reality, and always there is process mismatch in tuning circuit and filter, like this, output Vdd and Vddl two control voltages of tuning circuit can depart from ideal value Δ V randomly:

Vdd-Vddl=ΔV+δV

Wherein, Δ V is tuning circuit when there is not DC maladjustment and noise, the difference of two control voltage Vdd and Vddl, and δ V represents the random quantity that DC maladjustment and noise are introduced.

In the ideal situation, δ V is 0, and meets the following conditions:

$\frac{1}{\mathrm{ro}}+K(a-b)\frac{W}{L}\mathrm{\&Delta;V}=0$

Therefore, under can obtaining nonideality, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{K(a-b)\frac{W}{L}\mathrm{\&delta;V}}=\frac{1}{a-b}\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

Because a, b are all little than 1, therefore the differential-mode output impedance of trsanscondutor increases to original doubly.

In conjunction with the formula of the common-mode rejection ratio of this trsanscondutor, known, the size of the main inverter of choose reasonable and auxiliary inverter, can avoid reducing common-mode rejection ratio.Such as, make a=0.6, b=0.4, namely inverter Inv3 ~ Inv6 is of a size of 0.6 times of inverter Invl, and inverter Inv3' ~ Inv6' is of a size of 0.4 times of inverter Invl, and therefore, differential-mode output impedance is 5 times of Nauta structure trsanscondutor current in Fig. 1:

$\mathrm{Zdiff}=\frac{1}{a-b}\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}=\frac{1}{0.6-0.4}\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}=5\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

Need to reduce further the susceptibility of trsanscondutor to tuning voltage DC imbalance and noise, under the main inverter of maintenance and auxiliary inverter size sum are greater than the prerequisite of 0.5 times of the size of inverter Invl, the difference of main inverter with the size of auxiliary anti-device can also be reduced further.Such as make a=0.55, b=0.45, namely inverter Inv3 ~ Inv6 is of a size of 0.55 times of inverter lnv1, and inverter Inv3' ~ Inv6' is of a size of 0.45 times of inverter lnvl, and therefore differential-mode output impedance is 10 times of current Nauta structure trsanscondutor:

$\mathrm{Zdiff}=\frac{1}{a-b}\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}=\frac{1}{0.55-0.45}\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}=10\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

Therefore, adopt the structure of the present embodiment greatly can reduce the susceptibility of trsanscondutor to tuning voltage DC imbalance and noise, make filter still can keep larger output impedance when tuning circuit exists DC maladjustment and noise, keep good frequency characteristic, improve the stability of filter.

Simultaneously, size sum due to inverter lnv3 and Inv3' equals the inverter Inv3 in Fig. 1, thus the electric current sum consumed also equals the inverter Inv3 in Fig. 1, the size sum of inverter Inv4 and Inv3' equals the inverter Inv4 of Fig. 1 Shen, thus the electric current sum consumed also equals the inverter Inv4 in Fig. 1, the size sum of inverter Inv5 and Inv5' equals the inverter Inv5 in Fig. 1, thus the electric current sum consumed also equals the inverter Inv5 in Fig. 1, the size sum of inverter Inv6 and Inv6' equals the inverter Inv6 in Fig. 1, thus the electric current sum consumed also equals the inverter Inv6 in Fig. 1, namely the shared silicon area of whole trsanscondutor and the electric current of consumption remain unchanged in integrated circuits.

Because inverter Inv3 is equal with inverter Inv5 size, inverter Inv4 is equal with inverter Inv6 size, inverter lnv3' is equal with inverter Inv6' size, inverter Inv4' is equal with inverter Inv5' size, therefore, the discussion to inverter Inv5, Inv6, Inv4' and Inv5' is omitted.

With reference to Fig. 3, the second embodiment of the trsanscondutor of a kind of high stability of the present invention is as follows:

A trsanscondutor for high stability, comprising: the first input inverter Invl, the second input inverter Inv2, the first main inverter Inv3, the second main inverter Inv4, the 3rd main inverter Inv5, the 4th main inverter InV6, the first auxiliary inverter Inv3', the 4th auxiliary inverter Inv6', in-phase input end Vin+'.Inverting input Vin-', in-phase output end Vout+ and reversed-phase output Vout-;

The input of described first input inverter Invl is connected with in-phase input end Vin+'; the output of described first input inverter Invl is connected with reversed-phase output Vout-; the input of described second input inverter Inv2 is connected with inverting input Vin-'; the output of described second input inverter Inv2 is connected with in-phase output end Vout+, and the control end of described first input inverter Invl and the second input inverter Inv2 all accesses the first control voltage;

The input of described first main inverter Inv3 is connected with reversed-phase output Vout-; the output of described first main inverter Inv3 is connected with in-phase output end Vout+; the input of the described first auxiliary inverter Inv3' is all connected with in-phase output end Vout+ with output, and the control end of the auxiliary inverter Inv3' of described first main inverter Inv3 and first all accesses the first control voltage;

The input of described second main inverter Inv4 is all connected with in-phase output end Vout+ with output, and the control end of described second main inverter Inv4 accesses the second control voltage;

The input of described 3rd main inverter Inv5 is all connected with reversed-phase output Vout-with output, and the control end of described 3rd main inverter Inv5 accesses the second control voltage;

The input of described 4th main inverter Inv6 is connected with in-phase output end Vout+, the output of described 4th main inverter Inv6 is connected with reversed-phase output Vout-, the input of the described 4th auxiliary inverter Inv6' is all connected with reversed-phase output Vout-with output, and the control end of the auxiliary inverter lnv6' of described 4th main inverter Inv6 and the 4th all accesses the first control voltage.

Described inverter all has identical structure: comprise a NMOS tube and a PMOS, as the input of inverter after the grid of described NMOS tube is connected with the grid of PMOS, as the output of inverter after the drain electrode of described NMOS tube is connected with the drain electrode of PMOS, the source electrode of described PMOS is the control end of inverter, and the source electrode of described NMOS tube is the earth terminal of inverter.

Be further used as preferred embodiment; the size of described first input inverter Invl is equal with the size of the second input inverter Inv2; the size of described first main inverter Inv3 is equal with the size of the 4th main inverter Inv6; the size of described second main inverter Inv4 is equal with the size of the 3rd main inverter Inv5, and the size of the described first auxiliary inverter Inv3' is equal with the size of the 4th auxiliary inverter Inv6';

Wherein, described size refers to the length-width ratio of inverter.

Be further used as preferred embodiment; the size sum of the auxiliary inverter Inv3' of described first main inverter Inv3, the second main inverter Inv4 and first is greater than the size of the first input inverter Invl, and the size sum of the auxiliary inverter Inv6' of described 3rd main inverter lnv5, the 4th main inverter Inv6 and the 4th is greater than the size of the second input inverter Inv2;

The size of described first main inverter lnv3 is greater than the size of the first auxiliary inverter Inv3', and the size of described 4th main inverter lnv6 is greater than the size of the 4th auxiliary inverter Inv6'.

The present embodiment is a kind of special case of embodiment in Fig. 2, the size of inverter Inv4' and Inv5' auxiliary in Fig. 2 is narrowed down to 0, namely from circuit, inverter Inv4' and Inv5' is removed, second control voltage Vdd1 is only linked into inverter Inv4 and Inv5, changes by regulating the size of inverter Inv4 and Inv5 the tuning voltage susceptibility that Vdd1 aligns admittance.

In the present embodiment, the common-mode rejection ratio of trsanscondutor is:

$\mathrm{CMRR}=\frac{(\mathrm{gm}3+\mathrm{gm}{3}^{\&prime;})+\mathrm{gm}4}{\frac{1}{\mathrm{ro}}}=\frac{(\mathrm{gm}6+\mathrm{gm}{6}^{\&prime;})+\mathrm{gm}5}{\frac{1}{\mathrm{ro}}}$

For in-phase output end Vout+, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+\mathrm{gm}4-(\mathrm{gm}3-\mathrm{gm}{3}^{\&prime;})}$

Therefore, by regulating the transconductance value of inverter Inv3 and Inv3', regulate trsanscondutor to the susceptibility of tuning voltage, the transconductance value of inverter Inv3 and Inv3' is more close, and the susceptibility of trsanscondutor to tuning voltage is lower.

The size of inverter Inv3, Inv3' and Inv4 is made to equal 0.5 times of inverter lnv1 respectively.0.3 times and 0.2 times.The differential-mode output impedance that then can obtain the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}\mathrm{Vdd}1-(0.5K\frac{W}{L}\mathrm{Vdd}-0.3K\frac{W}{L}\mathrm{Vdd})}$

$=\frac{1}{\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}(\mathrm{Vdd}1-\mathrm{Vdd})}=\frac{1}{\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}\mathrm{\&Delta;V}+0.2K\frac{W}{L}\mathrm{\&delta;V}}$

Similar with the first embodiment, suppose that trsanscondutor output impedance reaches infinitely great when the voltage difference that first controls voltage Vdd processed and the second control voltage Vdd1 is △ V, make in the ideal case, trsanscondutor reaches infinitely-great DC current gain, now, then satisfies condition:

$\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}\mathrm{\&Delta;V}=0$

Therefore, under nonideality, the differential-mode output impedance of the present embodiment is 5 times of trsanscondutor as shown in Figure 1:

$\mathrm{Zdiff}=\frac{1}{0.2K\frac{W}{L}\mathrm{\&delta;V}}=5\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

If desired the susceptibility of trsanscondutor to the imbalance of tuning voltage DC and noise is reduced further, under the main inverter of maintenance and auxiliary inverter size sum are greater than the prerequisite of 0.5 times of the size of inverter Invl, the difference of main inverter with the size of auxiliary anti-device can also be reduced further.Such as, the size of inverter Inv3, Inv3' and Inv4 is made to equal 0.55 times, 0.45 times and 0.1 times of inverter Invl respectively.The differential-mode output impedance that then can obtain the trsanscondutor of the present embodiment is 10 times of trsanscondutor as shown in Figure 1:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+0.1K\frac{W}{L}\mathrm{Vdd}1-(0.55K\frac{W}{L}\mathrm{Vdd}-0.45K\frac{W}{L}\mathrm{Vdd})}=10\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

Therefore, as a kind of special case of the first embodiment in Fig. 2, as long as the dimension difference maintaining inverter Inv3 and Inv3' equals the size of inverter Inv4, then the trsanscondutor of the present embodiment also can reduce the susceptibility of trsanscondutor to the imbalance of tuning voltage DC and noise greatly, make filter still can keep larger output impedance when tuning circuit exists DC maladjustment and noise, keep good frequency characteristic, improve the stability of filter.

Because inverter Inv3 is equal with inverter Inv5 size, inverter Inv4 is equal with inverter Inv6 size, and inverter Inv3' is equal with inverter Inv6' size, therefore, omits inverter Inv5.The discussion of Inv6 and Inv6.

With reference to Fig. 4, the 3rd embodiment of the trsanscondutor of a kind of high stability of the present invention is as follows:

A trsanscondutor for high stability, comprising: the first input inverter Invl.Second input inverter Inv2, the first main inverter Inv3, the second main inverter lnv4, the 3rd main inverter Inv5, the 4th main inverter Inv6, the second auxiliary inverter Inv4', the 3rd auxiliary inverter Inv5', in-phase input end Vin+'.Inverting input Vin-', in-phase output end Vout+ and reversed-phase output Vout-;

The input of described first input inverter Invl is connected with in-phase input end Vin+'; the output of described first input inverter Invl is connected with reversed-phase output Vout-; the input of described second input inverter Inv2 is connected with inverting input Vin-'; the output of described second input inverter lnv2 is connected with in-phase output end Vout+, and the control end of described first input inverter Invl and the second input inverter Inv2 all accesses the first control voltage;

The input of described first main inverter Inv3 is connected with reversed-phase output Vout-, and the output of described first main inverter Inv3 is connected with in-phase output end Vout+, and the control end of described first main inverter Inv3 accesses the first control voltage;

The input of described second main inverter Inv4 is all connected with in-phase output end Vout+ with output; the input of the described second auxiliary inverter Inv4' is connected with reversed-phase output Vout-; the output of the described second auxiliary inverter Inv4' is connected with in-phase output end Vout+, and the control end of the auxiliary inverter Inv4' of described second main inverter Inv4 and second all accesses the second control voltage;

The input of described 3rd main inverter Inv5 is all connected with reversed-phase output Vout-with output; the input of the described 3rd auxiliary inverter Inv5' is connected with in-phase output end Vout+; the output of the described 3rd auxiliary inverter Inv5' is connected with reversed-phase output Vout-, and the control end of the auxiliary inverter Inv5' of described 3rd main inverter Inv5 and the 3rd all accesses the second control voltage;

The input of described 4th main inverter Inv6 is connected with in-phase output end Vout+, and the output of described 4th main inverter Inv6 is connected with reversed-phase output Vout-, and the control end of described 4th main inverter Inv6 accesses the first control voltage.

Described inverter all has identical structure: comprise a NMOS tube and a PMOS, as the input of inverter after the grid of described NMOS tube is connected with the grid of PMOS, as the output of inverter after the drain electrode of described NMOS tube is connected with the drain electrode of PMOS, the source electrode of described PMOS is the control end of inverter, and the source electrode of described NMOS tube is the earth terminal of inverter.

Be further used as preferred enforcement ten thousand formulas, the size of described first input inverter Invl is equal with the size of the second input inverter Inv2, the size of described first main inverter Inv3 is equal with the size of the 4th main inverter lnv6, the size of described second main inverter lnv4 is equal with the size of the 3rd main inverter lnv5, and the size of the described second auxiliary inverter Inv4' is equal with the size of the 3rd auxiliary inverter Inv5'.

Be further used as preferred enforcement ten thousand formulas; the size sum of the auxiliary inverter Inv4' of described first main inverter Inv3, the second main inverter Inv4 and second is greater than the size of the first input inverter Invl, and the size sum of described 3rd main inverter Inv5, the 3rd auxiliary inverter Inv5' and the 4th main inverter Inv6 is greater than the size of the second input inverter Inv2;

The size of described second main inverter Inv4 is greater than the size of the second auxiliary inverter Inv4', and the size of described 3rd main inverter Inv5 is greater than the size of the 3rd auxiliary inverter Inv5'.

The present embodiment is the another kind of special case of embodiment in Fig. 2, the size of inverter Inv3' and Inv6' auxiliary in Fig. 2 is narrowed down to 0, namely from circuit, inverter Inv3' and Inv6' is removed, first control voltage Vdd is only linked into inverter lnv3 and Inv6, changes by regulating the size of inverter Inv3 and Inv6 the tuning voltage susceptibility that Vdd aligns admittance.

In the present embodiment, the common-mode rejection ratio of trsanscondutor is:

$\mathrm{CMRR}=\frac{\mathrm{gm}3+(\mathrm{gm}4+\mathrm{gm}{4}^{\&prime;})}{\frac{1}{\mathrm{ro}}}=\frac{\mathrm{gm}6+(\mathrm{gm}5+\mathrm{gm}{5}^{\&prime;})}{\frac{1}{\mathrm{ro}}}$

For in-phase output end Vout+, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+(\mathrm{gm}4-\mathrm{gm}{4}^{\&prime;})-\mathrm{gm}3}$

Therefore, by regulating the transconductance value of inverter Inv4 and Inv4', regulate trsanscondutor to the susceptibility of tuning voltage, the transconductance value of inverter Inv4 and lnv4' is more close, and the susceptibility of trsanscondutor to tuning voltage is lower.

The size of inverter Inv3, Inv4 and Inv4' is made to equal 0.2 times of inverter lnvl respectively.0.5 times and 0.3 times.The negative admittance that then the first control voltage Vdd controls is 0.2*gml, and the positive admittance that the second control voltage controls is (0.5-0.3) * gm1=0.2*gml.The combination of inverter lnv4 and Inv4' can be equivalent to the inverter that is of a size of 0.2 times of the size of inverter Invl.Now, the differential-mode output impedance of the trsanscondutor of the present embodiment is:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+(0.5K\frac{W}{L}\mathrm{Vdd}1-0.3K\frac{W}{L}\mathrm{Vdd}1)-0.2K\frac{W}{L}\mathrm{Vdd}}$

$=\frac{1}{\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}\mathrm{\&Delta;V}+0.2K\frac{W}{L}\mathrm{\&delta;V}}$

Similar with the first embodiment, suppose when the voltage difference of the first control voltage vdd and the second control voltage vddl is Δ V, trsanscondutor output impedance reaches infinitely great, and make in the ideal case, trsanscondutor reaches infinitely-great DC current gain, now, then satisfies condition:

$\frac{1}{\mathrm{ro}}+0.2K\frac{W}{L}\mathrm{\&Delta;V}=0$

Therefore, non-bury think state under, the differential-mode output impedance of the present embodiment is 5 times of trsanscondutor as shown in Figure 1:

$\mathrm{Zdiff}=\frac{1}{0.2K\frac{W}{L}\mathrm{\&delta;V}}=5\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

If desired the susceptibility of trsanscondutor to the imbalance of tuning voltage DC and noise is reduced further, under the main inverter of maintenance and auxiliary inverter size sum are greater than the prerequisite of 0.5 times of the size of inverter Inv1, the difference of main inverter with the size of auxiliary anti-device can also be reduced further.Such as, the size of inverter Inv3, Inv4 and Inv4' is made to equal 0.1 times, 0.55 times and 0.45 times of inverter Invl respectively.10 times that the differential-mode output impedance that then can obtain the trsanscondutor of the present embodiment is the such as trsanscondutor shown in Fig. 1 Shen:

$\mathrm{Zdiff}=\frac{1}{\frac{1}{\mathrm{ro}}+(0.55K\frac{W}{L}\mathrm{Vdd}1-0.45K\frac{W}{L}\mathrm{Vdd}1)-0.1K\frac{W}{L}\mathrm{Vdd}}=10\&CenterDot;\frac{1}{K\frac{W}{L}\mathrm{\&delta;V}}$

Therefore, as the another kind of special case of the first embodiment in Fig. 2, as long as the dimension difference maintaining inverter Inv4 and Inv4' equals the size of inverter Inv3, then the trsanscondutor of the present embodiment also can reduce the susceptibility of trsanscondutor to the imbalance of tuning voltage DC and noise greatly, make filter still can keep larger output impedance when tuning circuit exists DC maladjustment and noise, keep good frequency characteristic, improve the stability of filter.

Because inverter lnv3 is equal with inverter Inv5 size, inverter lnv4 is equal with inverter Inv6 size, and inverter Inv4' is equal with inverter Inv5' size, therefore, omits the discussion to inverter Inv5, Inv6 and Inv5'.

3 embodiments of the present invention are all the admittance by regulating the dimension difference of main inverter and auxiliary inverter to carry out regulation output end, thus reach the object reducing tuning voltage susceptibility, belong to a total inventive concept, the second embodiment and the 3rd embodiment are the special cases of the first embodiment.

More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent modification or replacement are all included in the application's claim limited range.

Claims (6)

1. the trsanscondutor of a high stability, it is characterized in that, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the first auxiliary inverter, the second auxiliary inverter, the 3rd auxiliary inverter, the 4th auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end, the output of described first input inverter is connected with reversed-phase output, the input of described second input inverter is connected with inverting input, the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output, the output of described first main inverter is connected with in-phase output end, the input of the described first auxiliary inverter is all connected with in-phase output end with output, and the control end of described first main inverter and the first auxiliary inverter all accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output, the input of the described second auxiliary inverter is connected with reversed-phase output, the output of the described second auxiliary inverter is connected with in-phase output end, and the control end of described second main inverter and the second auxiliary inverter all accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output, the input of the described 3rd auxiliary inverter is connected with in-phase output end, the output of the described 3rd auxiliary inverter is connected with reversed-phase output, and the control end of described 3rd main inverter and the 3rd auxiliary inverter all accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, the output of described 4th main inverter is connected with reversed-phase output, the input of the described 4th auxiliary inverter is all connected with reversed-phase output with output, and the control end of described 4th main inverter and the 4th auxiliary inverter all accesses the first control voltage;

The size of described first input inverter is equal with the size of the second input inverter, the size of described first main inverter is equal with the size of the 4th main inverter, the size of described second main inverter is equal with the size of the 3rd main inverter, the size of the described first auxiliary inverter is equal with the size of the 4th auxiliary inverter, and the size of the described second auxiliary inverter is equal with the size of the 3rd auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

2. the trsanscondutor of a kind of high stability according to claim 1, it is characterized in that, described first main inverter, the second main inverter, the first auxiliary inverter and second assist the size sum of inverter to be greater than the size of the first input inverter, and described 3rd main inverter, the 4th main inverter, the 3rd auxiliary inverter and the 4th assist the size sum of inverter to be greater than the size of the second input inverter;

The size of described first main inverter is greater than the size of the first auxiliary inverter, the size of described second main inverter is greater than the size of the second auxiliary inverter, the size of described 3rd main inverter is greater than the size of the 3rd auxiliary inverter, and the size of described 4th main inverter is greater than the size of the 4th auxiliary inverter.

3. the trsanscondutor of a high stability, it is characterized in that, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the first auxiliary inverter, the 4th auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end, the output of described first input inverter is connected with reversed-phase output, the input of described second input inverter is connected with inverting input, the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output, the output of described first main inverter is connected with in-phase output end, the input of the described first auxiliary inverter is all connected with in-phase output end with output, and the control end of described first main inverter and the first auxiliary inverter all accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output, and the control end of described second main inverter accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output, and the control end of described 3rd main inverter accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, the output of described 4th main inverter is connected with reversed-phase output, the input of the described 4th auxiliary inverter is all connected with reversed-phase output with output, and the control end of described 4th main inverter and the 4th auxiliary inverter all accesses the first control voltage;

The size of described first input inverter is equal with the size of the second input inverter, the size of described first main inverter is equal with the size of the 4th main inverter, the size of described second main inverter is equal with the size of the 3rd main inverter, and the size of the described first auxiliary inverter is equal with the size of the 4th auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

4. the trsanscondutor of a kind of high stability according to claim 3, it is characterized in that, the size sum of described first main inverter, the second main inverter and the first auxiliary inverter is greater than the size of the first input inverter, and the size sum of described 3rd main inverter, the 4th main inverter and the 4th auxiliary inverter is greater than the size of the second input inverter;

The size of described first main inverter is greater than the size of the first auxiliary inverter, and the size of described 4th main inverter is greater than the size of the 4th auxiliary inverter.

5. the trsanscondutor of a high stability, it is characterized in that, comprising: the first input inverter, the second input inverter, the first main inverter, the second main inverter, the 3rd main inverter, the 4th main inverter, the second auxiliary inverter, the 3rd auxiliary inverter, in-phase input end, inverting input, in-phase output end and reversed-phase output;

The input of described first input inverter is connected with in-phase input end, the output of described first input inverter is connected with reversed-phase output, the input of described second input inverter is connected with inverting input, the output of described second input inverter is connected with in-phase output end, and the control end of described first input inverter and the second input inverter all accesses the first control voltage;

The input of described first main inverter is connected with reversed-phase output, and the output of described first main inverter is connected with in-phase output end, and the control end of described first main inverter accesses the first control voltage;

The input of described second main inverter is all connected with in-phase output end with output, the input of the described second auxiliary inverter is connected with reversed-phase output, the output of the described second auxiliary inverter is connected with in-phase output end, and the control end of described second main inverter and the second auxiliary inverter all accesses the second control voltage;

The input of described 3rd main inverter is all connected with reversed-phase output with output, the input of the described 3rd auxiliary inverter is connected with in-phase output end, the output of the described 3rd auxiliary inverter is connected with reversed-phase output, and the control end of described 3rd main inverter and the 3rd auxiliary inverter all accesses the second control voltage;

The input of described 4th main inverter is connected with in-phase output end, and the output of described 4th main inverter is connected with reversed-phase output, and the control end of described 4th main inverter accesses the first control voltage;

The size of described first input inverter is equal with the size of the second input inverter, the size of described first main inverter is equal with the size of the 4th main inverter, the size of described second main inverter is equal with the size of the 3rd main inverter, and the size of the described second auxiliary inverter is equal with the size of the 3rd auxiliary inverter;

Wherein, described size refers to the length-width ratio of inverter.

6. the trsanscondutor of a kind of high stability according to claim 5, it is characterized in that, the size sum of described first main inverter, the second main inverter and the second auxiliary inverter is greater than the size of the first input inverter, and the size sum of described 3rd main inverter, the 3rd auxiliary inverter and the 4th main inverter is greater than the size of the second input inverter;

The size of described second main inverter is greater than the size of the second auxiliary inverter, and the size of described 3rd main inverter is greater than the size of the 3rd auxiliary inverter.