CN103187257B - The formation method of metal gates - Google Patents
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- CN103187257B CN103187257B CN201110454121.XA CN201110454121A CN103187257B CN 103187257 B CN103187257 B CN 103187257B CN 201110454121 A CN201110454121 A CN 201110454121A CN 103187257 B CN103187257 B CN 103187257B
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Abstract
A formation method for metal gates, comprising: provide Semiconductor substrate, and described Semiconductor substrate is formed with alternative gate; Form dielectric layer on the semiconductor substrate, described dielectric layer surface is concordant with alternative gate surface; Titanium nitride layer is formed at dielectric layer and alternative gate surface; Oxidation processes is carried out to described titanium nitride layer, forms titanium dioxide layer on titanium nitride layer surface; Titanium dioxide layer is formed patterned photoresist layer, and described patterned photoresist layer has the first opening of corresponding alternative gate; With described patterned photoresist layer for mask, etch titanium dioxide layer and titanium nitride layer successively, form the second opening exposing alternative gate surface; With described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, form groove, in groove, fill full metal, form metal gates.First opening of embodiment of the present invention morphogenesis characters dimensionally stable in photoresist layer, facilitates the control of photoetching process stage first opening features size.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of metal gates.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in MOS transistor.In order to avoid the metal material of metal gates is on the impact of other structures of transistor, the gate stack structure of described metal gates and high K gate dielectric layer adopts " rear grid (gate last) " technique to make usually.
Fig. 1 ~ Fig. 4 is the cross-sectional view that existing employing " rear grid (gate last) " technique makes metal gates.
With reference to figure 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 is formed with alternative gate structure, described alternative gate structure comprises the gate dielectric layer 102 being positioned at Semiconductor substrate 100 surface and the alternative gate 103 be positioned on gate medium 102, the material of described alternative gate 103 is polysilicon, and the sidewall of described grid structure is also formed with side wall (not shown); Form dielectric layer 104 on Semiconductor substrate 100 surface, the surface of dielectric layer 104 is concordant with the surface of alternative gate 103; Titanium nitride layer 105 is formed at alternative gate 103 and dielectric layer 104 surface, separator between the photoresist layer of described titanium nitride layer 105 grid 103 and follow-up formation as an alternative, prevent photoresist layer from contacting with the direct of polysilicon alternative gate, cause the residual of photoresist on polysilicon alternative gate surface, affect the removal of follow-up polysilicon alternative gate; Described titanium nitride layer 105 forms photoresist layer 106, graphical described photoresist layer 106, in photoresist layer 106, form the first opening 10 exposing titanium nitride layer 105 surface, the position of the corresponding alternative gate 103 in position of described first opening 10.
With reference to figure 2, with described patterned photoresist layer 106 for mask, etch described titanium nitride layer 105 along the first opening 10, form the second opening 20 exposing alternative gate 103 surface.
With reference to figure 3, with described patterned photoresist layer 106 and titanium nitride layer 105 for mask, remove described alternative gate 103 (shown in Fig. 2), form groove 107.
With reference to figure 4, remove the patterned photoresist layer 106 shown in Fig. 3 and titanium nitride layer 105, in groove, fill full metal, form metal gates 108.
More formation methods about metal gates please refer to the United States Patent (USP) that publication number is US2002/0064964A1.
The formation method of existing metal gates, in the photoetching process stage, the first opening 10 that graphical photoresist layer 106 is formed, the feature size variations of the first opening 10 is larger, be unfavorable for the control of the characteristic size of photoetching process stage first opening 10, and affect the follow-up formation of the second opening 20 and the etching of alternative gate 103.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of metal gates, and in photoresist layer, the first opening of morphogenesis characters dimensionally stable, facilitates the control of photoetching process stage first opening features size.
For solving the problem, the invention provides a kind of formation method of metal gates, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with alternative gate;
Form dielectric layer on the semiconductor substrate, described dielectric layer surface is concordant with alternative gate surface;
Titanium nitride layer is formed at dielectric layer and alternative gate surface;
Oxidation processes is carried out to described titanium nitride layer, forms titanium dioxide layer on titanium nitride layer surface;
Titanium dioxide layer is formed patterned photoresist layer, and described patterned photoresist layer has the first opening of corresponding alternative gate;
With described patterned photoresist layer for mask, etch titanium dioxide layer and titanium nitride layer successively, form the second opening exposing alternative gate surface;
With described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, form groove, in groove, fill full metal, form metal gates.
Optionally, the described oxidation processes to titanium nitride layer is cineration technics or furnace process.
Optionally, the gas that described cineration technics adopts is oxygen, and reaction temperature is 40 degrees Celsius ~ 250 degrees Celsius, and oxygen flow is 10sccm ~ 1000sccm.
Optionally, the gas that described furnace process adopts is oxygen, and reaction temperature is 400 degrees Celsius ~ 800 degrees Celsius, and oxygen flow is 10sccm ~ 30sccm.
Optionally, the thickness of described titanium nitride layer is 20 dust ~ 200 dusts.
Optionally, the formation process of described titanium nitride layer is physical vapour deposition (PVD).
Optionally, described alternative gate surface and sidewall and semiconductor substrate surface are formed with etching stop layer.
Optionally, the material of described etching stop layer is the silicon nitride of tension stress or the silicon nitride of compression.
Optionally, the forming process of described dielectric layer is: form layer of dielectric material on etching stop layer surface; Layer of dielectric material described in cmp and etching stop layer, with alternative gate surface for stop-layer, form dielectric layer, the surface of dielectric layer is concordant with alternative gate surface.
Optionally, the forming process of described metal gates is: with described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, forms groove; Remove described patterned photoresist layer, titanium dioxide layer and titanium nitride layer; Form the metal level covering groove, etching stop layer, dielectric layer surface; Metal level described in cmp take dielectric layer surface as stop-layer, forms metal gates.
Optionally, also gate dielectric layer is formed with between described alternative gate and Semiconductor substrate.
Optionally, the material of described gate dielectric layer is silica, silicon oxynitride or high K dielectric material.
Optionally, the material of described metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Optionally, described before formation metal gates, also comprise step: at sidewall and the bottom formation diffusion impervious layer of groove.
Optionally, the material of described diffusion impervious layer is TiN or TaN.
Optionally, described diffusion impervious layer surface is formed with functional layer.
Optionally, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
Compared with prior art, technical solution of the present invention has the following advantages:
Before titanium nitride layer surface forms photoresist layer, oxidation processes is carried out to described titanium nitride layer, the titanium on titanium nitride layer surface and oxygen reaction is made to form the stable titanium dioxide layer of one deck, titanium dioxide layer make titanium nitride layer and air isolated, prevent titanium nitride layer from exposing and oxidation reaction slowly occurs in atmosphere, the extinction coefficient (K) on titanium nitride layer surface and refraction coefficient (N) is made to keep stable, follow-up when forming the first opening in photoresist layer, because the extinction coefficient (K) on titanium nitride layer surface and refraction coefficient (N) keep stable, with under identical conditions of exposure, the impact of titanium nitride layer on the light that exposure bench produces is constant, the characteristic size forming the first opening in photoresist layer is made to keep stable, facilitate the control of the characteristic size of photoetching process stage first opening, the characteristic size of the first opening keeps stable, the characteristic size of follow-up the second opening formed for mask etching titanium nitride layer with patterned photoresist layer is made to keep stable, during with patterned photoresist layer and titanium nitride layer for mask etching alternative gate, the etching of alternative gate can not be affected.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of existing metal gates forming process;
Fig. 5 is the schematic flow sheet of embodiment of the present invention method for forming metallic grid;
Fig. 6 ~ Figure 13 is the cross-sectional view of embodiment of the present invention metal gates forming process.
Embodiment
With reference to figure 1, in the forming process of existing making metal gates, in the photoetching process stage, described titanium nitride layer 105 forms photoresist layer 106, graphical described photoresist layer 106, form the first opening 10 exposing titanium nitride layer 105 surface, after formation first opening 10, generally to measure the characteristic size (CD) of the first opening 10 and whether stablize with monitoring photoetching technology, inventor finds in actual production process, the characteristic size (CD) of the first opening 10 often changes, offset criteria value, and the time that (before forming photoresist layer 106) stops before entering photoetching process is longer, side-play amount between the characteristic size (CD) of the first opening 10 and standard value is larger.
Inventor studies discovery further, titanium nitride layer 105 is placed in air can there is oxidation reaction slowly, the titanium on titanium nitride layer 105 surface can react with the oxygen in air formation titanium dioxide, the time that titanium nitride layer 105 is placed in air is more of a specified duration, the titanium on titanium nitride layer 105 surface is more oxidized, the Facing material of titanium nitride layer 105 is changed, existing titanium nitride has titanium dioxide again, affect extinction coefficient (K) and the refraction coefficient (N) of titanium nitride layer 105, the time that titanium nitride layer 105 is placed in atmosphere is longer, extinction coefficient (K) and refraction coefficient (N) excursion of titanium nitride layer 105 are larger, in a lithographic process, when forming the first opening 10 in photoresist layer 106, because the extinction coefficient (K) of titanium nitride layer 105 and refraction coefficient (N) there occurs change, under same conditions of exposure, the light that exposure bench produces makes the characteristic of photoresist in photoresist layer 106 change, reflection and the absorption of unnecessary light is had on the surface of titanium nitride layer 105, the characteristic of more or less photoresist is changed, during subsequently through development formation the first opening 10, make the characteristic size of the first opening 10 excessive or too small, offset criteria value, affect the characteristic size of the second opening 20 and the etching of alternative gate 103 of follow-up formation, and be unfavorable for the control of the characteristic size of photoetching process stage first opening 10.
For solving the problem, inventor proposes a kind of formation method of metal gates, comprising: provide Semiconductor substrate, and described Semiconductor substrate is formed with alternative gate; Form dielectric layer on the semiconductor substrate, described dielectric layer surface is concordant with alternative gate surface; Titanium nitride layer is formed at dielectric layer and alternative gate surface; Oxidation processes is carried out to described titanium nitride layer, forms titanium dioxide layer on titanium nitride layer surface; Titanium dioxide layer is formed patterned photoresist layer, and described patterned photoresist layer has the first opening of corresponding alternative gate; With described patterned photoresist layer for mask, etch titanium dioxide layer and titanium nitride layer successively, form the second opening exposing alternative gate surface; With described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, form groove, in groove, fill full metal, form metal gates.Said method, before formation photoresist layer, oxidation processes is carried out to titanium nitride layer and forms the stable titanium dioxide layer of one deck, titanium nitride layer is made to have stable extinction coefficient (K) and refraction coefficient (N), when forming the first opening in photoresist layer, the characteristic size of the first opening keeps stable.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
With reference to the schematic flow sheet that figure 5, Fig. 5 is embodiment of the present invention method for forming metallic grid, comprising:
Step S201, Semiconductor substrate is provided, described Semiconductor substrate is formed with alternative gate structure, described alternative gate structure comprises the gate dielectric layer being positioned at semiconductor substrate surface and the alternative gate be positioned on gate dielectric layer, and described alternative gate structure side wall is formed with etching stop layer with surface and semiconductor substrate surface;
Step S202, forms layer of dielectric material, layer of dielectric material described in cmp and etching stop layer on etching stop layer surface, and with alternative gate surface for stop-layer, form dielectric layer, the surface of dielectric layer is concordant with alternative gate surface;
Step S203, forms titanium nitride layer on dielectric layer, etching stop layer, alternative gate surface;
Step S204, carries out oxidation processes to described titanium nitride layer, forms titanium dioxide layer on titanium nitride layer surface;
Step S205, form patterned photoresist layer on titanium dioxide layer surface, described patterned photoresist layer has the first opening of corresponding alternative gate;
Step S206, with described patterned photoresist layer for mask, etches titanium dioxide layer and titanium nitride layer successively, forms the second opening exposing alternative gate surface;
Step S207, with described patterned photoresist layer and titanium nitride layer for mask, removes described alternative gate, forms groove; Remove described patterned photoresist layer, titanium dioxide layer and titanium nitride layer; Form the metal level covering described groove, etching barrier layer, dielectric layer surface; Metal level described in cmp take dielectric layer surface as stop-layer, forms metal gates.
Fig. 6 ~ Figure 13 is the cross-sectional view of embodiment of the present invention metal gates forming process.
With reference to figure 6, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 is formed with alternative gate structure 30, described alternative gate structure 30 comprises the gate dielectric layer 303 being positioned at Semiconductor substrate 300 surface and the alternative gate 302 be positioned on gate dielectric layer 303, and described alternative gate structure 30 sidewall is formed with etching stop layer 304 with surface and Semiconductor substrate 300 surface.
Described Semiconductor substrate 300 is silicon substrate, silicon-Germanium substrate, germanium substrate one wherein, and described Semiconductor substrate 300 surface can also form some epitaxial loayers or strained silicon layer to improve the electric property of semiconductor device.Described Semiconductor substrate 300 can also inject certain Doped ions to change electrical parameter according to design requirement.Fleet plough groove isolation structure (not shown) is also formed in described Semiconductor substrate 300, described fleet plough groove isolation structure is for isolating different transistors, prevent electricity between different crystal pipe from connecting, the material of described fleet plough groove isolation structure can be silica, silicon nitride, silicon oxynitride wherein one or more.
The material of described alternative gate 302 is polysilicon, and alternative gate 302 is follow-up for the formation of metal gates after removal, and the described metal gates formed in the embodiment of the present invention also can be able to be the metal gates of PMOS transistor for the metal gates of nmos pass transistor.
The material of described gate dielectric layer 303 is silica, silicon oxynitride, and the material of described gate dielectric layer 303 also can be hafnium oxide (HfO
2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide tantalum (HfTaO), hafnium oxide titanium (HfTiO), the contour K dielectric material of hafnium oxide zirconium (HfZrO).Described gate dielectric layer 303 is the single layer structure of high K dielectric material, and described gate dielectric layer 303 also can be the double-decker of silica or silicon oxynitride and high K dielectric material.
The sidewall of described alternative gate structure 30 is also formed with side wall (not shown), and described side wall comprises offset side wall and is positioned at the master wall on offset side wall surface, follow-up before formation etching stop layer, need remove the master wall on offset side wall surface.
Also be formed in described Semiconductor substrate 300 with alternative gate structure 30 and offset side wall for mask, adopt the light doping section (not shown) of ion implantation technology formation in the Semiconductor substrate 300 of alternative gate structure 30 and offset side wall both sides, and with alternative gate structure 30 and master wall for mask, adopt the heavily doped region (not shown) of ion implantation technology formation in the Semiconductor substrate 300 of alternative gate structure 30 and master wall both sides, the degree of depth of described heavily doped region is greater than the degree of depth of light doping section, the source/drain region of heavily doped region and light doping section transistor formed.
Described etching stop layer 304 (CESL, contact etch stop layer) is stressor layers, in order to the channel region stress application at transistor, improves the mobility of channel region charge carrier, improves the performance of transistor.The material of described etching stop layer 304 is compression silicon nitride (compressive SiN) or tension stress silicon nitride (tensile SiN), when metal gates to be formed is the metal gates of nmos pass transistor, the material of described etching stop layer 303 is the silicon nitride of tension stress; When metal gates to be formed is the metal gates of PMOS transistor, the material of described etching stop layer 304 is the silicon nitride of compression.
The technique forming described etching stop layer 304 is chemical vapor deposition method (CVD), before formation etching stop layer 304, also comprise step: the master wall removing offset side wall surface, to improve the stress that etching stop layer 304 is applied to channel region.
With reference to figure 7, form layer of dielectric material (not shown) on etching stop layer 304 surface, layer of dielectric material described in cmp and etching stop layer 304, with alternative gate 302 surface for stop-layer, form dielectric layer 305, the surface of dielectric layer 305 is concordant with alternative gate 302 surface.
With reference to figure 8, form titanium nitride layer 306 on dielectric layer 305, etching stop layer 304, alternative gate 302 surface.
The formation process of described titanium nitride layer 306 is physical vapour deposition (PVD), and the thickness of described titanium nitride layer 306 is 20 dust ~ 200 dusts.
Separator between the photoresist layer of described titanium nitride layer 306 grid 302 and follow-up formation as an alternative, prevent photoresist layer from contacting with the direct of polysilicon alternative gate, cause the residual of photoresist on polysilicon alternative gate surface, affect the removal of follow-up polysilicon alternative gate.
Described titanium nitride layer 306 also can be used as hard mask layer during follow-up removal alternative gate 302.
With reference to figure 9, oxidation processes is carried out to described titanium nitride layer 306, form titanium dioxide layer 307 on titanium nitride layer 306 surface.
Once oxidation process is carried out to described titanium nitride layer 306, the titanium on titanium nitride layer 306 surface and oxygen reaction is made to form the stable titanium dioxide layer of one deck 307, titanium dioxide layer 307 makes titanium nitride layer 306 and air isolated, prevent titanium nitride layer 306 from exposing and oxidation reaction slowly occurs in atmosphere, the extinction coefficient (K) on titanium nitride layer 306 surface and refraction coefficient (N) is made to keep stable, follow-up when forming the first opening in photoresist layer, because the extinction coefficient (K) on titanium nitride layer 306 surface and refraction coefficient (N) keep stable, with under existing identical conditions of exposure, the impact of titanium nitride layer 306 on the light that exposure bench produces is constant, the characteristic size forming the first opening in photoresist layer is made to keep stable, make the characteristic size of the first opening equal with standard value or differ a steady state value.When the characteristic size of the first opening differs a steady state value with standard value, the characteristic size of the first opening can be made equal with standard value by the correction of many exposure parameters.The characteristic size of the first opening keeps stable, facilitates the control of the characteristic size of photoetching process stage first opening; The characteristic size of the first opening keeps stable, the characteristic size of follow-up the second opening formed for mask etching titanium nitride layer 306 with patterned photoresist layer is made to keep stable, when being mask etching alternative gate with patterned photoresist layer and titanium nitride layer 306, the etching of alternative gate can not be affected.
Be cineration technics or furnace process to the described oxidation processes to titanium nitride layer 306.
The gas that described cineration technics adopts is oxygen, and reaction temperature is 40 degrees Celsius ~ 250 degrees Celsius, and oxygen flow is 10sccm ~ 1000sccm.
The gas that described furnace process adopts is oxygen, and reaction temperature is 400 degrees Celsius ~ 800 degrees Celsius, and oxygen flow is 10sccm ~ 30sccm.
With reference to Figure 10, form patterned photoresist layer 308 on titanium dioxide layer 307 surface, described patterned photoresist layer has the first opening 309 of corresponding alternative gate.
Because the titanium on titanium nitride layer 306 surface and oxygen reaction define the stable titanium dioxide layer of one deck 307, titanium dioxide layer 307 makes titanium nitride layer 306 and air isolated, prevent titanium nitride layer 306 from exposing and oxidation reaction slowly occurs in atmosphere, the extinction coefficient (K) on titanium nitride layer 306 surface and refraction coefficient (N) is made to keep stable, photoresist layer (not shown) is formed on titanium dioxide layer 307 surface, when described photoresist layer is exposed, because the extinction coefficient (K) on titanium nitride layer 306 surface and refraction coefficient (N) keep stable, with under existing identical conditions of exposure, the absorption of light that titanium nitride layer 306 produces exposure bench and the impact of reflection remain unchanged, the characteristic size forming the first opening 309 in photoresist layer is made to keep stable, the characteristic size of the first opening 309 is equal with standard value or differ a steady state value.When the characteristic size of the first opening 309 differs a steady state value with standard value, can by making the characteristic size of the first opening 309 equal with standard value to the correction of existing exposure parameter.The characteristic size of the first opening 309 keeps stable, facilitates the control of the characteristic size of photoetching process stage first opening 309; The characteristic size of the first opening 309 keeps stable, the follow-up characteristic size being the second opening that mask etching titanium nitride layer 306 is formed with patterned photoresist layer 308 is made to keep stable, when being mask etching alternative gate with patterned photoresist layer and titanium nitride layer 306, the etching of alternative gate can not be affected.
With reference to Figure 11, with described patterned photoresist 308 for mask, etch titanium dioxide layer 307 and titanium nitride layer 306 successively, form the second opening 310 exposing alternative gate 302 surface.
Described etching titanium dioxide layer 307 and titanium nitride layer 306 adopt dry etching or wet etching, described etching titanium dioxide layer 307 and titanium nitride layer 306 can a step etching also can step etching.
With reference to Figure 12, with described patterned photoresist layer 308 and titanium nitride layer 306 for mask, remove described alternative gate 302 (shown in Figure 11), form groove 311.
Removing described alternative gate 302 is dry etch process or wet-etching technology.
With reference to Figure 13, remove patterned photoresist layer 308, titanium dioxide layer 307 and titanium nitride layer 306 shown in described Figure 12; Form the metal level (not shown) covering described groove 311 (shown in Figure 12), etching barrier layer 304, dielectric layer surface 305; Metal level described in cmp, with dielectric layer 305 surface for stop-layer, forms metal gates 312.
The material of described metal gates 312 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Before formation metal gates 312, also comprise step: in sidewall and the bottom formation diffusion impervious layer (not shown) of groove 311.Described diffusion impervious layer is diffused in dielectric layer 305 and gate dielectric layer 303 for preventing the metal ion in metal gates 312, affects the stability of device.The material of described diffusion impervious layer is TiN or TaN.
In other embodiments of the invention, described diffusion impervious layer surface is formed with functional layer, for regulating the work function of transistor.
The material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
To sum up, the formation method of the metal gates that the embodiment of the present invention provides, before titanium nitride layer surface forms photoresist layer, oxidation processes is carried out to described titanium nitride layer, the titanium on titanium nitride layer surface and oxygen reaction is made to form the stable titanium dioxide layer of one deck, titanium dioxide layer make titanium nitride layer and air isolated, prevent titanium nitride layer from exposing and oxidation reaction slowly occurs in atmosphere, the extinction coefficient (K) on titanium nitride layer surface and refraction coefficient (N) is made to keep stable, follow-up when forming the first opening in photoresist layer, because the extinction coefficient (K) on titanium nitride layer surface and refraction coefficient (N) keep stable, with under identical conditions of exposure, the impact of titanium nitride layer on the light that exposure bench produces is constant, the characteristic size forming the first opening in photoresist layer is made to keep stable, facilitate the control of the characteristic size of photoetching process stage first opening, the characteristic size of the first opening keeps stable, the characteristic size of follow-up the second opening formed for mask etching titanium nitride layer with patterned photoresist layer is made to keep stable, during with patterned photoresist layer and titanium nitride layer for mask etching alternative gate, the etching of alternative gate can not be affected.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (17)
1. a formation method for metal gates, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate is formed with alternative gate;
Form dielectric layer on the semiconductor substrate, described dielectric layer surface is concordant with alternative gate surface;
Titanium nitride layer is formed at dielectric layer and alternative gate surface;
Oxidation processes is carried out to described titanium nitride layer, forms titanium dioxide layer on titanium nitride layer surface;
Titanium dioxide layer is formed patterned photoresist layer, and described patterned photoresist layer has the first opening of corresponding alternative gate;
With described patterned photoresist layer for mask, etch titanium dioxide layer and titanium nitride layer successively, form the second opening exposing alternative gate surface;
With described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, form groove, in groove, fill full metal, form metal gates.
2. the formation method of metal gates as claimed in claim 1, it is characterized in that, be cineration technics or furnace process to the oxidation processes of titanium nitride layer.
3. the formation method of metal gates as claimed in claim 2, is characterized in that, the gas that described cineration technics adopts is oxygen, and reaction temperature is 40 degrees Celsius ~ 250 degrees Celsius, and oxygen flow is 10sccm ~ 1000sccm.
4. the formation method of metal gates as claimed in claim 2, is characterized in that, the gas that described furnace process adopts is oxygen, and reaction temperature is 400 degrees Celsius ~ 800 degrees Celsius, and oxygen flow is 10sccm ~ 30sccm.
5. the formation method of metal gates as claimed in claim 1, it is characterized in that, the thickness of described titanium nitride layer is 20 dust ~ 200 dusts.
6. the formation method of metal gates as claimed in claim 1, it is characterized in that, the formation process of described titanium nitride layer is physical vapour deposition (PVD).
7. the formation method of metal gates as claimed in claim 1, is characterized in that, described alternative gate surface and sidewall and semiconductor substrate surface are formed with etching stop layer.
8. the formation method of metal gates as claimed in claim 7, it is characterized in that, the material of described etching stop layer is the silicon nitride of tension stress or the silicon nitride of compression.
9. the formation method of metal gates as claimed in claim 7, it is characterized in that, the forming process of described dielectric layer is: form layer of dielectric material on etching stop layer surface; Layer of dielectric material described in cmp and etching stop layer, with alternative gate surface for stop-layer, form dielectric layer, the surface of dielectric layer is concordant with alternative gate surface.
10. the formation method of metal gates as claimed in claim 9, it is characterized in that, the forming process of described metal gates is: with described patterned photoresist layer and titanium nitride layer for mask, remove described alternative gate, form groove; Remove described patterned photoresist layer, titanium dioxide layer and titanium nitride layer; Form the metal level covering groove, etching stop layer, dielectric layer surface; Metal level described in cmp take dielectric layer surface as stop-layer, forms metal gates.
The formation method of 11. metal gates as claimed in claim 1, is characterized in that, be also formed with gate dielectric layer between described alternative gate and Semiconductor substrate.
The formation method of 12. metal gates as claimed in claim 11, is characterized in that, the material of described gate dielectric layer is silica, silicon oxynitride or high K dielectric material.
The formation method of 13. metal gates as claimed in claim 1, is characterized in that, the material of described metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
The formation method of 14. metal gates as claimed in claim 1, is characterized in that, before formation metal gates, also comprises step: at sidewall and the bottom formation diffusion impervious layer of groove.
The formation method of 15. metal gates as claimed in claim 14, is characterized in that, the material of described diffusion impervious layer is TiN or TaN.
The formation method of 16. metal gates as claimed in claim 14, it is characterized in that, described diffusion impervious layer surface is formed with functional layer.
The formation method of 17. metal gates as claimed in claim 16, is characterized in that, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
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| CN104752185B (en) * | 2013-12-31 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of metal gates |
| CN105826176B (en) * | 2015-01-06 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11532698B2 (en) * | 2019-09-11 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diffusion barrier layer in top electrode to increase break down voltage |
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