CN103165611B - Read only memory and preparation method thereof - Google Patents
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- CN103165611B CN103165611B CN201110422511.9A CN201110422511A CN103165611B CN 103165611 B CN103165611 B CN 103165611B CN 201110422511 A CN201110422511 A CN 201110422511A CN 103165611 B CN103165611 B CN 103165611B
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- 238000002360 preparation method Methods 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 8
- 230000000875 corresponding Effects 0.000 claims description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Abstract
A kind of read only memory, comprises the memory element of several array arrangements.Read only memory comprises the memory element of two kinds of different structures；Two kinds of memory element are respectively the first metal-oxide-semiconductor and the second metal-oxide-semiconductor；Source electrode and the drain electrode of the first metal-oxide-semiconductor are equipped with lightly doped drain, the source electrode of the second metal-oxide-semiconductor and drain electrode one of them there is lightly doped drain or all without lightly doped drain.Therefore, the drive current differences of the metal-oxide-semiconductor output of both different structures not can be used for distinguishing " 0 " or " 1 " signal of ROM storage unit storage.And the making of the memory element of read only memory and conventional MOS pipe processing technology, the mask plate that traditional masks read only memory is extra can be saved, shorten fabrication cycle and the cost of read only memory.
Description
[technical field]
The present invention relates to semiconductor memory, especially relate to a kind of read only memory and preparation method thereof.
[background technology]
Read only memory (ROM, read only memory) is the one of semiconductor memory.As its name suggests,
Read only memory may only read its information being stored in, and cannot wipe the information being stored in or weight
Newly written.ROM stores data stabilization, even if in the case of not having power supply to support, the data deposited are the most not
Can lose.
Read only memory comprises several and is arranged in array, and is used for storing up stored memory element.At present, city
Read only memory relatively conventional on face is mask ROM.Need when this mask ROM makes
Extra mask plate forms the memory element for storing information.Utilize the mask plate ion implanting that this is extra
Form the memory element of two kinds of different cut-in voltages.Read information time, utilize between two kinds of cut-in voltages it
Between operation voltage read location information.Such as, during reading, it is less than the cut-in voltage of operation voltage
Memory element may turn on the corresponding signal of telecommunication and obtained；Memory element higher than the cut-in voltage of operation voltage
Would be at closed mode, do not have the signal of telecommunication to obtain.Therefore, the information of mask ROM storage uses
Said method just can read effectively.
But, this kind of mask ROM needs to use extra mask plate and forms two kinds of different unlatchings
The memory element of voltage, adds the cost of manufacture of read only memory.
[summary of the invention]
Based on this, the present invention provides a kind of read only memory and preparation method thereof, can save traditional masks read-only
Mask plate extra in memorizer, shortens fabrication cycle and the cost of manufacture of read only memory.
A kind of read only memory, comprises the memory element of several array arrangements.Read only memory comprises two kinds
The memory element of different structure.Two kinds of memory element are respectively the first metal-oxide-semiconductor and the second metal-oxide-semiconductor.First
Source electrode and the drain electrode of metal-oxide-semiconductor are equipped with lightly doped drain, the source electrode of the second metal-oxide-semiconductor and drain electrode one of them
There is lightly doped drain or all without lightly doped drain.
Further, it is as a example by p-type memory element by the memory element of two kinds of different structures, a MOS
The source electrode of pipe and drain electrode are equipped with one of them tool of p-type lightly doped drain, the source electrode of the second metal-oxide-semiconductor and drain electrode
There is p-type lightly doped drain or all without p-type lightly doped drain.
Further, as a example by the memory element of two kinds of different structures is for N-type memory element, a MOS
The source electrode of pipe and drain electrode are equipped with one of them tool of N-type lightly doped drain, the source electrode of the second metal-oxide-semiconductor and drain electrode
There is N-type lightly doped drain or all without N-type lightly doped drain.
The manufacture method of a kind of above-mentioned read only memory, comprises the following steps:
Step 1: silicon substrate is provided, concurrently forms the active area of the memory element of two kinds of different structures at silicon substrate；
Step 2: form grid oxygen medium and the control gate of two kinds of different structure memory element in surfaces of active regions；
Step 3: form drain electrode and the respective lightly doped drain of source electrode in the both sides of the first metal-oxide-semiconductor control gate,
Form lightly doped drain or the lightly doped drain of source electrode of drain electrode in the side of the second metal-oxide-semiconductor control gate simultaneously；
Or drain electrode and the respective lightly doped drain of source electrode is only formed in the both sides of the first metal-oxide-semiconductor control gate；
Step 4: form sidewall in the control gate both sides of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor；
Step 5: concurrently form the first metal-oxide-semiconductor drain electrode in the control gate both sides with sidewall and source electrode is respective
Ion doped region and the second metal-oxide-semiconductor drain and the respective ion doped region of source electrode.
Further, step 3 include following step by step:
Step 31: coat photoresistance in the surface of silicon being formed with control gate；
Step 32: remove in two kinds of different structure memory element and will form the light on the region of lightly doped drain
Resistance part is divided；
Step 33: carry out ion implanting to the region eliminating photoresistance, forms lightly doped drain；
Step 34: remain in the photoresistance of surface of silicon after removing ion implanting.
Further, step 32 comprises the following steps:
There is provided lightly doped drain mask plate, by the first metal-oxide-semiconductor drain electrode and lightly doped drain and second of source electrode
The lightly doped drain of metal-oxide-semiconductor drain electrode or source electrode is defined on the mask plate of lightly doped drain；Or only by first
The lightly doped drain of metal-oxide-semiconductor drain electrode and source electrode is defined on the mask plate of lightly doped drain；
By the mask plate of lightly doped drain, exposure is formed with the photoresistance of the surface of silicon of control gate, development
Remove the light resistance part in the lightly doped drain region that surface of silicon corresponds to define on the mask plate of lightly doped drain
Point.
Above-mentioned read only memory, utilizes the second metal-oxide-semiconductor drain electrode to have relative to the first metal-oxide-semiconductor with source electrode and gently mixes
The drain electrode in miscellaneous drain region and source electrode only have one to have lightly doped drain or both of which non-impurity-doped drain region so that two
Kind metal-oxide-semiconductor is when the information of reading, and the difference between electric current can be used for judging that its " 0 " or " 1 " stored is believed
Breath.In the manufacture method of read only memory, directly define on the mask plate of lightly doped drain and to be formed
Lightly doped drain zone position, it is not necessary to extra mask plate, therefore can save the read-only storage of traditional masks
The mask plate that device is extra.
[accompanying drawing explanation]
Fig. 1 is the first metal-oxide-semiconductor structural representation in read only memory embodiment of the present invention；
Fig. 2 is the second metal-oxide-semiconductor structural representation in read only memory embodiment of the present invention；
Fig. 3 is the second metal-oxide-semiconductor another kind structural representation in read only memory embodiment of the present invention；
Fig. 4 is the driving current diagram of three shown in Fig. 1, Fig. 2 and Fig. 3 kind metal-oxide-semiconductor output；
Fig. 5 is ROM storage unit part domain schematic diagram in the embodiment of the present invention.
[detailed description of the invention]
The present embodiment proposes read only memory and preparation method thereof, can save traditional masks read only memory volume
Outer mask plate, shortens fabrication cycle and the cost of read only memory.
The read only memory of the present embodiment, comprises the memory element of several array arrangements.Read only memory bag
Memory element containing two kinds of different structures.Two kinds of memory element be respectively the first metal-oxide-semiconductor 101 shown in Fig. 1,
The second metal-oxide-semiconductor 102 or 102 shown in Fig. 2 or Fig. 3 '.The source electrode 14 of the first metal-oxide-semiconductor 101 and leakage
Pole 16 is equipped with lightly doped drain 12 (LDD, Lightly Doped Drain).2nd MOS as shown in Figure 2
The source electrode 18 of pipe 102 and drain electrode 20 only drain and 20 is provided with lightly doped drain 12, or only source electrode 18 sets
There is lightly doped drain 12.In a word, the source electrode 18 of the second metal-oxide-semiconductor 102 or drain electrode one of 20 have and gently mix
Miscellaneous drain region 12.Or as it is shown on figure 3, the second metal-oxide-semiconductor 102 ' drain electrode 20 ' and source electrode 18 ' are all
Without lightly doped drain.
In memory element, the first metal-oxide-semiconductor 101 is compared with the second metal-oxide-semiconductor 102, drain electrode 16 and source electrode 14
It is equipped with lightly doped drain 12, and the second metal-oxide-semiconductor 102 source electrode 18 and drain electrode 20 only one are provided with and gently mix
Miscellaneous drain region 12.Therefore when the first metal-oxide-semiconductor 101 and the second metal-oxide-semiconductor 102, identical voltage conditions is loaded
Time, the electric current Id amplitude that drives of output has bigger difference.The source electrode 18 of the second metal-oxide-semiconductor 102 and leakage
Pole 20 only one of both has lightly doped drain 12, and therefore the second metal-oxide-semiconductor 102 length of effective channel is big
In the length of effective channel of the first metal-oxide-semiconductor 101, thus the driving electric current Id of the second metal-oxide-semiconductor 102 output
Then less than the driving electric current Id of the first metal-oxide-semiconductor 101 output.In like manner, the second metal-oxide-semiconductor 102 ' shown in Fig. 3
Owing to drain electrode 20 ' and source electrode 18 ' both of which are without lightly doped drain, time the most in working order, the 2nd MOS
Pipe 102 ' length of effective channel more than the raceway groove effective length of the second metal-oxide-semiconductor 102 shown in Fig. 2, thus the
The driving electric current of two metal-oxide-semiconductor 102 ' outputs is less than the driving electric current of the output of the second metal-oxide-semiconductor 102.
Referring to Fig. 4, shown in the block curve corresponding diagram 3 in Fig. 4, the second metal-oxide-semiconductor 102 ' output drives
Streaming current, the driving electric current of the second metal-oxide-semiconductor 102 output, dashed curve shown in chain-dotted line curve corresponding diagram 2
The then driving electric current of the first metal-oxide-semiconductor 101 output shown in corresponding diagram 1.Therefore, in memory element second
No matter metal-oxide-semiconductor uses the structure shown in Fig. 2 or the structure shown in Fig. 3, and read only memory can rely on
The difference driving electric current of two metal-oxide-semiconductors and the output of the first metal-oxide-semiconductor comes discernible signal " 0 " or " 1 ".Second
Metal-oxide-semiconductor is preferably chosen the structure shown in Fig. 3, due to the second metal-oxide-semiconductor 102 ' and first shown in Fig. 3
The driving electric current of metal-oxide-semiconductor output is maximum, and more conducively information read device understands that resolution read only memory is deposited
The signal " 0 " of storage or " 1 ".
As a example by p-type memory element, the memory element of two kinds of different structures is p-type memory element.First
The source electrode of metal-oxide-semiconductor and drain electrode are equipped with p-type lightly doped drain (PLDD), the source electrode of the second metal-oxide-semiconductor and
Draining, one of them has p-type lightly doped drain or all without p-type lightly doped drain.
As a example by N-type memory element, the memory element of two kinds of different structures is N-type memory element.First
The source electrode of metal-oxide-semiconductor and drain electrode are equipped with N-type lightly doped drain, the source electrode of the second metal-oxide-semiconductor and drain electrode wherein
One of there is N-type lightly doped drain or all without N-type lightly doped drain.
The manufacture method of a kind of above-mentioned read only memory embodiment, comprises the following steps:
Step 1: silicon substrate is provided, concurrently forms the active area of the memory element of two kinds of different structures at silicon substrate.
Refer to Fig. 1 to Fig. 3 and Fig. 5, form first shown in Fig. 1 and Fig. 2 or Fig. 3 the most on a silicon substrate
The active area 10 of metal-oxide-semiconductor and the second metal-oxide-semiconductor.Active area 10 shown in Fig. 5 is read-only on active area mask plate
Memory Storage Unit part domain schematic diagram.
Step 2: form grid oxygen medium and the control gate of two kinds of different structure memory element on active area 10 surface.
Refer to Fig. 1 to Fig. 3 and Fig. 5, concurrently form the grid of the metal-oxide-semiconductor stacked gradually on active area 10 surface
Oxygen medium 17 and control gate 11.
Step 3: refer to Fig. 1 and Fig. 2, forms drain electrode in the both sides of the first metal-oxide-semiconductor 101 control gate 11
16 and the respective lightly doped drain of source electrode 14 12, simultaneously in the side of the second metal-oxide-semiconductor 102 control gate 11
Form lightly doped drain 12 or the lightly doped drain 12 of source electrode 18 of drain electrode 20.Or, refer to Fig. 1 and
Fig. 3 only forms drain electrode 20 in the both sides of the first metal-oxide-semiconductor 101 control gate 11 and source electrode 18 is respective gently mixes
Miscellaneous drain region 12, control gate 11 both sides of the second metal-oxide-semiconductor 102 ' not necessarily form and district are lightly doped.
Step 3 specifically include following step by step:
Step 31: coat photoresistance in the surface of silicon being formed with control gate 11；
Step 32: remove in two kinds of different structure memory element and will form the light on the region of lightly doped drain
Resistance part is divided, in order to subsequent step carries out ion implanting；
Step 33: carry out ion implanting to the region eliminating photoresistance, forms lightly doped drain；
Step 34: remain in the photoresistance of surface of silicon after removing ion implanting.
Wherein, step 32 comprises the following steps:
Thering is provided lightly doped drain mask plate, drain 16 and the lightly doped drain of source electrode 14 by the first metal-oxide-semiconductor 101
District 12 and the second metal-oxide-semiconductor 102 drain 20 or the lightly doped drain 12 of source electrode 18 be defined on lightly doped drain
On mask plate.Or, select preferred version: the only first metal-oxide-semiconductor 101 needs to form lightly doped drain 12.
Therefore, only the first metal-oxide-semiconductor 101 is drained 20 and the lightly doped drain 12 of source electrode 18 be defined on and be lightly doped
On the mask plate of drain region.If the region 20 of Fig. 5 example is two Fig. 1 institutes defined on the mask plate of lightly doped drain
The first metal-oxide-semiconductor 101 shown drains the lightly doped drain 12 of 16 and source electrode 14.It is the most read-only that Fig. 5 enumerates
Memory element part domain schematic diagram in memorizer.It practice, read only memory contains several such as Fig. 1
The second metal-oxide-semiconductor 102 ' shown in the first shown metal-oxide-semiconductor 101 and some Fig. 3.Therefore at lightly doped drain
On the mask plate in district, actually definition has several regions 20 to drain corresponding to several first metal-oxide-semiconductors 101
16 and the lightly doped drain 12 of source electrode 14.
By the mask plate of lightly doped drain, exposure is formed with the photoresistance of the surface of silicon of control gate 11, aobvious
Shadow removes the light in the lightly doped drain region 20 that surface of silicon corresponds to define on the mask plate of lightly doped drain
Resistance part is divided.
Wherein, the ionic type that step 33 is injected is based in read only memory depending on the type of memory element.
If memory element is p-type, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are then PMOS, lightly doped drain
Corresponding to p-type lightly doped drain, the ionic type that step 33 is injected is then p-type.If memory element is N-type,
First metal-oxide-semiconductor and the second metal-oxide-semiconductor are then NMOS tube, and lightly doped drain corresponds to N-type and is lightly doped
Drain region, the ionic type that step 33 is injected is then N-type.
Step 4: form sidewall in control gate 11 both sides of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor.Refer to
Fig. 1, Fig. 2 or Fig. 3, the sidewall 13 of control gate 11 both sides of formation can be by realization side exemplified below
Method is formed: after completing lightly doped drain ion implanting, at control gate 11 superficial growth insulating medium layer, so
After perform etching formed insulating dielectric materials sidewall 13.
Step 5: concurrently form the first metal-oxide-semiconductor shown in Fig. 1 in control gate 11 both sides with sidewall 13
101 drain electrodes 16 and the respective ion doped region of source electrode 14 and the second metal-oxide-semiconductor 102 shown in Fig. 2 or Fig. 3
Or 102 ' drain electrodes 20 or 20 ' and source electrode 18 or 18 ' respective ion doped region.Metal-oxide-semiconductor drain electrode and source
The ion doped region of pole is mainly completed by following steps: at the silicon substrate table forming the control gate with sidewall
Face coating photoresistance, is exposed by drain electrode and source mask plate, removes the photoresistance on drain electrode and source region.Please
Refering to Fig. 5, dotted line frame 21 is drain electrode and the ion doped region of source electrode of signal on drain electrode and source mask plate.
Then carry out the ion implanting of drain electrode and source electrode, form the ion doped region of drain electrode and source electrode, i.e. drain electrode and source
Pole.Finally remove ion implanting and remain in the photoresistance of surface of silicon.
Therefore, it can be seen that relatively conventional read only memory from the manufacture method of whole read only memory,
Whole process is without extra mask plate, and the processing technology of conventional MOS pipe is compatible.Therefore, the present embodiment
The fabrication cycle of read only memory can shorten, its cost also decreases.
Above example only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but
Therefore the restriction to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that, for this area
For those of ordinary skill, without departing from the inventive concept of the premise, it is also possible to make some deformation and change
Entering, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended power
Profit requires to be as the criterion.
Claims (6)
1. a read only memory, comprises the memory element of several array arrangements, it is characterised in that described read only memory comprises the memory element of two kinds of different structures；The two memory element is respectively the first metal-oxide-semiconductor and the second metal-oxide-semiconductor；Source electrode and the drain electrode of described first metal-oxide-semiconductor are equipped with lightly doped drain, the source electrode of described second metal-oxide-semiconductor and drain electrode one of them there is lightly doped drain or all without lightly doped drain, make the length of effective channel of described first metal-oxide-semiconductor be less than the length of effective channel of the second metal-oxide-semiconductor；Described read only memory relies on the difference driving electric current of the second metal-oxide-semiconductor and the output of the first metal-oxide-semiconductor to come discernible signal " 0 " or " 1 ".
Read only memory the most according to claim 1, it is characterized in that, the memory element of the two different structure is p-type memory element, the source electrode of described first metal-oxide-semiconductor and drain electrode are equipped with p-type lightly doped drain, the source electrode of described second metal-oxide-semiconductor and drain electrode, and one of them has p-type lightly doped drain or all without p-type lightly doped drain.
Read only memory the most according to claim 1, it is characterized in that, the memory element of the two different structure is N-type memory element, the source electrode of described first metal-oxide-semiconductor and drain electrode are equipped with N-type lightly doped drain, the source electrode of described second metal-oxide-semiconductor and drain electrode, and one of them has N-type lightly doped drain or all without N-type lightly doped drain.
4. the manufacture method of a read only memory as claimed in claim 1, it is characterised in that comprise the following steps:
Step 1: silicon substrate is provided, concurrently forms the active area of the memory element of the two different structure at described silicon substrate；
Step 2: form grid oxygen medium and the control gate of the two different structure memory element in described surfaces of active regions；
Step 3: form drain electrode and the respective lightly doped drain of source electrode in the both sides of described first metal-oxide-semiconductor control gate, forms lightly doped drain or the lightly doped drain of source electrode of drain electrode simultaneously in the side of the second metal-oxide-semiconductor control gate；Or only form drain electrode and the respective lightly doped drain of source electrode in the both sides of the first metal-oxide-semiconductor control gate, make the length of effective channel length of effective channel less than the second metal-oxide-semiconductor of described first metal-oxide-semiconductor；
Step 4: form sidewall in the control gate both sides of described first metal-oxide-semiconductor and the second metal-oxide-semiconductor；
Step 5: concurrently form described first metal-oxide-semiconductor drain electrode and the respective ion doped region of source electrode and the drain electrode of the second metal-oxide-semiconductor and the respective ion doped region of source electrode in the control gate both sides with described sidewall.
The manufacture method of read only memory the most according to claim 4, it is characterised in that described step 3 include following step by step:
Step 31: coat photoresistance in the surface of silicon being formed with control gate；
Step 32: remove the photoresistance part on the region that will form described lightly doped drain in the two different structure memory element；
Step 33: carry out ion implanting to the described region eliminating photoresistance, forms lightly doped drain；
Step 34: remain in the photoresistance of described surface of silicon after removing ion implanting.
The manufacture method of read only memory the most according to claim 5, it is characterised in that remove the photoresistance part that will be formed on the region of described lightly doped drain and comprise the following steps:
Lightly doped drain mask plate is provided, the lightly doped drain of described first metal-oxide-semiconductor drain electrode and the lightly doped drain of source electrode and described second metal-oxide-semiconductor drain electrode or source electrode is defined on the mask plate of described lightly doped drain；Or only the lightly doped drain of described first metal-oxide-semiconductor drain electrode and source electrode is defined on the mask plate of described lightly doped drain；
By the mask plate of described lightly doped drain, being formed with the photoresistance of the surface of silicon of control gate described in exposure, development removes described surface of silicon corresponding to the photoresistance part in the lightly doped drain region that defines on the mask plate of described lightly doped drain.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110422511.9A CN103165611B (en) | 2011-12-15 | Read only memory and preparation method thereof | |
| PCT/CN2012/084284 WO2013086912A1 (en) | 2011-12-15 | 2012-11-08 | Read only memory and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110422511.9A CN103165611B (en) | 2011-12-15 | Read only memory and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103165611A CN103165611A (en) | 2013-06-19 |
| CN103165611B true CN103165611B (en) | 2016-12-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4208780A (en) * | 1978-08-03 | 1980-06-24 | Rca Corporation | Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer |
| US6803283B1 (en) * | 2002-09-30 | 2004-10-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method to code flashROM using LDD and source/drain implant |
| CN1967879A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Operation mehtod of single-poly non-volatile memory device |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4208780A (en) * | 1978-08-03 | 1980-06-24 | Rca Corporation | Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer |
| US6803283B1 (en) * | 2002-09-30 | 2004-10-12 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method to code flashROM using LDD and source/drain implant |
| CN1967879A (en) * | 2005-11-17 | 2007-05-23 | 力旺电子股份有限公司 | Operation mehtod of single-poly non-volatile memory device |
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