CN103165602A - 防止半导体集成电路中等离子体导致的栅极介电层损害的天线单元设计 - Google Patents
防止半导体集成电路中等离子体导致的栅极介电层损害的天线单元设计 Download PDFInfo
- Publication number
- CN103165602A CN103165602A CN2012104774197A CN201210477419A CN103165602A CN 103165602 A CN103165602 A CN 103165602A CN 2012104774197 A CN2012104774197 A CN 2012104774197A CN 201210477419 A CN201210477419 A CN 201210477419A CN 103165602 A CN103165602 A CN 103165602A
- Authority
- CN
- China
- Prior art keywords
- coupled
- gate
- metal lead
- substrate
- lead wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 14
- 210000000080 chela (arthropods) Anatomy 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 108010022579 ATP dependent 26S protease Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
- H01L27/0811—MIS diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供了一种防止等离子体增强栅极介电层失效的天线单元。天线单元设计利用多晶硅引线作为伪晶体管的栅极。多晶硅引线可以是一组平行内嵌的多晶硅引线中的一条。伪晶体管包括通过金属引线直接地或者通过钳低单元间接地耦合至保持在Vss的衬底的栅极。栅极设置在源极和漏极连接在一起的连续源极/漏极掺杂区上方的介电层上方。二极管由半导体衬底形成,其中,二极管形成在半导体衬底中。源极/漏极区耦合至可以是输入引脚的另一条金属引线并耦合至有源晶体管栅极,以防止等离子体增强对有源晶体管的栅极介电层的损害。防止半导体集成电路中等离子体导致的栅极介电层损害的天线单元设计。
Description
技术领域
本发明涉及半导体器件及其制造方法。更具体地来说,本发明涉及防止等离子体导致的栅极介电层损害(也被称为天线效应(antenna effect))的天线单元。
背景技术
集成电路和其他半导体器件被形成为包括众多的耦合在一起并且耦合至各种其他部件的独立晶体管,以形成功能器件。如果任何一个晶体管失效,则可以破坏器件功能。在先进半导体器件制造和生产中,通常在用于形成几乎所有的集成电路和其他半导体器件的制造操作的序列中多次使用等离子体化学操作。等离子体操作包括等离子体蚀刻操作和等离子体沉积操作。等离子体汽相沉积PVD和等离子体增强化学汽相沉积PECVD仅代表多种等离子体沉积操作中的两个。
等离子体操作利用激发的离子并且这些离子常常以较高的偏差通常被引导至衬底表面。等离子体中的激发的、加速的离子可以导致损害先前形成的部件。反应离子蚀刻(RIE)操作和利用离子轰击的其他操作也可以损害现有部件而对现有部件造成的损害统称为等离子体导致的损害。
用于集成电路和其他半导体器件的高灵敏度晶体管通常包括定位在可以是氧化物或其他栅极介电材料的栅极介电层上方的多晶硅或金属栅极。等离子体导致的栅极介电层损害通常被称为天线效应,是损害晶体管栅极和晶体管栅极介电材料的效应,并且可以MOS集成电路制造期间潜在地导致成品率和可靠性问题。如果栅极介电层损害严重,可以破坏设备功能。
因此,期望和优选地提供消除或减轻任何等离子体导致的栅极介电层损害的结构。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供一种半导体结构,包括:至少一个有源晶体管,具有有源多晶硅栅极;金属引线,耦合至至少一个所述有源多晶硅栅极;以及二极管,通过伪晶体管将所述金属引线耦合至Vss,所述伪晶体管包括设置在栅极介电层上方的伪多晶硅晶体管栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方,所述二极管包括耦合至所述连续源极/漏极掺杂区的所述金属引线和耦合至所述Vss的所述伪多晶硅晶体管栅极。
在该半导体结构中,所述至少一个有源晶体管设置在半导体衬底上,所述衬底保持在所述Vss,并且所述伪多晶硅晶体管栅极耦合至所述衬底。
在该半导体结构中,所述伪多晶硅晶体管栅极通过其他金属引线耦合至所述衬底。
在该半导体结构中,所述伪多晶硅晶体管栅极通过钳低单元耦合至所述衬底。
在该半导体结构中,所述二极管包括PN结。
在该半导体结构中,所述连续源极/漏极掺杂区是N型区,所述衬底是P型衬底,并且所述二极管包括位于所述N型区和所述P型衬底之间的PN结。
在该半导体结构中,所述金属引线耦合至所述半导体器件的输入引脚。
在该半导体结构中,在所述半导体衬底上的天线单元中形成所述半导体结构,所述天线单元包括具有基本相同的长度并且延伸穿过所述天线单元的多条平行的多晶硅线,并且所述伪多晶硅晶体管栅极由一条所述多晶硅线形成。
在该半导体结构中,所述金属引线通过第一连接导电结构和第二连接导电结构耦合至所述连续源极/漏极掺杂区,其中,所述第一连接导电结构在所述伪多晶硅晶体管栅极的源极侧耦合至所述连续源极/漏极掺杂区,以及所述第二连接导电结构在所述伪多晶硅晶体管栅极的漏极侧耦合至所述连续源极/漏极掺杂区。
根据本发明的另一方面,提供了一种半导体结构,包括:至少一个有源晶体管,具有有源多晶硅栅极并形成在半导体衬底上;金属引线,耦合至至少一个所述有源多晶硅栅极;以及二极管,通过伪晶体管将所述金属引线耦合至所述半导体衬底,所述伪晶体管包括设置在栅极介电层上方的伪多晶硅晶体管栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方,所述二极管包括耦合至所述连续源极/漏极掺杂区的所述金属引线和耦合至所述半导体衬底的所述伪多晶硅晶体管栅极。
在该半导体结构中,所述半导体衬底保持在Vss。
在该半导体结构中,所述伪多晶硅晶体管栅极通过钳低单元耦合至所述衬底。
在该半导体结构中,所述连续源极/漏极掺杂区是第一杂质类型,所述半导体衬底是相反的掺杂杂质类型的材料,以及所述二极管包括位于所述连续源极/漏极掺杂区和所述半导体衬底之间的PN结。
在该半导体结构中,所述第一掺杂杂质类型包括N型,而所述相反的掺杂杂质类型包括P型。
在该半导体结构中,在所述半导体衬底上的天线单元中形成所述半导体结构,所述天线单元包括具有基本相同的长度并且延伸穿过所述天线单元的多条平行的多晶硅线,所述伪多晶硅栅极由一条所述多晶硅线形成,所述金属引线通过相应的导电部件分别耦合至所述连续源极/漏极掺杂区的源极侧和漏极侧。
根据本发明的又一方面,提供了一种用于形成半导体结构的方法,所述方法包括:提供半导体衬底;在所述半导体衬底的表面上限定天线单元;形成具有基本相同的长度并且完全延伸穿过所述单元的多条基本平行的多晶硅线;使用一条所述多晶硅线作为伪栅极来形成伪晶体管,所述伪晶体管包括设置在栅极介电层上方的所述伪栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方;以及形成耦合至有源晶体管栅极并进一步耦合至由所述伪晶体管形成的二极管的金属引线,其中,所述伪栅极耦合至所述半导体衬底,并且所述金属引线耦合至所述连续源极/漏极掺杂区。
该方法进一步包括将所述半导体衬底耦合至Vss电压源。
在该方法中,所述伪栅极通过其他金属引线直接耦合至所述半导体衬底。
在该方法中,所述伪栅极通过钳低单元间接耦合至所述半导体衬底。
在该方法中,所述半导体衬底包括P型衬底,所述连续源极/漏极掺杂区包括N型材料,以及所述二极管包括形成在所述连续源极/漏极掺杂区和所述半导体衬底之间的PN结。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据标准实践,附图中的各种部件没有必要按比例绘制。相反地,为了清晰,各种部件的尺寸可以被任意增加或减少。在整个说明书和附图中,相同的数字用于指示相同的部件。
图1是示出根据本发明的示例性天线单元结构的部分的立体截面透视图;
图2A和图2B分别是根据本发明的示例性天线单元结构的电路图和器件布局;
图3A和图3B分别是根据本发明的另一个示例性天线单元结构的电路图和器件布局。
具体实施方式
本发明提供一种减轻集成电路芯片设计中的天线规则冲突(antenna ruleviolation)的结构。本发明还提供了用于形成此结构以及将此结构的形成集成到用于形成各种不同的集成电路器件的工艺操作中的方法。为了避免也被称为天线效应的等离子体导致的栅极介电层损害,天线规则是在芯片设计中必须遵守的规则。当诸如互连金属引线的导电部件耦合至晶体管的多晶硅栅电极或其他栅电极并由于对该结构实施的等离子体工艺操作或其他操作具有高电荷时,天线效应可以导致栅极介电材料和栅电极的击穿。如果在连接至晶体管的栅电极的导电引线上累积大量的电荷,则由于这种天线效应可以破坏晶体管。
公开的天线单元结构减轻了等离子体导致的栅极介电层损害,即,天线效应。天线单元包括防止和减轻天线效应的结构。由于种种原因,必须使用专用的基板面(real estate)形成许多天线单元。这样的一个原因是要求当形成多晶硅引线时,这些天线通常被形成为若干平行线的组,该若干平行线紧接形成并且具有基本上相同长度。一些示例性天线单元不可以使用这种嵌套的多晶硅引线,而是优选地形成在单独分配的天线单元区域中。
本发明提供利用多晶硅引线的天线单元,例如多晶硅引线可以被形成为与其他平行多晶硅引线紧密嵌套。
图1示出了示例性天线二极管结构2,天线二极管结构是CMOS结构并且可以形成在诸如逻辑或存储器件或其他半导体器件的集成电路中的专用天线单元中或各种其他位置处。金属引线4是天线二极管结构2的输入引脚并且可以由各种合适的导电材料和使用各种图案化操作形成。金属引线4连接至布线金属线(未示出)并形成到达衬底的放电路径。金属引线4也耦合6(如通过箭头所示)至例如可以容易受到也被称为天线效应的等离子体导致的栅极介电层损害影响的集成电路的有源晶体管的栅极。半导体衬底10可以是硅衬底或其他合适的半导体衬底并且包括顶面26。在所示的实施例中,半导体衬底10是耦合至Vss源的P型衬底,但是可以在其他示例性实施例中使用N型衬底。有源区12形成在半导体衬底10中并从衬底表面26向下延伸。根据半导体衬底10是P型材料的示例性实施例,有源区12是N型有源区。一般来说,有源区12具有与半导体衬底10相对的极性。也根据半导体衬底10是P型材料的示例性实施例,N阱区24包括是P型有源区的有源区14。
通常,以圆形区域示出伪晶体管16。在示例性实施例中伪晶体管16是NMOS晶体管并且包括优选地由多晶硅形成的伪晶体管栅极18。如下文中所示,形成伪晶体管栅极18的多晶硅引线可以是多条相同长度的基本上平行的多晶硅引线中的一条。诸如栅极氧化物的栅极介电层设置在晶体管栅极18和有源区12之间的界面20处,该有源区12在示例性实施例中是N型有源区。有源区12是单一掺杂区域,即,从伪晶体管16的源极区位置延伸至伪晶体管16的漏极区位置的连续掺杂区域,而没有与有源晶体管 中不同的沟道掺杂特性。伪晶体管16包括因此电连接在一起的源极/漏极区22。金属引线4通过相应的导电结构32耦合至每个源极/漏极区22。在所示的实施例中,每个导电结构32都由导电通孔38、下部导电金属部分34和上部导电金属部分36形成,但在其他实施例中可以使用不同的连接导电部件。在一个实施例中,下部导电金属部分34由钨形成而上部导电金属部分36由铜形成,但在其他实施例中可以使用其他合适的导电材料。因此,金属引线4耦合至每个源极/漏极区22,该源极/漏极区耦合在一起以避免泄漏。伪晶体管栅极18如下所述直接地或间接地耦合30(如通过箭头所示)至衬底10,该衬底是保持在Vss的P型衬底。
可以使用已知的或今后开发的工艺和各种合适的材料形成前述部件中的每个。可以使用同时用于形成天线二极管结构结合其中的集成电路的其他部件或其他半导体器件的相同工艺操作来实施天线二极管结构2的形成。
根据一个示例性实施例,伪晶体管栅极18可以直接耦合至半导体衬底10和Vss,例如,通过其他金属引线直接耦合至半导体衬底10。在图2A的电路图中和在图2B的示例性天线单元布局中示出了这种直接耦合。图2A示出了连接在一起并连接至金属引线4的源极/漏极区22,如上所述,该金属引线4可以是输入引脚。衬底10保持在Vss并耦合30至伪晶体管栅极18。图2B示出了示例性天线单元布局42,该天线单元布局包括具有基本上相同的长度的多条基本上平行的多晶硅引线44。如图2B所示,这些多晶硅引线44中的一条形成位于天线二极管结构2中的伪晶体管栅极18。天线单元布局42也示出了可以是输入引脚或耦合至输入引脚的金属引线4和有源区12。有源区12形成在保持在Vss的半导体衬底10的区域中。如图1和图2B所示,二极管形成在有源区12和半导体衬底10之间的相交区域处。金属引线4通过如上所述的导电结构32和导电通孔38耦合至有源区12的源极/漏极区。如也在图2A的电路图中所示,图2B的天线单元布局42示出了例如通过导电通孔38和导电部分36和34在伪晶体管16的伪多晶硅栅极18和半导体衬底10之间的示例性连接。通过向伪晶体管16提供逻辑“0”以使其截止,伪晶体管16(在示例性实施例中的NMOS晶 体管)可以截止以避免泄漏。金属引线50以及导电通孔52和56也可以用于电耦合各种示例性实施例中的部件。
根据诸如图3A和图3B所示的另一个示例性实施例,伪晶体管16的伪多晶硅栅极18可以使用钳低电平(tie-low)单元耦合至衬底,即,至Vss。钳低单元在本领域内是公知的并用于提供ESD保护,即,通过避免在诸如伪多晶硅栅极18的栅极和诸如半导体衬底10的电源/地线之间的直接连接防止静电放电(ESD)的保护。图3A是具有与图2A的电路图类似的部件的电路图并且示出了连接在一起并连接至金属线4的源极/漏极区22。然而,在图3A的电路图中,伪多晶硅栅极18通过钳低单元40间接地耦合30至半导体衬底10和Vss。
在图3B的示例性天线单元布局48中通过虚线也指出了钳低单元40,图3B还包括具有基本上相同长度的多条平行的多晶硅引线44。一个这种多晶硅引线44用作天线二极管结构2的伪栅电极18。在图3B的天线单元布局48中,天线二极管结构2与图2B所示的天线二极管结构2基本上相同。钳低单元40提供ESD保护、逻辑“0”以及与半导体衬底10和Vss的间接连接。应该强调的是,图3A和图3B所示的钳低单元40仅仅是示例性的,而诸如可以是本领域内公知的或今后开发的其他钳低单元结构可以用于将伪栅电极18间接地耦合至半导体衬底和Vss电压源。这种钳低单元可以是标准单元库的部分并用于将晶体管栅极连接至电源或接地。
根据一个方面,提供减轻半导体器件中的等离子体导致的栅极介电层损害的半导体结构。半导体结构包括:至少一个有源晶体管,具有有源多晶硅栅极;金属引线,耦合至至少一个有源多晶硅栅极;以及二极管,通过包括设置在连续源极/漏极掺杂区上方的栅极介电层上方的伪多晶硅晶体管栅极的伪晶体管将金属引线耦合至Vss。二极管包括耦合至连续源极/漏极掺杂区的金属引线和耦合至Vss的伪多晶硅晶体管栅极。
根据另一个方面,提供用于减轻半导体器件中的等离子体导致的栅极介电层损害的半导体结构。半导体结构包括:至少一个有源晶体管,具有有源多晶硅栅极并且形成在半导体衬底上;金属引线,耦合至至少一个有源多晶硅栅极;以及二极管,通过伪晶体管将金属引线耦合至半导体衬底。 伪晶体管包括设置在连续源极/漏极掺杂区上方的栅极介电层上方的伪多晶硅晶体管栅极,二极管包括耦合至连续源极/漏极掺杂区的金属引线以及耦合至半导体衬底的伪多晶硅晶体管栅极。
根据又一个方面,提供形成用于减轻半导体器件中的等离子体导致的栅极介电层损害的半导体结构的方法。方法包括:提供半导体衬底;在半导体衬底的表面上限定天线单元,形成具有基本上相同长度并且完全地延伸穿过单元的多条多晶硅线;使用一条多晶硅线作为其伪栅极形成伪晶体管,伪晶体管包括设置在位于连续源极/漏极掺杂区上方的栅极介电层上方的伪栅极;以及形成耦合至有源晶体管栅极并进一步耦合至由伪晶体管形成的二极管的金属引线,其中,伪栅极耦合至半导体衬底而金属引线耦合至连续源极/漏极掺杂区。
前面仅仅示出了本发明的原理。因此,应该理解,虽然本文中没有明确地描述或示出,但是本领域技术人员将能够设计实现本发明的原理并包括在本主旨和范围内的各种布置。此外,在此列举的所有实例和条件语言主要明确旨在仅用于教导目的,以帮助读者理解本发明的原理和发明者贡献的概念以促进本领域进步,并且应被解释为不限于这些具体列举的实例和条件。此外,本文中列举本发明的原理、方面和实施例,以及它们的具体实例的所有陈述旨在包含它们的结构和功能等同物。此外,旨在这种等同物包括当前公知的等同物和将来开发的等同物,即,无论结构怎样,开发的实施相同功能的任意元件。
意在结合被认为是整个书面描述的一部分的附图阅读示例性实施例的该描述。在描述中,空间相对位置的术语,例如“下部”、“上部”、“水平”、“垂直”、“在...之上”、“在...之下”、“向上”、“向下”、“顶部”、“底部”等及其派生词(例如,“水平地”、“向下地”、“向上地”等)应该理解为指的是如所描述的或如所讨论的附图中所示的定向。这些空间相对位置的术语是为了描述方便,并不要求以特定定向构建或操作器件或结构。除非另有明确说明,否则关于连接、耦合等的术语(例如“连接”和“互连”)指的是结构直接固定或附接至另结构或通过中间结构间接固定或附接至另一结构的关系以及可移动或刚性附接或关系。
尽管已经根据示例性实施例描述了本发明,但本发明不限于此。相反,所附权利要求应该被广泛地理解为包括可以由本领域技术人员在不背离等效范围的情况下做出的本发明的其他变型例和实施例。
Claims (10)
1.一种半导体结构,包括:
至少一个有源晶体管,具有有源多晶硅栅极;
金属引线,耦合至至少一个所述有源多晶硅栅极;以及
二极管,通过伪晶体管将所述金属引线耦合至Vss,所述伪晶体管包括设置在栅极介电层上方的伪多晶硅晶体管栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方,所述二极管包括耦合至所述连续源极/漏极掺杂区的所述金属引线和耦合至所述Vss的所述伪多晶硅晶体管栅极。
2.根据权利要求1所述的半导体结构,其中,所述至少一个有源晶体管设置在半导体衬底上,所述衬底保持在所述Vss,并且所述伪多晶硅晶体管栅极耦合至所述衬底。
3.根据权利要求2所述的半导体结构,其中,所述伪多晶硅晶体管栅极通过其他金属引线耦合至所述衬底。
4.根据权利要求2所述的半导体结构,其中,所述伪多晶硅晶体管栅极通过钳低单元耦合至所述衬底。
5.根据权利要求2所述的半导体结构,其中,所述二极管包括PN结。
6.根据权利要求2所述的半导体结构,其中,所述连续源极/漏极掺杂区是N型区,所述衬底是P型衬底,并且所述二极管包括位于所述N型区和所述P型衬底之间的PN结。
7.根据权利要求2所述的半导体结构,其中,所述金属引线耦合至所述半导体器件的输入引脚。
8.根据权利要求2所述的半导体结构,其中,在所述半导体衬底上的天线单元中形成所述半导体结构,所述天线单元包括具有基本相同的长度并且延伸穿过所述天线单元的多条平行的多晶硅线,并且所述伪多晶硅晶体管栅极由一条所述多晶硅线形成。
9.一种半导体结构,包括:
至少一个有源晶体管,具有有源多晶硅栅极并形成在半导体衬底上;
金属引线,耦合至至少一个所述有源多晶硅栅极;以及
二极管,通过伪晶体管将所述金属引线耦合至所述半导体衬底,所述伪晶体管包括设置在栅极介电层上方的伪多晶硅晶体管栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方,所述二极管包括耦合至所述连续源极/漏极掺杂区的所述金属引线和耦合至所述半导体衬底的所述伪多晶硅晶体管栅极。
10.一种用于形成半导体结构的方法,所述方法包括:
提供半导体衬底;
在所述半导体衬底的表面上限定天线单元;
形成具有基本相同的长度并且完全延伸穿过所述单元的多条基本平行的多晶硅线;
使用一条所述多晶硅线作为伪栅极来形成伪晶体管,所述伪晶体管包括设置在栅极介电层上方的所述伪栅极,其中所述栅极介电层设置在连续源极/漏极掺杂区上方;以及
形成耦合至有源晶体管栅极并进一步耦合至由所述伪晶体管形成的二极管的金属引线,其中,所述伪栅极耦合至所述半导体衬底,并且所述金属引线耦合至所述连续源极/漏极掺杂区。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/316,807 US8872269B2 (en) | 2011-12-12 | 2011-12-12 | Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits |
US13/316,807 | 2011-12-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103165602A true CN103165602A (zh) | 2013-06-19 |
CN103165602B CN103165602B (zh) | 2016-07-20 |
Family
ID=48571208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210477419.7A Active CN103165602B (zh) | 2011-12-12 | 2012-11-21 | 防止半导体集成电路中等离子体导致的栅极介电层损害的天线单元设计 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8872269B2 (zh) |
CN (1) | CN103165602B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109478550A (zh) * | 2016-07-13 | 2019-03-15 | 高通股份有限公司 | 用于减小的泄漏电流和提高的去耦电容的标准单元架构 |
CN110931375A (zh) * | 2018-09-20 | 2020-03-27 | 南亚科技股份有限公司 | 半导体结构及其制造方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140159157A1 (en) * | 2012-12-07 | 2014-06-12 | Altera Corporation | Antenna diode circuitry and method of manufacture |
US9490245B1 (en) * | 2015-06-19 | 2016-11-08 | Qualcomm Incorporated | Circuit and layout for a high density antenna protection diode |
KR102542466B1 (ko) | 2015-11-27 | 2023-06-12 | 삼성전자주식회사 | 빔 스티어링 소자 및 이를 적용한 시스템 |
KR102520856B1 (ko) | 2016-07-21 | 2023-04-12 | 삼성전자주식회사 | P-n 접합층을 포함하는 빔 스티어링 소자 |
US10692808B2 (en) | 2017-09-18 | 2020-06-23 | Qualcomm Incorporated | High performance cell design in a technology with high density metal routing |
US10325663B1 (en) | 2017-12-29 | 2019-06-18 | Macronix International Co., Ltd. | Protecting memory cells from in-process charging effects |
KR102496371B1 (ko) | 2018-10-30 | 2023-02-07 | 삼성전자주식회사 | 반도체 장치 |
KR20220037011A (ko) * | 2020-09-16 | 2022-03-24 | 삼성전자주식회사 | 반도체 장치 |
US11862625B2 (en) | 2021-07-01 | 2024-01-02 | Nxp Usa, Inc. | Area-efficient ESD protection inside standard cells |
US11754615B2 (en) | 2021-09-21 | 2023-09-12 | International Business Machines Corporation | Processor frequency improvement based on antenna optimization |
TWI804379B (zh) * | 2022-07-06 | 2023-06-01 | 龍華科技大學 | 降低半導體元件電漿靜電效應之製作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034433A (en) * | 1997-12-23 | 2000-03-07 | Intel Corporation | Interconnect structure for protecting a transistor gate from charge damage |
US20060094164A1 (en) * | 2004-10-29 | 2006-05-04 | Nec Electronics Corporation | Semiconductor integrated device, design method thereof, designing apparatus thereof, program thereof, manufacturing method thereof, and manufacturing apparatus thereof |
CN102024807A (zh) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的保护装置及保护方法 |
CN102142429A (zh) * | 2010-01-28 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | 等离子体损伤检测结构及其制作方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3470390A (en) * | 1968-02-02 | 1969-09-30 | Westinghouse Electric Corp | Integrated back-to-back diodes to prevent breakdown of mis gate dielectric |
JP3256110B2 (ja) * | 1995-09-28 | 2002-02-12 | シャープ株式会社 | 液晶表示装置 |
US7323752B2 (en) * | 2004-09-30 | 2008-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with floating diffusion regions |
-
2011
- 2011-12-12 US US13/316,807 patent/US8872269B2/en active Active
-
2012
- 2012-11-21 CN CN201210477419.7A patent/CN103165602B/zh active Active
-
2014
- 2014-10-10 US US14/511,932 patent/US9202696B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034433A (en) * | 1997-12-23 | 2000-03-07 | Intel Corporation | Interconnect structure for protecting a transistor gate from charge damage |
US20060094164A1 (en) * | 2004-10-29 | 2006-05-04 | Nec Electronics Corporation | Semiconductor integrated device, design method thereof, designing apparatus thereof, program thereof, manufacturing method thereof, and manufacturing apparatus thereof |
CN102024807A (zh) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的保护装置及保护方法 |
CN102142429A (zh) * | 2010-01-28 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | 等离子体损伤检测结构及其制作方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109478550A (zh) * | 2016-07-13 | 2019-03-15 | 高通股份有限公司 | 用于减小的泄漏电流和提高的去耦电容的标准单元架构 |
CN109478550B (zh) * | 2016-07-13 | 2023-05-16 | 高通股份有限公司 | 用于减小的泄漏电流和提高的去耦电容的标准单元架构 |
CN110931375A (zh) * | 2018-09-20 | 2020-03-27 | 南亚科技股份有限公司 | 半导体结构及其制造方法 |
CN110931375B (zh) * | 2018-09-20 | 2022-06-17 | 南亚科技股份有限公司 | 半导体结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20130146981A1 (en) | 2013-06-13 |
US8872269B2 (en) | 2014-10-28 |
CN103165602B (zh) | 2016-07-20 |
US20150031194A1 (en) | 2015-01-29 |
US9202696B2 (en) | 2015-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103165602B (zh) | 防止半导体集成电路中等离子体导致的栅极介电层损害的天线单元设计 | |
CN103887304B (zh) | 用于单片数据转换接口保护的装置及其形成方法 | |
US9318479B2 (en) | Electrostatic discharge (ESD) silicon controlled rectifier (SCR) with lateral gated section | |
US9190519B2 (en) | FinFET-based ESD devices and methods for forming the same | |
US20140131765A1 (en) | ESD Devices Comprising Semiconductor Fins | |
US8354697B2 (en) | Semiconductor integrated circuit device and a method of manufacturing the same | |
US20190006348A1 (en) | Electrostatic discharge protection semiconductor device | |
CN101339947A (zh) | 半导体器件 | |
KR100772097B1 (ko) | 반도체 회로용 정전기 보호소자 | |
US8866229B1 (en) | Semiconductor structure for an electrostatic discharge protection circuit | |
US10083966B2 (en) | Semiconductor integrated circuits having contacts spaced apart from active regions | |
CN105470250A (zh) | 过电压保护设备及方法 | |
CN105489503B (zh) | 半导体结构及其形成方法、静电保护电路 | |
US8664726B2 (en) | Electrostatic discharge (ESD) protection device, method of fabricating the device, and electronic apparatus including the device | |
CN105185776A (zh) | 天线效应放电回路及其制造方法 | |
CN104143549B (zh) | 一种静电释放保护电路版图及集成电路 | |
CN111587484A (zh) | 半导体集成电路装置 | |
CN103839925A (zh) | 半导体装置 | |
CN113192948A (zh) | 半导体器件 | |
CN101866920B (zh) | 一种esd保护结构 | |
CN105405843B (zh) | 静电保护电路 | |
CN110534510A (zh) | 静电放电保护半导体器件 | |
CN111883514B (zh) | 测试结构,晶圆及测试结构的制作方法 | |
TWI553821B (zh) | 靜電放電防護結構 | |
KR100773740B1 (ko) | 반도체 기판과 동일한 전압 레벨을 갖는 패드 및 이를포함하는 반도체 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |