CN103165561B - A kind of encapsulating structure of silicon substrate pinboard - Google Patents
A kind of encapsulating structure of silicon substrate pinboard Download PDFInfo
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- CN103165561B CN103165561B CN201310062926.9A CN201310062926A CN103165561B CN 103165561 B CN103165561 B CN 103165561B CN 201310062926 A CN201310062926 A CN 201310062926A CN 103165561 B CN103165561 B CN 103165561B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The present invention relates to a kind of encapsulating structure of silicon substrate pinboard, belong to technical field of semiconductor encapsulation.It comprises silicon substrate carrier (1), be arranged on the encapsulating region (2) of silicon substrate carrier (1) surrounding, front insulating barrier (31), insulating backside layer (32), front is interconnection metal layer (41) again, the back side is interconnection metal layer (42) again, front protecting layer (51) and back-protective layer (52), and be successively set on the positive and negative of silicon substrate carrier (1) and encapsulating region (2) respectively, the through hole (21) of filling metal is set in described encapsulating region (2), described front again interconnection metal layer (41) and the back side again interconnection metal layer (42) be connected by through hole (21) interior metal.The encapsulating structure of silicon substrate pinboard of the present invention is simple, packaging cost is low, finished product rate is high.
Description
Technical field
The present invention relates to a kind of encapsulating structure of silicon substrate pinboard, belong to technical field of semiconductor encapsulation.
Background technology
Along with the development of semiconductor technology, silicon through hole interconnection technique becomes the common method of semiconductor packages.Silicon through hole interconnection technique comprises that silicon through hole makes usually, PECVD(plasma enhanced chemical vapor deposition) technology contoured insulator layer and metal filled, this technology substantially increases the flexibility of semiconductor packages.
Silicon through hole interconnection technique has also been applied to the encapsulation of silicon substrate pinboard, silicon forming process of through hole mainly adopts " BOSCH " lithographic method, namely etching and passivation technology is used alternatingly, " BOSCH " lithographic method finally can leave the lines (scallop) that height rises and falls on hole wall, i.e. hole wall ripple, as shown in Figure 1, not only speed is slow for the alternately lithographic method of " BOSCH ", and hole wall ripple causes follow-up PECVD(plasma enhanced chemical vapor deposition used) insulating barrier that formed covers imperfect.Meanwhile, in the encapsulation process of silicon substrate pinboard, conventional CMP(chemico-mechanical polishing) the technique bottom of carrying out metal in surface evening and through hole exposes, in this polishing process, often cause metal or metal ion transport, make device produce electric leakage, cause product failure.Above factor, the encapsulation technology cost that result in existing silicon substrate pinboard is high, finished product rate is low.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, the encapsulating structure of the silicon substrate pinboard that a kind of encapsulating structure is simple, packaging cost is low, finished product rate is high is provided.
the present invention is achieved in thatan encapsulating structure for silicon substrate pinboard, comprises silicon substrate carrier, insulating barrier, again interconnection metal layer and protective layer,
The surrounding of described silicon substrate carrier arranges encapsulating region; described encapsulating region is encapsulated with the side of silicon substrate carrier and is connected; described insulating barrier comprises front insulating barrier and insulating backside layer; described interconnection metal layer again comprises front interconnection metal layer and back side interconnection metal layer more again; described protective layer comprises front protecting layer and back-protective layer
Described front insulating barrier is arranged on the front in silicon substrate carrier and encapsulating region; described front again interconnection metal layer optionally covers on the insulating barrier of front; described front protecting layer is arranged on front again on interconnection metal layer, and on front again interconnection metal layer, form several front protecting layer openings
Described insulating backside layer is arranged on the back side in silicon substrate carrier and encapsulating region; the described back side is under interconnection metal layer optionally covers insulating backside layer again; described back-protective layer is arranged on the back side again under interconnection metal layer, and under the back side again interconnection metal layer, form several back-protective layer openings
In described encapsulating region, through hole is set, fills metal in described through hole, described front again interconnection metal layer and the back side again interconnection metal layer be connected by metal in through hole.
The encapsulating junction of described encapsulating region and silicon substrate carrier is step-like.
Described through hole is single row or multiple rows array.
Go directly the lower surface of front interconnection metal layer again for the upper end of described through hole, and go directly the upper surface of back side interconnection metal layer again for the lower end of through hole.
In described back-protective layer opening, tin ball is set.
Described tin ball becomes array arrangement.
In described back-protective layer opening, the metal column of top with tin cap is set.
Described metal column becomes array arrangement.
Arrange metal micro convex point in described front protecting layer opening, the top of described metal micro convex point arranges tin projection.
Described metal micro convex point becomes array arrangement.
the invention has the beneficial effects as follows:
1, utilize the through-hole structure formed in the encapsulating region of silicon substrate pinboard surrounding, achieve electric signal transmission and heat trnasfer, solve technological problems and the Cost Problems of through-silicon via structure well;
2, on encapsulating region, adopt laser beam drilling to form metal in through hole in conjunction with the mode of electroless copper, both reduced the complexity of technological operation, also reduced product cost, improved product yield and reliability.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the silicon through hole hole wall ripple that prior art produces.
Fig. 2 is the schematic diagram of the embodiment one of the encapsulating structure of a kind of silicon substrate pinboard of the present invention.
Fig. 3 is the A-A cutaway view of Fig. 2.
Fig. 4 is the schematic diagram of the embodiment two of the encapsulating structure of a kind of silicon substrate pinboard of the present invention.
Fig. 5 is the schematic diagram of the embodiment three of the encapsulating structure of a kind of silicon substrate pinboard of the present invention.
In figure:
Silicon substrate carrier 1
Encapsulating region 2
Front insulating barrier 31
Insulating backside layer 32
Front is interconnection metal layer 41 again
The back side is interconnection metal layer 42 again
Front protecting layer 51
Back-protective layer 52
Tin ball 6
Metal column 7
Tin cap 8
Metal micro convex point 9
Tin projection 10.
Embodiment
See Fig. 2 to Fig. 5, the encapsulating structure of a kind of silicon substrate pinboard of the present invention, comprises silicon substrate carrier 1, insulating barrier, again interconnection metal layer and protective layer.The surrounding of described silicon substrate carrier 1 arranges encapsulating region 2, and encapsulating region 2 is encapsulated with the side of silicon substrate carrier 1 and is connected.The material in encapsulating region 2 is resin, is generally epoxylite material, includes inserts, to reduce the larger problem of thermal expansion coefficient difference between resin material and silicon materials, the thermomechanical reliability of lift structure.Encapsulate junction and in step-like, the bonded area between single or multiple step increase encapsulating material and silicon substrate carrier 1 can be utilized, thus promote the adhesion of encapsulating region 2 and silicon substrate carrier 1, as shown in the schematic diagram that Fig. 2 amplifies.
Described insulating barrier comprises front insulating barrier 31 and insulating backside layer 32, then interconnection metal layer comprises front interconnection metal layer 41 and back side interconnection metal layer 42 more again, and described protective layer comprises front protecting layer 51 and back-protective layer 52.
Described front insulating barrier 31 is arranged on the front in silicon substrate carrier 1 and encapsulating region 2, described front again interconnection metal layer 41 optionally covers on front insulating barrier 31, described front protecting layer 51 is arranged on front again on interconnection metal layer 41, and on front again interconnection metal layer 41, form several front protecting layer openings 511; Described insulating backside layer 32 is arranged on the back side in silicon substrate carrier 1 and encapsulating region 2; the described back side again interconnection metal layer 42 optionally covers insulating backside layer 32 times; described back-protective layer 52 is arranged on back side interconnection metal layer 42 times again, and in the back side again interconnection metal layer form several back-protective layer openings 521 for 42 times.
Wherein, the concrete number of plies of front interconnection metal layer 41 and back side interconnection metal layer 42 more again can be set to one or more layers according to product requirement, and common, front again interconnection metal layer 41 is high-density wiring layer, and namely live width/line-spacing is at below 5um.Protective layer material generally includes silica, silicon nitride or resinae dielectric material, and different dielectric material again between interconnection metal layer can be identical, also can be different.
The front protecting layer opening 511 that front interconnection metal layer 41 is formed again and the back side is the back-protective layer opening 521 that formed for 42 times of interconnection metal layer again, is convenient to the connection of subsequent element, as shown in Fig. 2, Fig. 4 and Fig. 5.In front protecting layer opening 511, the metal micro convex point 9 of top with tin projection 10 can be set, and metal micro convex point 9 one-tenth array arrangements.In back-protective layer opening 521, tin ball 6 is set, tin ball 6 one-tenth array arrangements, as shown in Figure 4, or the metal column 7 of top with tin cap 8 is set, metal column 7 one-tenth array arrangement, as shown in Figure 5.
The through hole 21 of single row or multiple rows array is set in described encapsulating region 2.Fill metal in described through hole 21, common, filling metal is electro-coppering.In through hole 21 upper end of metal, lower end respectively with front again interconnection metal layer 41, the back side again interconnection metal layer 42 be connected, be the interface channel of silicon substrate pinboard positive/negative electric signal, be also one of heat dissipation channel of encapsulating structure simultaneously.
Claims (10)
1. an encapsulating structure for silicon substrate pinboard, comprises silicon substrate carrier (1), insulating barrier, again interconnection metal layer and protective layer,
It is characterized in that: the surrounding of described silicon substrate carrier (1) arranges encapsulating region (2); described encapsulating region (2) is encapsulated with the side of silicon substrate carrier (1) and is connected; described insulating barrier comprises front insulating barrier (31) and insulating backside layer (32); described interconnection metal layer again comprises front interconnection metal layer (41) and back side interconnection metal layer (42) more again; described protective layer comprises front protecting layer (51) and back-protective layer (52)
Described front insulating barrier (31) is arranged on the front of silicon substrate carrier (1) and encapsulating region (2); described front again interconnection metal layer (41) optionally covers on front insulating barrier (31); described front protecting layer (51) is arranged on front again on interconnection metal layer (41); and in front, interconnection metal layer (41) is upper again forms several front protecting layer openings (511)
Described insulating backside layer (32) is arranged on the back side of silicon substrate carrier (1) and encapsulating region (2); the described back side is under interconnection metal layer (42) optionally covers insulating backside layer (32) again; described back-protective layer (52) is arranged on the back side again under interconnection metal layer (42); and several back-protective layer openings (521) are formed under the back side again interconnection metal layer (42)
In described encapsulating region (2), through hole (21) is set, fills metal in described through hole (21), described front again interconnection metal layer (41) and the back side again interconnection metal layer (42) be connected by through hole (21) interior metal.
2. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1, is characterized in that: described encapsulating region (2) is step-like with the encapsulating junction of silicon substrate carrier (1).
3. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1, is characterized in that: described through hole (21) is single row or multiple rows array.
4. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1 and 2, it is characterized in that: go directly the lower surface of front interconnection metal layer (41) again for the upper end of described through hole (21), go directly the upper surface of back side interconnection metal layer (42) again for the lower end of through hole (21).
5. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1, is characterized in that: arrange tin ball (6) in described back-protective layer opening (521).
6. the encapsulating structure of a kind of silicon substrate pinboard according to claim 5, is characterized in that: described tin ball (6) becomes array arrangement.
7. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1, is characterized in that: arrange the metal column (7) of top with tin cap (8) in described back-protective layer opening (521).
8. the encapsulating structure of a kind of silicon substrate pinboard according to claim 7, is characterized in that: described metal column (7) becomes array arrangement.
9. the encapsulating structure of a kind of silicon substrate pinboard according to claim 1, is characterized in that: arrange metal micro convex point (9) in described front protecting layer opening (511), and the top of described metal micro convex point (9) arranges tin projection (10).
10. the encapsulating structure of a kind of silicon substrate pinboard according to claim 9, is characterized in that: described metal micro convex point (9) becomes array arrangement.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310062926.9A CN103165561B (en) | 2013-02-28 | 2013-02-28 | A kind of encapsulating structure of silicon substrate pinboard |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310062926.9A CN103165561B (en) | 2013-02-28 | 2013-02-28 | A kind of encapsulating structure of silicon substrate pinboard |
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| CN103165561A CN103165561A (en) | 2013-06-19 |
| CN103165561B true CN103165561B (en) | 2015-09-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465570B (en) * | 2014-12-31 | 2017-06-23 | 江阴长电先进封装有限公司 | A kind of TSV Interposer structures and its method for packing |
| CN105575938B (en) * | 2016-02-26 | 2018-10-26 | 中国科学院微电子研究所 | A kind of silicon substrate pinboard and preparation method thereof |
| CN112151418B (en) * | 2020-09-11 | 2024-04-05 | 安徽龙芯微科技有限公司 | Packaging mechanism and packaging method of silicon-based adapter plate |
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| CN101416567A (en) * | 2006-04-10 | 2009-04-22 | 松下电器产业株式会社 | Relay substrate, method for manufacturing the relay substrate and three-dimensional circuit device using the relay substrate |
| CN102299143A (en) * | 2010-06-25 | 2011-12-28 | 台湾积体电路制造股份有限公司 | Semiconductor element |
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| US6406934B1 (en) * | 2000-09-05 | 2002-06-18 | Amkor Technology, Inc. | Wafer level production of chip size semiconductor packages |
| JP4093018B2 (en) * | 2002-11-08 | 2008-05-28 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| US7023084B2 (en) * | 2003-03-18 | 2006-04-04 | Sumitomo Metal (Smi) Electronics Devices Inc. | Plastic packaging with high heat dissipation and method for the same |
| JP5117692B2 (en) * | 2006-07-14 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US20090032925A1 (en) * | 2007-07-31 | 2009-02-05 | England Luke G | Packaging with a connection structure |
| US8487444B2 (en) * | 2009-03-06 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional system-in-package architecture |
| US8093151B2 (en) * | 2009-03-13 | 2012-01-10 | Stats Chippac, Ltd. | Semiconductor die and method of forming noise absorbing regions between THVS in peripheral region of the die |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101416567A (en) * | 2006-04-10 | 2009-04-22 | 松下电器产业株式会社 | Relay substrate, method for manufacturing the relay substrate and three-dimensional circuit device using the relay substrate |
| CN102299143A (en) * | 2010-06-25 | 2011-12-28 | 台湾积体电路制造股份有限公司 | Semiconductor element |
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