CN103165482B - Bump technology - Google Patents
Bump technology Download PDFInfo
- Publication number
- CN103165482B CN103165482B CN201110423999.7A CN201110423999A CN103165482B CN 103165482 B CN103165482 B CN 103165482B CN 201110423999 A CN201110423999 A CN 201110423999A CN 103165482 B CN103165482 B CN 103165482B
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- Prior art keywords
- bump
- ring wall
- fluting
- face
- containing titanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
- H01L2224/11902—Multiple masking steps
- H01L2224/11906—Multiple masking steps with modification of the same mask
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a bump technology. The bump technology comprises that a silicon substrate is offered, a titanium containing metal layer which comprises a plurality of first areas and a plurality of second areas is prepared on the silicon substrate, a light resistance layer is prepared on the titanium containing metal layer, the light resistance layer is patterned to form a plurality of opening grooves which correspond to the plurality of first areas, a plurality of copper bumps are prepared in the plurality of opening grooves, a heating step is conducted, a plurality of bump isolating layers are prepared on the plurality of copper bumps, a plurality of jointing layers are prepared on the plurality of bump isolating layers, the light resistance layer is removed, the plurality of second areas of the titanium containing metal layer are removed, and each of the plurality of first areas is enabled to form a metal layer under each of the plurality of copper bumps.
Description
Technical field
The invention relates to a kind of bump technology, relate to a kind of bump technology preventing copper ion free especially.
Background technology
Because current electronic product is more and more compact, therefore internal circuit layout is also more and more intensive, but this kind of circuit layout easily causes the situation of short circuit because adjacent electrical connection module distance is too near.
As can be seen here, above-mentioned existing technology with in use in structure, obviously still has inconvenience and defect, and is urgently further improved.Therefore how to found a kind of bump technology of new structure, also become the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, overcome the defect that existing technology exists, and a kind of bump technology of new structure is provided, technical problem to be solved is such that it will prevent the copper ion of described copper bump dissociate and cause the situation of electrical short, and due to each this projection separator be to prevent the copper ion of described copper bump from dissociating, therefore the spacing of adjacent copper bump can reduce further, and then promotes wiring density.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of bump technology that the present invention proposes, wherein at least comprise: a silicon substrate is provided, this silicon substrate be there is a surface, multiple weld pads and being arranged on this surface are arranged on the protective layer on this surface, this protective layer has multiple opening, and described opening appears described weld pad; Form one containing titanium coating at this silicon substrate, should be cover this protective layer and described weld pad containing titanium coating, and should be that there is multiple firstth district and multiple the secondth district be positioned at outside described firstth district containing titanium coating; Form a photoresist layer at this containing titanium coating; This photoresist layer of patterning to form multiple fluting, described fluting be to should titaniferous metal level described firstth district and respectively this fluting be that there is a madial wall; Form multiple copper bump at described fluting, respectively this copper bump has one first end face and one first ring wall; Carry out a heating steps, to make respectively this fluting of this photoresist layer form reaming, and make to be formed with a spacing between this first ring wall of this madial wall of respectively this fluting and each this copper bump; Form multiple projection separator at this first end face of described spacing, respectively this copper bump and this first ring wall, and respectively this projection separator has one second end face; Form described second end face of multiple knitting layer at described projection separator; Remove this photoresist layer; And remove this described secondth district containing titanium coating, and make this respectively this firstth district containing titanium coating be formed as one to be positioned at Underbump metallization floor under each this projection separator.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid bump technology, wherein said respectively this Underbump metallization layer has one second ring wall and this second ring wall has one first outer perimeter, respectively this projection separator separately has one the 3rd ring wall and the 3rd ring wall has one second outer perimeter, and this second outer perimeter is not less than this first outer perimeter.
Aforesaid bump technology, wherein said respectively this Underbump metallization layer has one second ring wall, and respectively this second ring wall and respectively this first ring wall be concordant.
Aforesaid bump technology, the glass transition temperature of wherein said heating steps is situated between 70-140 DEG C.
Aforesaid bump technology, the material of wherein said knitting layer is gold.
Aforesaid bump technology, the material of wherein said projection separator be selected from nickel, palladium or gold one of them.
Aforesaid bump technology, wherein said is forming multiple copper bump in the step of described fluting, and respectively this first ring wall of this copper bump is this madial wall contacting respectively this fluting.
Aforesaid bump technology, this wherein said protective layer separately has one and appears face, and respectively this projection separator separately has a bottom surface, and this appears between face and this bottom surface is have a gap.
The present invention compared with prior art has obvious advantage and beneficial effect.As known from the above, for achieving the above object, the invention provides a kind of bump technology, it comprises provides a silicon substrate, this silicon substrate be there is a surface, multiple weld pads and being arranged on this surface are arranged on the protective layer on this surface, this protective layer has multiple opening, and described opening appears described weld pad; Form one containing titanium coating at this silicon substrate, should be cover this protective layer and described weld pad containing titanium coating, and should be that there is multiple firstth district and multiple the secondth district be positioned at outside described firstth district containing titanium coating; Form a photoresist layer at this containing titanium coating; This photoresist layer of patterning to form multiple fluting, described fluting be to should titaniferous metal level described firstth district and respectively this fluting be that there is a madial wall; Form multiple copper bump at described fluting, respectively this copper bump has one first end face and one first ring wall; Carry out a heating steps, to make respectively this fluting of this photoresist layer form reaming, and make to be formed with a spacing between this first ring wall of this madial wall of respectively this fluting and each this copper bump; Form multiple projection separator at this first end face of described spacing, respectively this copper bump and this first ring wall, and respectively this projection separator has one second end face; Form described second end face of multiple knitting layer at described projection separator; Remove this photoresist layer; And remove this described secondth district containing titanium coating, and make this respectively this firstth district containing titanium coating be formed as one to be positioned at Underbump metallization floor under each this projection separator.Because respectively this projection separator is coated respectively this copper bump, therefore can prevent the copper ion of described copper bump from dissociating and causing the situation of electrical short, and due to each this projection separator be to prevent the copper ion of described copper bump from dissociating, therefore the spacing of adjacent copper bump can reduce further, and then promotes wiring density.
By technique scheme, bump technology of the present invention at least has following advantages and beneficial effect: by being coated respectively this copper bump at each this projection separator, therefore can prevent the copper ion of described copper bump from dissociating and causing the situation of electrical short, and by being to prevent the copper ion of described copper bump from dissociating at each this projection separator, therefore the spacing of adjacent copper bump can reduce further, and then promotes wiring density.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other objects of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1: according to a preferred embodiment of the present invention, a kind of flow chart of bump technology.
Fig. 2 A to Fig. 2 J: according to a preferred embodiment of the present invention, the schematic cross-section of this bump technology.
10: a silicon substrate is provided
11: form one containing titanium coating at this silicon substrate, and should be that there is multiple firstth district and multiple secondth district containing titanium coating
12: form a photoresist layer at this containing titanium coating
13: this photoresist layer of patterning to form multiple fluting, described fluting be to should titaniferous metal level described firstth district and respectively this fluting be that there is a madial wall
14: form multiple copper bump at described fluting, respectively this copper bump has one first end face and one first ring wall
15: carry out a heating steps, to make respectively this fluting of this photoresist layer form reaming, and make to be formed with a spacing between this first ring wall of this madial wall of respectively this fluting and each this copper bump
16: form multiple projection separator at this first end face of described spacing, respectively this copper bump and this first ring wall
17: form multiple knitting layer at described projection separator
18: remove this photoresist layer
19: remove described secondth district that this contains titanium coating, and make this respectively this firstth district containing titanium coating be formed as a Underbump metallization floor
100: projection cube structure
110: silicon substrate 111: surface
112: weld pad 113: protective layer
113a: opening 113b: appear face
120: copper bump 121: the first end face
122: the first ring walls
130: projection separator 131: the second end face
132: the three ring walls 133: bottom surface
140: knitting layer 150: Underbump metallization layer
151: the second ring walls
200: containing titanium coating
210: the first districts of district 220: the second
300: photoresist layer
310: fluting 311: madial wall
A1: the first outer perimeter A2: the second outer perimeter
B: clearance D: spacing
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of bump technology proposed according to the present invention, structure, feature and effect thereof, be described in detail as follows.
Refer to Fig. 1 and Fig. 2 A to Fig. 2 J, it is a preferred embodiment of the present invention, a kind of bump technology comprises the following step: first, refer to step 10 and Fig. 2 A of Fig. 1, one silicon substrate 110 is provided, this silicon substrate 110 be there is a surface 111, protective layer 113 that multiple weld pads 112 and being arranged on this surface 111 are arranged on this surface 111, this protective layer 113 has multiple opening 113a, and described opening 113a appears described weld pad 112; Then, refer to step 11 and Fig. 2 B of Fig. 1, form one containing titanium coating 200 at this silicon substrate 110, should be cover this protective layer 113 and described weld pad 112 containing titanium coating 200, and multiple first district 210 and multiple the second district 220 be positioned at outside described first district 210 should be had containing titanium coating 200; Afterwards, refer to step 12 and Fig. 2 C of Fig. 1, form a photoresist layer 300 at this containing titanium coating 200; Then, refer to step 13 and Fig. 2 D of Fig. 1, this photoresist layer 300 of patterning to form multiple fluting 310, described fluting 310 be to should titaniferous metal level 200 described first district 210 and respectively this fluting 310 be that there is a madial wall 311; Afterwards, refer to step 14 and Fig. 2 E of Fig. 1, form multiple copper bump 120 at described fluting 310, respectively this copper bump 120 has one first end face 121 and one first ring wall 122, in the present embodiment, respectively this first ring wall 122 of this copper bump 120 is these madial walls 311 contacting respectively this fluting 310.
Then, refer to step 15 and Fig. 2 F of Fig. 1, carry out a heating steps, reaming is formed to make respectively this fluting 310 of this photoresist layer 300, and make to be formed with a space D between this first ring wall 122 of this madial wall 311 of respectively this fluting 310 and each this copper bump 120, in the present embodiment, the glass transition temperature of this heating steps is between 70-140 DEG C; Afterwards, refer to step 16 and Fig. 2 G of Fig. 1, form multiple projection separator 130 at this first end face 121 of described space D, respectively this copper bump 120 and this first ring wall 122, and respectively this projection separator 130 has one second end face 131, the material of described projection separator 130 be optional comfortable nickel, palladium or gold one of them; Then, refer to step 17 and Fig. 2 H of Fig. 1, form described second end face 131 of multiple knitting layer 140 at described projection separator 130, in the present embodiment, the material of described knitting layer 140 is gold; Afterwards, refer to step 18 and Fig. 2 I of Fig. 1, remove this photoresist layer 300; Finally, refer to step 19 and Fig. 2 J of Fig. 1, remove described second district 220 that this contains titanium coating 200, and make this respectively this firstth district 210 containing titanium coating 200 be formed as one to be positioned at Underbump metallization floor 150 under each this projection separator 130 to form a projection cube structure 100, in the present embodiment, the material of described Underbump metallization layer 150 be optional comfortable titanium/tungsten/gold, titanium/copper or titanium/tungsten/copper one of them.
In addition, referring again to Fig. 2 J, respectively this Underbump metallization layer 150 has one second ring wall 151 and this second ring wall 151 has one first outer perimeter A1, respectively this projection separator 130 separately has one the 3rd ring wall 132 and the 3rd ring wall 132 has one second outer perimeter A2, this second outer perimeter A2 is not less than this first outer perimeter A1, and respectively this first ring wall 122 of this second ring wall 151 and each this copper bump 120 is for concordant, in addition, in the present embodiment, this protective layer 113 separately has one and appears face 113b, respectively this projection separator 130 separately has a bottom surface 133, this appears between face 113b and this bottom surface 133 is have a gap B.Because respectively this projection separator 130 is coated respectively these copper bumps 120, therefore can prevent the copper ion of described copper bump 120 from dissociating and causing the situation of electrical short, and due to each this projection separator 130 be to prevent the copper ion of described copper bump 120 from dissociating, therefore the spacing of adjacent copper bump 120 can reduce further, and then promotes wiring density.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (8)
1. a bump technology, is characterized in that at least comprising:
One silicon substrate is provided, this silicon substrate be there is a surface, multiple weld pads and being arranged on this surface are arranged on the protective layer on this surface, this protective layer has multiple opening, and described opening appears described weld pad;
Form one containing titanium coating at this silicon substrate, should be cover this protective layer and described weld pad containing titanium coating, and should be that there is multiple firstth district and multiple the secondth district be positioned at outside described firstth district containing titanium coating;
Form a photoresist layer at this containing titanium coating;
This photoresist layer of patterning to form multiple fluting, described fluting be to should titaniferous metal level described firstth district and respectively this fluting be that there is a madial wall;
Form multiple copper bump at described fluting, respectively this copper bump has one first end face and one first ring wall;
Carry out a heating steps, to make respectively this fluting of this photoresist layer form reaming, and make to be formed with a spacing between this first ring wall of this madial wall of respectively this fluting and each this copper bump;
Form multiple projection separator at this first end face of described spacing, respectively this copper bump and this first ring wall, and respectively this projection separator has one second end face;
Form described second end face of multiple knitting layer at described projection separator;
Remove this photoresist layer; And
Remove this described secondth district containing titanium coating, and make this respectively this firstth district containing titanium coating be formed as one to be positioned at Underbump metallization floor under each this projection separator.
2. bump technology as claimed in claim 1, it is characterized in that wherein said respectively this Underbump metallization layer has one second ring wall and this second ring wall has one first outer perimeter, respectively this projection separator separately has one the 3rd ring wall and the 3rd ring wall has one second outer perimeter, and this second outer perimeter is not less than this first outer perimeter.
3. bump technology as claimed in claim 1, is characterized in that wherein said respectively this Underbump metallization layer has one second ring wall, and respectively this second ring wall and respectively this first ring wall be concordant.
4. bump technology as claimed in claim 1, is characterized in that the glass transition temperature of wherein said heating steps is between 70-140 DEG C.
5. bump technology as claimed in claim 1, it is characterized in that the material of wherein said knitting layer is is gold.
6. bump technology as claimed in claim 1, it is characterized in that the material of wherein said projection separator be selected from nickel, palladium or gold one of them.
7. bump technology as claimed in claim 1, it is characterized in that wherein said at the multiple copper bump of formation in the step of described fluting, respectively this first ring wall of this copper bump is this madial wall contacting respectively this fluting.
8. bump technology as claimed in claim 1, it is characterized in that this wherein said protective layer separately has one and appears face, respectively this projection separator separately has a bottom surface, and this appears between face and this bottom surface is have a gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110423999.7A CN103165482B (en) | 2011-12-13 | 2011-12-13 | Bump technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110423999.7A CN103165482B (en) | 2011-12-13 | 2011-12-13 | Bump technology |
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| Publication Number | Publication Date |
|---|---|
| CN103165482A CN103165482A (en) | 2013-06-19 |
| CN103165482B true CN103165482B (en) | 2015-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110423999.7A Active CN103165482B (en) | 2011-12-13 | 2011-12-13 | Bump technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105513983B (en) * | 2014-09-26 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | The method and wafer bonding structure of wafer bonding |
| US9780052B2 (en) * | 2015-09-14 | 2017-10-03 | Micron Technology, Inc. | Collars for under-bump metal structures and associated systems and methods |
| CN109979834A (en) * | 2019-03-29 | 2019-07-05 | 颀中科技（苏州）有限公司 | Bump manufacturing method for semiconductor packages |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1917155A (en) * | 2005-08-18 | 2007-02-21 | 三星电子株式会社 | Thin film transistor substrate and fabrication thereof |
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| US8264072B2 (en) * | 2007-10-22 | 2012-09-11 | Infineon Technologies Ag | Electronic device |
| US8492891B2 (en) * | 2010-04-22 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with electrolytic metal sidewall protection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1917155A (en) * | 2005-08-18 | 2007-02-21 | 三星电子株式会社 | Thin film transistor substrate and fabrication thereof |
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| CN103165482A (en) | 2013-06-19 |
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