CN103164365B

CN103164365B - Bus arbiter

Info

Publication number: CN103164365B
Application number: CN201110424416.2A
Authority: CN
Inventors: 林川
Original assignee: Wuxi Zhonggan Microelectronics Co Ltd
Current assignee: Nanjing Sino Microelectronics Co., Ltd.
Priority date: 2011-12-15
Filing date: 2011-12-15
Publication date: 2016-02-03
Anticipated expiration: 2031-12-15
Also published as: CN103164365A

Abstract

The invention provides a kind of bus arbiter, for on-chip integration system, this bus arbiter comprises module protocol interface, storer arbitration modules, bus switch module and memory interface; Puppy parc required for functional module is connected with bus arbiter by module protocol interface; The request of access of storer arbitration modules to functional module access storer makes arbitration; The logical consequence that bus switch module is arbitrated according to storer, the protocol bus of the internal unity sent by the interface of authorized functional module is switched to memory interface; The information of the burst transfer that memory interface obtains according to the switch logic of bus switch module, converts the bus protocol that storer needs to by the protocol information of functional module.

Description

Bus arbiter

Technical field

The present invention relates to a kind of bus arbiter, particularly the configurable bus arbiter of one.

Background technology

On-chip integration system (SoC), there is multiple functional module needs to access storer, as processor, hardware accelerator or IP etc.The memory resource of system comprises shared storage (as ROM, SRAM) in chip external memory (as SDRAM, DDR, NOR) and sheet.Jumbo storer generally only allows a read and write access simultaneously, so the access of storer needs by bus arbiter unit according to certain selection strategy, some module access request are authorized by memory access authority, the interim request of access hanging up other, processes all request of access until all simultaneously.

Processor and other functional modules independent operating separately.The connection of processor and storer is controlled by internal bus and moderator thereof.Because the signal source of each functional module is different, the bandwidth of needs is different, and it adopts internal bus agreement possibility varied, has AHB more widely, AHB_Lite, AXI, AXI_Lite, APB, OCP etc.Conveniently integrated various IP and module, bus arbiter needs the request simultaneously supporting above various protocols.

Summary of the invention

The object of this invention is to provide a kind of collocation method being applicable to the bus arbiter of multiple bus protocol.

A kind of bus arbiter, for on-chip integration system, this bus arbiter comprises module protocol interface, storer arbitration modules, bus switch module and memory interface;

Puppy parc required for functional module is connected with bus arbiter by module protocol interface;

The request of access of storer arbitration modules to functional module access storer makes arbitration;

The logical consequence that bus switch module is arbitrated according to storer, the protocol bus of the internal unity sent by the interface of authorized functional module is switched to memory interface;

The information of the burst transfer that memory interface obtains according to the switch logic of bus switch module, converts the bus protocol that storer needs to by the protocol information of functional module.

The dirigibility of the bus of bus arbiter of the present invention is high, can adapt to multiple different bus agreement and multiple memorizers, portable and extensibility is strong.

Accompanying drawing explanation

Fig. 1 is the structural drawing of on-chip integration system.

Fig. 2 is the structural drawing of embodiment of the present invention bus arbiter.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, specific embodiment is described in detail.

As shown in Figure 1, a kind of on-chip integration system of the embodiment of the present invention comprises bus arbiter, multiple functional module and multiple memory module.Described multiple memory module can be the memory devices such as ROM, SRAM, NORFLASH, SDRAM, APBBUS.Described multiple functional module accesses described multiple memory module by bus arbiter.

As shown in Figure 2, bus arbiter comprises module protocol interface, storer arbitration modules, bus switch module and memory interface.

Puppy parc required for functional module is connected with bus arbiter by module protocol interface, as AHB, AHB_Lite, AXI, AXI_Lite, APB, OCP etc. resolve to the protocol bus of internal unity, and the information comprising burst transfer has the start address of burst transfer, the transmission length of burst transfer information, the read-write type of burst transfer information, the access storage class of burst transfer, the additional information (as unroll transmission or incremental transmission) of burst transfer.Module protocol interface waits for the ED signal of institute access storer feedback, and using handshake that this signal terminates as function module data.

The request of access of storer arbitration modules to functional module access storer makes arbitration.When multiple functional module initiates request of access to a certain storer, this memory access authority, according to the selection strategy of setting, is authorized the request of access of wherein some functional modules by storer arbitration modules.

The logical consequence that bus switch module is arbitrated according to storer, the protocol bus of the internal unity sent by the interface of authorized functional module is switched to memory interface.

When being configured bus arbiter, according to the structure of above-mentioned bus arbiter, for module protocol interface, storer arbitration modules, bus switch module and memory interface arrange different configuration files respectively.

For module protocol interface, need to arrange various protocols interface sub-module: as the protocol interface submodule, AXI protocol interface submodule etc. of AHB.

For storer arbitration modules, only need design storer arbitration modules, but its receptible functional module request of access number can pass through parameter configuration

For bus switch module, only need design bus switch module, but the unified protocol bus number of its receptible inside modules can pass through parameter configuration

For memory interface, need to design multiple memory interface submodule: as interface control module, the interface control module of SRAM, the interface control module etc. of SDRAM of ROM.

In automatic generating configuration file, can the agreement (AHB, AXI etc.) of the number of pre-configured functional module, functional module and bus arbiter and memory interface type (ROM, SRAM, SDRAM etc.).Just modules can be connected into complete bus arbiter unit by script, meanwhile, the supporting test vector generating correspondence.

The dirigibility of bus arbiter bus of the present invention is high, can adapt to multiple different bus agreement and multiple memorizers, portable and extensibility is strong.For the interface optimization of a certain type, can be directly effective to all same kind interfaces of example.System maintenance debugging is also simpler.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. a bus arbiter, for on-chip integration system, is characterized in that, this bus arbiter comprises module protocol interface, storer arbitration modules, bus switch module and memory interface;

Puppy parc required for multiple functional module is connected with bus arbiter by module protocol interface resolves to the protocol bus of internal unity, described module protocol interface comprises protocol interface submodule and the AXI protocol interface submodule of AHB, described module protocol interface waits for the ED signal of institute's access storer feedback, and using handshake that this signal terminates as function module data;

The request of access of storer arbitration modules to multiple functional module access storer makes arbitration;

The information of the burst transfer that memory interface obtains according to the switch logic of bus switch module, converts the bus protocol that storer needs to by the protocol information of functional module,

The information of described burst transfer comprises the start address of burst transfer, the transmission length of burst transfer information, the read-write type of burst transfer information, the access storage class of burst transfer, the additional information of burst transfer, described memory interface comprises the interface control module of the interface control module of ROM, the interface control module of SRAM and SDRAM.