CN103152165A - Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof - Google Patents
Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof Download PDFInfo
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Abstract
The invention discloses a field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and an implementing method thereof. The AES processor comprises an interface storage area buffer module, a control module, an AES encryption and decryption module, a read-only memory lookup table module, a register module and an output module. The implementing method for the processor comprises the following steps: 1, initializing a data table; 2, performing initial setting; 3, receiving data; 4, reading the data; 5, selecting a data processing mode; 6, judging whether the encryption and decryption are finished; and 7, outputting a result. The invention mainly solves the problems that an AES processor is controlled complicatedly and modules have low portability, reliability, safety and processing speed in the prior art; and an improved algorithm and a lookup table-based method are used. The AES processor has all levels of structures which are fixed, is simple in control logic, comprises the modules with high portability, is suitable to be implemented in a singlechip FPGA, and has the characteristics of high speed and high accuracy.
Description
Technical field
The invention belongs to communication technical field, further relate in field of information security technology based on field programmable gate array (Field Programmable Gate Array, FPGA) ultrahigh speed Advanced Encryption Standard (Advanced Encryption Standard, AES) processor and its implementation.The present invention has utilized the flexibility of FPGA programming and the reliability of hardware fully in the situation that the assurance processing speed is higher and the resource occupation minimum, has realized the safety encipher to data and information.The present invention can be widely applicable for smart card (smart card), and cell phone bank system carries out senior encryption and decryption in the ATM cash dispenser, to guarantee the safety of data and information.
Background technology
Along with the development of the communication technology, communication environment is increasingly sophisticated, compares with traditional software enciphering method, and it is fast that hardware encipher has computational speed, and cost is low, and efficient is high; Dependable performance, fail safe is good, is difficult for by advantages such as attacks.The superior point of FPGA technology is exactly to utilize strong design tool to shorten the construction cycle, and abundant Resources on Chip is provided, can parallel data processing, easily realize pipeline organization, and improve the flexibility of design, and upgrading is convenient, reduces design cost.Rely on these advantages, the fpga chip that employing speed is faster, degree of parallelism is larger realizes that AES has become inexorable trend.
Traditional AES processor is fully based on aes algorithm, by carrying out computing with taking turns.And in each of encrypting is taken turns computing again strictly according to key add, byte is replaced, row displacement, row mix four steps and carry out successively, in each of deciphering is taken turns computing again strictly according to the displacement of driving in the wrong direction, contrary byte replace, key adds, contrary row mix four steps and carry out successively.Although this mode is being widely used in application specific processor in real time, but in each that realizes this mode processor is taken turns computing, each is taken turns a large amount of displacements, multiplication, XOR in computing, thereby difficulty and complexity that the address is controlled have been increased, the transplantability of its module is lower, take a large amount of resource of FPGA, increase the expense of processor.
patent " a kind of method and device of realizing the AES the encryption and decryption " (application number 201210236963.2 of Jiyi Sci. ﹠ Tech.'s application, application publication number CN102801519A, be 2012.11.28 in open day) be to design the AES processor with traditional method, in each of encryption and decryption is taken turns computing, carry out computing in strict accordance with four steps of conventional method, this patent is by having used the result of identical register buffer memory encryption and decryption wheel computing, and use identical logic realization S box and contrary S box computing, realized reducing the purpose of chip area and power consumption.There are three weak points in this patent application.One, the optimization method that this patent does not propose encryption and decryption causes the encryption and decryption step complicated.Its two, this patent do not avoid to S box, contrary S box and row mix, the calculating of contrary row blend step, cause the encryption and decryption process can not guarantee correctness and the fail safe of data.Its three, this patent will be expanded initial key, and carries out computing in strict accordance with four traditional steps, causes the speed of encryption and decryption data that certain restriction is arranged, thereby can not satisfy well the needs of rate applications occasion.
the people's such as Liakot professor Ali paper " Design of an ultra high speed AES processor for next generation IT security " (Liakot Ali, Ishak Aris, Fakir Sharif Hossain, Niranjan Roy.Design of an ultra high speed AES processor for next generation IT security[A] .Computers and Electrical Engineering, 2011, 37:1160-1170.) a kind of AES processor device proposed, this AES processor device adopts the EP2SGX30DF780C3 device of altera corp to realize the encryption rate of 36.16Gbps.The encrypting module of this AES processor device is fully based on look-up tables'implementation, and in each of deciphering module is taken turns computing, or replace in strict accordance with traditional retrograde displacement (InShiftRow), contrary byte that (InSubBytes), contrary row mix (InMixcolumn), key adds (AddRoundKey) four steps and carries out computing.There are following three weak points in this piece paper: one, to encrypting, better optimization method is not proposed, and when the AES processor that causes this scheme to realize is encrypted data, 21 clock cycle delays are arranged between input and output; Its two, the memory module of AES processor is not done further improvement, cause the AES processor read-only memorys (Read Only Memory, ROM) that taken 4K extraly more; Its three, the internal structure of AES processor deciphering module is not done further improvement, cause the deciphering module more complicated.
Summary of the invention
The object of the invention is to overcome above-mentioned the deficiencies in the prior art, solved that traditional AES processor control logic is complicated, grow, take the more problem of resource time of delay between input and output, proposed that a kind of computational speed is faster, resource utilization is higher, structure simpler super high-speed A ES processor and its implementation based on FPGA, to improve its practical performance.
The present invention is based on the super high-speed A ES processor of FPGA, comprise interface memory block buffer module, control module, AES encryption and decryption module, read-only memory look-up table means, register module, output module, described interface memory block buffer module, AES encryption and decryption module are connected with control bus by data/address bus; Described read-only memory look-up table means, register module, control module, output module are connected with control bus by data/address bus; Wherein:
Interface memory block buffer module is used for the data on temporary transient storage input data bus;
Control module is for the transfer of data between the arithmetic element of controlling and coordinate AES encryption and decryption module, read-only memory look-up table means, register module and control output encrypted result or decrypted result;
AES encryption and decryption module is respectively used to Standard Encryption expressly, the standard of ciphertext is deciphered;
The read-only memory look-up table means is used for the ephemeral data of storage encryption and decryption process, and the result of searching is delivered on data/address bus;
Register module is used for the expanded keys of storage encryption and decryption process, and according to the control number of controller, the data of register is delivered on data/address bus;
Output module is used for selecting output to encrypt or decrypted result from encrypting module, deciphering module.
The implementation method of super high-speed A ES processor of the present invention comprises the steps:
(1) initialization data table
According to the data of the expanded keys register of byte substitution table, contrary byte substitution table and encrypting module, calculate and search vector table, search the expanded keys register data of contrary column vector table and deciphering module.
(2) initial setting up
The user calculates the clock frequency of system works according to the speedometer of deal with data, the clock of this frequency is connected to the clock port of processor, makes processor be in reset mode for reset signal of system.
(3) receive data
The input data sequence of intending encryption and decryption is temporary to interface memory block buffer module, under the control of control module, the data sequence of first round arithmetic element receiving interface memory block buffer module output.The operation times of encryption and decryption module is set as 1, completes initialization operation.
(4) reading out data
Under the control of control module, will read out with expanded keys register data corresponding to operation times in expanded keys register data corresponding with operation times in encrypting module and deciphering module.
(5) select the processing mode of data
5a) judge whether operation times equals 1, if so, execution in step 5b) operation, otherwise, execution in step 5c) operation;
5b) read the expanded keys register data corresponding with operation times from encrypting module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module;
5c) read the expanded keys register data corresponding with operation times from encrypting module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching the output of column vector table corresponding to operation times, obtain the result of computing corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching contrary column vector table output corresponding to operation times, obtain the result of computing corresponding with operation times in deciphering module.
(6) judge whether encryption and decryption is completed
Judge whether operation times equals 11, if so, complete encryption and decryption data, the operation of execution in step (7); Otherwise, do not complete encryption and decryption data, operation times adds 1, the operation of execution in step (4).
(7) Output rusults
Output module receives the result from the encryption and decryption module arithmetic, under the control of control module, selects output encrypted result or decrypted result.
The present invention compared with prior art has following characteristics:
First, because encryption and decryption module in the present invention all adopts algorithm after optimization, in algorithm after optimization, one takes turns computing two steps is arranged at the most, can effectively overcome in prior art encryption and decryption module the 2nd and take turns the portable poor problem of complexity, module that all will carry out FOUR EASY STEPS in taking turns computing to the 10th each of taking turns, make store control logic of the present invention simple, module portable high.
Second, because encryption and decryption module in the present invention all adopts algorithm after optimization, the internal structure of encryption and decryption module is identical, can effectively overcome the problem of deciphering module complexity in prior art, make internal structure of the present invention symmetrical, facilitate the placement-and-routing of internal element.
The 3rd, because the present invention designs based on look-up table fully, the look-up table of curing has guaranteed that system data can not be modified easily, can effectively overcome the problem that prior art easily is tampered when practicality, makes the present invention improve reliability; In the encryption and decryption module, the expanded keys register data is different, and the present invention is asymmetric encryption seemingly, but its essence is symmetric cryptography, makes the present invention improve security performance.By searching the look-up table of curing, can effectively overcome prior art and the problem that deal with data is made mistakes easily occur when practicality, make the present invention guarantee the validity of system.
The 4th, because the present invention designs based on hardware language fully, the simplification of hardware language makes the present invention complete first group of data encrypting and deciphering and only wants 10 clock delays, effectively overcome and completed 21 clock delay problems of first group of data encrypting and deciphering needs in prior art, made the present invention that better real-time be arranged.
The 5th, because the present invention uses the inner abundant register resources of FPGA fully, overcome effectively in the prior art, the AES processor has taken the problems of 4K ROM extraly, make the present invention improve the cost performance of resource utilization ratio and AES processor.
Description of drawings
Fig. 1 is the overall structure block diagram of processor of the present invention;
Fig. 2 is processor encryption and decryption modular structure block diagram of the present invention;
Fig. 3 is that one of processor encryption and decryption module of the present invention is taken turns the computing block diagram of optimizing structure;
Fig. 4 is the flow chart of processor implementation method of the present invention;
Fig. 5 is processor encryption and decryption simulation result figure of the present invention.
Embodiment:
The present invention will be further described below in conjunction with accompanying drawing.
Overall structure with reference to 1 pair of processor of the present invention of accompanying drawing is further described.
Processor of the present invention comprises interface memory block buffer module, control module, AES encryption and decryption module, read-only memory look-up table means, register module, output module; Interface memory block buffer module, AES encryption and decryption module are connected with control bus by data/address bus; Read-only memory look-up table means, register module, control module, output module are connected with control bus by data/address bus.
Interface memory block buffer module is used for the data on temporary transient storage input data bus.Interface memory block buffer module comprises four random access memory rams that are arranged on encryption and decryption module front end buffering area; 32 input data buss of each RAM, output data bus are connected with external data input data line, encryption and decryption module input data line respectively.In the embodiment of the present invention, each clock of AES processor can be processed 128 Bit datas, if the data of outside input are too fast, and AES processor possibility obliterated data, deal with data effectively; If the data of outside input are slower, FPGA can not get sufficient utilization.
And peripheral hardware operating frequency with FPGA working clock frequency different this two contradictions different with AES encryption and decryption data processing width for the solution input data bus, AES processor adopting interface of the present invention memory block buffer module realizes the data of outside input and the temporary transient storage of inner pending data, like this when the input data are too fast, guarantee that data do not lose, when input data rate was slower, FPGA can be utilized fully.AES processor of the present invention gets up four RAM side by side, and the bus of each RAM output accounts for 32, transfers 128 Bit datas of serial under 128 clocks to 128 Bit datas parallel under a clock.
Control module is for the transfer of data between the arithmetic element of controlling and coordinate AES encryption and decryption module, read-only memory look-up table means, register module and control output encrypted result or decrypted result.
Under the control of control module, after reset signal (reset) is effective, just can carry out normal encryption and decryption work; When being high level, be encryption mode when control signal (en_de) at this moment, the enciphered data on output bus (data_out) is always than late 10 clocks of the data of input bus (text); When being low level, be decryption mode when control signal (en_de) at this moment, the data decryption on output bus (data_out) is always than late 10 clocks of the data of input bus (text).
Encryption and decryption module with reference to 2 pairs of processors of the present invention of accompanying drawing is further described.
AES encryption and decryption module is respectively used to Standard Encryption expressly, the standard of ciphertext is deciphered; The input of 128 bits of AES encryption and decryption module, output port are connected with the output data line of interface memory block buffer module, the input data line of output control module respectively; AES encryption and decryption module comprises that 11 of encryption takes turns 11 of arithmetic element and deciphering and take turns arithmetic element; 11 of encryption and decryption is taken turns arithmetic element all with the mode cascade of streamline.
AES encrypting module the 1st is taken turns arithmetic element and is only had key to add a step, the 2nd of AES encrypting module takes turns, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns and the 10th take turns arithmetic element include search the column vector table, key adds two steps; The 11th round arithmetic element of AES encrypting module comprises that byte is replaced, key adds two steps; AES deciphering module the 1st is taken turns arithmetic element and is only had key to add a step, and the 2nd of AES deciphering module takes turns, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns and the 10th take turns arithmetic element and include and search contrary column vector table key and add two steps; The 11th round arithmetic element of AES deciphering module comprises that contrary byte is replaced, key adds two steps; The internal structure of encrypting module and deciphering module is identical.
With reference to one taking turns Optimization Steps and be further described in the encryption and decryption module of 3 pairs of processors of the present invention of accompanying drawing.
In the cryptographic algorithm of prior art, each is taken turns calculating and all is based on state matrix, and each takes turns mathematical expression form such as the following table 1 of calculating, and wherein i, j are respectively line number, the columns in the byte substitution table; b
ij, S[a
ij] be that i in the byte substitution table is capable, the j column data; c
0j, c
1j, c
2j, c
3jRepresent respectively the 1st row j row in state matrix, the 2nd row j row, the 3rd row j row, the 4th data corresponding to row j row; d
0j, d
1j, d
2j, d
3jRespectively c
0j, c
1j, c
2j, c
3jData after multiplying each other with contrary mixed linear transformation matrix, k
0j, k
1j, k
2j, k
3j, be the 1st row j row, the 2nd row j row, the 3rd row j row, the 4th data corresponding to row j row in the last round key state matrix.
Every mathematical expression form of taking turns computing in the cryptographic operation of table 1 prior art
Four-step calculation step to upper table 1 merges, and the expression formula that the process key adds after step is
Expressed by four vectors through the result that key adds after step, search by designing four that the column vector table replaces in encrypting module that every byte of taking turns computing is replaced, row displacement and row mix the operation of three steps.
set the front state matrix of retrograde displacement of (a) in accompanying drawing 3, state matrix after retrograde displacement, the key state matrix, state matrix after contrary byte is replaced, state matrix after key adds, the state matrix that contrary row mix is respectively A, B, K, C, D and E, (b) state matrix before the retrograde displacement in, state matrix after retrograde displacement, the key state matrix, the key state matrix, state matrix after contrary byte is replaced, the state matrix that contrary row mix, state matrix after key adds is respectively A, B, K`, C`, D` and E`, following relation is arranged between matrix:
E`＝R?C`＝C
In accompanying drawing 3, (a), Fig. 3 (b) and Fig. 3 (c) are optimized to key with four step computings of taking turns in the prior art deciphering module and add and search contrary column vector table two step.Accompanying drawing 3 (d) and Fig. 3 (e) are optimized to key with four step computings of taking turns in the prior art encrypting module and add and search column vector table two step.In algorithm after optimization, one in deciphering module taken turns one in calculation step and encrypting module, and to take turns calculation step just the same.Deciphering module is the same with encrypting module, searches contrary column vector table and replaces in deciphering module every contrary byte of taking turns computing replace, drive in the wrong direction displacement and contrary row to mix for three steps and operate by designing four.
The read-only memory look-up table means is used for the ephemeral data of storage encryption and decryption process, and the result of searching is delivered on data/address bus; The byte that comprises encrypting module is replaced look-up table, is searched the column vector table, and the byte of deciphering module is contrary replaces look-up table and search contrary column vector table four kind of look-up table; Wherein search the column vector table and comprise and search column vector table 1, search column vector table 2, search column vector table 3, search column vector table 4, search contrary column vector table and comprise and search contrary column vector table 1, search contrary column vector table 2, search contrary column vector table 3, search contrary column vector table 4.Search the column vector table in the read-only memory look-up table means of AES processor, search the memory space that contrary column vector table occupies respectively 1152K.
Byte replace the contrary input of replacing look-up table of look-up table, byte, output port respectively with AES encryption and decryption module in the 10th output of taking turns arithmetic element, AES encryption and decryption module the input of 11th round arithmetic element be connected; Take turns in the 2nd of AES encryption and decryption module, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns, the 10th take turns arithmetic element, each is taken turns search column vector table and the output of searching contrary column vector table, input port by data wire respectively with AES encryption and decryption module in the input of previous round arithmetic element, AES encryption and decryption module the output of last round of arithmetic element be connected.The byte substitution table of AES processor, contrary byte substitution table occupy respectively the 32K memory space.
Register module is used for the expanded keys of storage encryption and decryption process, and according to the control number of controller, the data of register is delivered on data/address bus; Register module comprises 11 expanded keys registers of encrypting module and 11 expanded keys registers of deciphering module; Each of encrypting module take turns expanded keys register and deciphering module each take turns the expanded keys register and be connected with the input port that each takes turns arithmetic element respectively by data/address bus.The register of AES processor encrypting module, the register of encrypting module occupy respectively 1408 bits.
Output module is used for selecting output to encrypt or decrypted result from encrypting module, deciphering module.256 bit input ports of output module are connected with 128 Bit data lines of encrypting module output and 128 Bit data lines of deciphering module output respectively; The output of 128 bits of output module is connected with the output of processor by data/address bus.
The AES processor has following I/O interface, as table 2.
The I/O interface of table 2AES processor
| clk | Synchronised clock |
| reset | Asynchronous reset |
| en_de | The encryption and decryption model selection |
| text | The data input |
| data_out | Data output |
Implementation method with reference to 4 pairs of processors of the present invention of accompanying drawing is described further.
Step 1. initialization data table
According to the data of the expanded keys register of byte substitution table, contrary byte substitution table and encrypting module, calculate and search vector table, search the expanded keys register data of contrary column vector table and deciphering module.
Need initialized tables of data that byte substitution table, contrary byte substitution table are arranged, search the column vector table, search contrary column vector table, the register data of encrypting module and the register data of deciphering module.
Wherein data such as the table 3 of byte substitution table:
Data in table 3 byte substitution table
| ? | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |
| 0 | 63 | 7c | 77 | 7b | f2 | 6b | 6f | c5 | 30 | 01 | 67 | 2b | fe | d7 | ab | 76 |
| 1 | ca | 82 | c9 | 7d | fa | 59 | 47 | f0 | ad | d4 | a2 | af | 9c | a4 | 72 | c0 |
| 2 | b7 | fd | 93 | 26 | 36 | 3f | f7 | cc | 34 | a5 | e5 | f1 | 71 | d8 | 31 | 15 |
| 3 | 04 | c7 | 23 | c3 | 18 | 96 | 05 | 9a | 07 | 12 | 80 | e2 | eb | 27 | b2 | 75 |
| 4 | 09 | 83 | 2c | 1a | 1b | 6e | 5a | a0 | 52 | 3b | d6 | b3 | 29 | e3 | 2f | 84 |
| 5 | 53 | d1 | 00 | ed | 20 | fc | b1 | 5b | 6a | cb | be | 39 | 4a | 4c | 58 | cf |
| 6 | d0 | ef | aa | fb | 43 | 4d | 33 | 85 | 45 | f9 | 02 | 7f | 50 | 3c | 9f | a8 |
| 7 | 51 | a3 | 40 | 8f | 92 | 9d | 38 | f5 | bc | b6 | da | 21 | 10 | ff | f3 | d2 |
| 8 | cd | 0c | 13 | ec | 5f | 97 | 44 | 17 | c4 | a7 | 7e | 3d | 64 | 5d | 19 | 73 |
| 9 | 60 | 81 | 4f | dc | 22 | 2a | 90 | 88 | 46 | ee | b8 | 14 | de | 5e | 0b | db |
| A | e0 | 32 | 3a | 0a | 49 | 06 | 24 | 5c | c2 | d3 | ac | 62 | 91 | 95 | e4 | 79 |
| B | e7 | c8 | 37 | 6d | 8d | d5 | 4e | a9 | 6c | 56 | f4 | ea | 65 | 7a | ae | 08 |
| C | ba | 78 | 25 | 2e | 1c | a6 | b4 | c6 | e8 | dd | 74 | 1f | 4b | bd | 8b | 8a |
| D | 70 | 3e | b5 | 66 | 48 | 03 | f6 | 0e | 61 | 35 | 57 | b9 | 86 | c1 | 1d | 9e |
| E | e1 | f8 | 98 | 11 | 69 | d9 | 8e | 94 | 9b | 1e | 87 | e9 | ce | 55 | 28 | df |
| F | 8c | a1 | 89 | 0d | bf | e6 | 42 | 68 | 41 | 99 | 2d | 0f | b0 | 54 | bb | 16 |
With in table 3 00 and data instance introduction corresponding to 0F search the generation step of column vector table data, first find 00 and data corresponding to 0F be respectively 63 and 76, with 63,76 respectively with [02,01,01,03]
TMultiply each other, with the data [C66363A5] that obtain
T, [EC76769A]
TStore respectively memory space corresponding to 00h, 0Fh of searching column vector table 1 into, in the same way other 254 data in table 3 are also generated corresponding data, complete the initialization of searching vector table 3 data.
Again with 256 data in table 3 respectively with [03,02,01,01]
T, [01,03,02,01]
T[01,01,03,02]
TMultiply each other, the acquisition data are stored into respectively search column vector table 2, search column vector table 3 and search the memory space of column vector table 4 correspondence, complete 4 initialization of searching column vector table data.
Wherein, data such as the table 4 of contrary byte substitution table:
Data in the contrary byte substitution table of table 4
| ? | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |
| 0 | 52 | 09 | 6a | d5 | 30 | 36 | a5 | 38 | bf | 40 | a3 | 9e | 81 | f3 | d7 | fb |
| 1 | 7c | e3 | 39 | 82 | 9b | 2f | ff | 87 | 34 | 8e | 43 | 44 | c4 | de | e9 | cb |
| 2 | 54 | 7b | 94 | 32 | a6 | c2 | 23 | 3d | ee | 4c | 95 | 0b | 42 | fa | c3 | 4e |
| 3 | 08 | 2e | a1 | 66 | 28 | d9 | 24 | b2 | 76 | 5b | a2 | 49 | 6d | 8b | d1 | 25 |
| 4 | 72 | f8 | f5 | 64 | 86 | 68 | 98 | 16 | d4 | a4 | 5c | cc | 5d | 65 | b6 | 92 |
| 5 | 6c | 70 | 48 | 50 | fd | ed | b9 | da | 5e | 15 | 46 | 57 | a7 | 8d | 9d | 84 |
| 6 | 90 | d8 | ab | 00 | 8c | bc | d3 | 0a | f7 | e4 | 58 | 05 | b8 | b3 | 45 | 06 |
| 7 | d0 | 2c | 1e | 8f | ca | 3f | 0f | 02 | c1 | af | bd | 03 | 01 | 13 | 8a | 6b |
| 8 | 3a | 91 | 11 | 41 | 4f | 67 | dc | ea | 97 | f2 | cf | ce | f0 | b4 | e6 | 73 |
| 9 | 96 | ac | 74 | 22 | e7 | ad | 35 | 85 | e2 | f9 | 37 | e8 | 1c | 75 | df | 6e |
| A | 47 | f1 | 1a | 71 | 1d | 29 | c5 | 89 | 6f | b7 | 62 | 0e | aa | 18 | be | 1b |
| B | fc | 56 | 3e | 4b | c6 | d2 | 79 | 20 | 9a | db | c0 | fe | 78 | cd | 5a | f4 |
| C | 1f | dd | a8 | 33 | 88 | 07 | c7 | 31 | b1 | 12 | 10 | 59 | 27 | 80 | ec | 5f |
| D | 60 | 51 | 7f | a9 | 19 | b5 | 4a | 0d | 2d | e5 | 7a | 9f | 93 | c9 | 9c | ef |
| E | a0 | e0 | 3b | 4d | ae | 2a | f5 | b0 | c8 | eb | bb | 3c | 83 | 53 | 99 | 61 |
| F | 17 | 2b | 04 | 7e | ba | 77 | d6 | 26 | e1 | 69 | 14 | 63 | 55 | 21 | 0c | 7d |
With in table 4 00 and data instance introduction corresponding to 0F search the generation step of contrary column vector table data, first find 00 and element corresponding to 0F be respectively 52 and FB, with 52, FB respectively with [0E, 09,0D, 0B]
TMultiply each other, with the data [51F4A750] that obtain
T, [B562A38F]
TStore respectively memory space corresponding to 00h, 0Fh of searching contrary column vector table 1 into, in the same way other 254 data in table 4 are also generated corresponding data, complete the initialization of searching contrary column vector table 1.
Again with 256 data in table 4 respectively with [0B, 0E, 09,0D]
T, [0D, 0B, 0E, 09]
T, [09,0D, 0B, 0E]
TMultiply each other, the acquisition data stored respectively search contrary column vector table 2, search contrary column vector table 3, search the memory space of contrary column vector table 4 correspondence, complete 4 initialization of searching contrary column vector table data.
The data of initial key and expanded keys register such as following table 5 in encrypting module:
The data of initial key and expanded keys register in table 5 encrypting module
| First round key | 2b，7e，15，16，28，ae，d2，a6，ab，f7，15，88，09，cf，4f，3c |
| The second round key | a0，fa，fe，17，88，54，2c，b1，23，a3，39，39，2a，6c，76，05 |
| The third round key | f2，c2，95，f2，7a，96，b9，43，59，35，80，7a，73，59，f6，7f |
| The fourth round key | 3d，80，47，7d，47，16，fe，3e，1e，23，7e，44，6d，7a，88，3b |
| The 5th round key | ef，44，a5，41，a8，52，5b，7f，b6，71，25，3b，db，0b，ad，00 |
| The 6th round key | d4，d1，c6，f8，7c，83，9d，87，ca，f2，b8，bc，11，f9，15，bc |
| The 7th round key | 6d，88，a3，7a，11，0b，3e，fd，db，f9，86，41，ca，00，93，fd |
| The 8th round key | 4e，54，f7，0e，5f，5f，c9，f3，84，a6，4f，b2，4e，a6，dc，4f |
| The 9th round key | ea，d2，73，21，b5，8d，ba，d2，31，2b，f5，60，7f，8d，29，2f |
| The tenth round key | ac，77，66，f3，19，fadc，21，28，d1，29，41，57，5c，00，6e |
| The 11 round key | d0，14，f9，a8，c9，ee，25，89，e1，3f，0c，c8，b6，63，0c，a6 |
in above table 5, the second round key is the generation step that example is introduced the expanded keys register data of deciphering module, to be converted to vector [0E against mixed linear transformation matrix A, 09, 0D, 0B, 0B, 0E, 09, 0D, 0D, 0B, 0E, 09, 09, 0D, 0B, 0E], again with the second round key data [a0, fa, fe, 17, 88, 54, 2c, b1, 23, a3, 39, 39, 2a, 6c, 76, 05] with vector [0E, 09, 0D, 0B, 0B, 0E, 09, 0D, 0D, 0B, 0E, 09, 09, 0D, 0B, 0E] multiply each other, with the data [2b that obtains, 37, 08, a7, f2, 62, d4, 05, bc, 3e, bd, bf, 4b, 61, 7d, 62] store in the second round key register of deciphering module, generate the third round of deciphering module with same method, fourth round, the 5th takes turns, the 6th takes turns, the 7th takes turns, the 8th takes turns, the 9th takes turns, the tenth round key register data.The first round, the 11 round key data are directly stored in the first round, the 11 round key register of deciphering module, obtain deciphering module initial key and expanded keys register data such as table 6.Above-mentioned contrary mixed linear transformation matrix
Table 6 deciphering module initial key and expanded keys register data
| First round key | 2b，7e，15，16，28，ae，d2，a6，ab，f7，15，88，09，cf，4f，3c |
| Second takes turns decruption key | 2b，37，08，a7，f2，62，d4，05，bc，3e，bd，bf，4b，61，7d，62 |
| The third round decruption key | cc，75，05，eb，3e，17，d1，ee，82，29，6c，51，c9，48，11，33 |
| The fourth round decruption key | 7c，1f，13，f7，42，08，c2，19，c0，21，ae，48，09，69，bf，7b |
| The 5th takes turns decruption key | 90，88，44，13，d2，80，86，0a，12，a1，28，42，1b，c8，97，39 |
| The 6th takes turns decruption key | 6e，a3，0a，fc，bc，23，8c，f6，ae，82，a4，b4，b5，4a，33，8d |
| The 7th takes turns decruption key | 6e，fc，d8，76，d2，df，54，80，7c，5d，fD，34，c9，17，c3，b9 |
| The 8th takes turns decruption key | 12，c0，76，47，c0，1f，22，c7，bc，42，d2，f3，75，55，11，4a |
| The 9th takes turns decruption key | df，7d，92，5a，1f，62，b0，9d，a3，20，62，6e，d6，75，73，24 |
| The tenth takes turns decruption key | 0c，7b，5a，63，13，19，ea，fe，b0，39，88，90，66，4c，fb，b4 |
| The 11 round key | d0，14，f9，a8，c9，ee，25，89，e1，3f，0c，c8，b6，63，0c，a6 |
Step 2. initial setting up
The present invention completes test on the XILINX spant6 of company family chip XC6SLX75, adopted the system clock of 320M, first low level is added in reset signal (reset) end, and the AES processor resets.
Step 3. receive data
With test data text1=128 ' h3243f6a8885a308d313198a2e0370734;
text2＝128′hb7aae03e900650a291c12453310530eb；
text3＝128′h3243f6a8885a308d313198a2e0370734；
text4＝128′hb7aae03e900650a291c12453310530eb；
Be input to successively signal end (text).After data stabilization to be entered, reset signal (reset) set high level; Enable signal (en_de) is set to high level; The operation times of encryption and decryption module is set as 1, completes initialization operation.
Step 4. reading out data
After initialization step was completed, the AES processor will be read with expanded keys register data corresponding to operation times in expanded keys register data corresponding with operation times in encrypting module and deciphering module under the control of control module.
Step 5. is selected the processing mode of data
5a) judge whether operation times equals 1, if so, execution in step 5b) operation, otherwise, execution in step 5c) operation;
5b) read the expanded keys register data corresponding with operation times from encrypting module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module;
5c) read the expanded keys register data corresponding with operation times from encrypting module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching the output of column vector table corresponding to operation times, obtain the result of computing corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching contrary column vector table output corresponding to operation times, obtain the result of computing corresponding with operation times in deciphering module.
Step 6. judges whether encryption and decryption is completed
Judge whether operation times equals 11, if so, complete encryption and decryption data, the operation of execution in step 7; Otherwise, do not complete encryption and decryption data, operation times adds 1, the operation of execution in step 4.
Step 7. Output rusults
Output module receives the result from the encryption and decryption module arithmetic, under the control of control module, selects output encrypted result or decrypted result.
Analogous diagram below in conjunction with accompanying drawing 5 is further described effect of the present invention.
1, simulated conditions
The emulation experiment of processor of the present invention is completed test on the XILINX spant6 of company family chip XC6SLX75, use ISE and Modelsim software and carried out emulation.Adopt the system clock of 320M, first low level is added in reset signal (reset) end, the AES processor resets.
2, emulation content
The data of accepting in step 3 are carried out encryption and decryption to be processed.Four groups of data of input are respectively
text1＝128′h3243f6a8885a308d313198a2e0370734；
text2＝128′hb7aae03e900650a291c12453310530eb；
text3＝128′h3243f6a8885a308d313198a2e0370734；
text4＝128′hb7aae03e900650a291c12453310530eb；
3, simulated effect analysis
The data of input are after the AES processor is processed, and on input port, first group of data the 10th clock afterwards exported the encrypted result Cipher1 of text1; The encrypted result Cipher2 of second group of data the 10th clock output text2 afterwards on input port; The encrypted result Cipher3 of the 3rd group of data the 10th clock output text3 afterwards on input port; The decrypted result Cipher4 of the 4th group of data the 10th clock output text4 afterwards on input port.Cipher1, Cipher2, Cipher3 and Cipher4 are respectively 128 ' h3925841d02dc09fbdc118597196a0b32,128 ' h9b6380c4ccaff4b55acd536d301da434,128 ' h3925841d02dc09fbdc118597196a0b32,128 ' h eba16c704daf8be4329eb31c16754d20.
Observe from the emulated data that obtains, each clock of processor of the present invention is encrypted or deciphers one group of 128 Bit data, can reach the processing speed of 40.96Gbps, illustrates that processor of the present invention has higher processing speed than prior art.128 Bit datas of first group of output only than slow 10 clocks of 128 Bit datas of first group of input, illustrate that processor of the present invention has reached the effect of desired design, has better real-time than prior art; The encryption and decryption result is entirely true, illustrates that processor of the present invention has guaranteed the reliability of system.
Claims (10)
1. super high-speed A ES processor based on FPGA, comprise interface memory block buffer module, control module, AES encryption and decryption module, read-only memory look-up table means, register module, output module, described interface memory block buffer module, AES encryption and decryption module are connected with control bus by data/address bus; Described read-only memory look-up table means, register module, control module, output module are connected with control bus by data/address bus; Wherein:
Described interface memory block buffer module is used for the data on temporary transient storage input data bus;
Described control module is for the transfer of data between the arithmetic element of controlling and coordinate AES encryption and decryption module, read-only memory look-up table means, register module and control output encrypted result or decrypted result;
Described AES encryption and decryption module is respectively used to Standard Encryption expressly, the standard of ciphertext is deciphered;
Described read-only memory look-up table means is used for the ephemeral data of storage encryption and decryption process, and the result of searching is delivered on data/address bus;
Described register module is used for the expanded keys of storage encryption and decryption process, and according to the control number of controller, the data of register is delivered on data/address bus;
Described output module is used for selecting output to encrypt or decrypted result from encrypting module, deciphering module.
2. the super high-speed A ES processor based on FPGA according to claim 1, is characterized in that, described interface memory block buffer module comprises four random access memory rams that are arranged on encryption and decryption module front end buffering area; 32 input data buss of each RAM, output data bus are connected with external data input data line, encryption and decryption module input data line respectively.
3. the super high-speed A ES processor based on FPGA according to claim 1, it is characterized in that, the input of 128 bits of described AES encryption and decryption module, output port are connected with the output data line of interface memory block buffer module, the input data line of output control module respectively; AES encryption and decryption module comprises that 11 of encryption takes turns 11 of arithmetic element and deciphering and take turns arithmetic element; 11 of encryption and decryption is taken turns arithmetic element all with the mode cascade of streamline; AES encrypting module the 1st is taken turns arithmetic element and is only had key to add a step, the 2nd of AES encrypting module takes turns, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns and the 10th take turns arithmetic element include search the column vector table, key adds two steps; The 11th round arithmetic element of AES encrypting module comprises that byte is replaced, key adds two steps; AES deciphering module the 1st is taken turns arithmetic element and is only had key to add a step, the 2nd of AES deciphering module takes turns, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns and the 10th take turns arithmetic element include search contrary column vector table, key adds two steps; The 11th round arithmetic element of AES deciphering module comprises that contrary byte is replaced, key adds two steps; The internal structure of encrypting module and deciphering module is identical.
4. the super high-speed A ES processor based on FPGA according to claim 1, it is characterized in that, described read-only memory look-up table means, the byte that comprises encrypting module is replaced look-up table, is searched the column vector table, and the byte of deciphering module is contrary replaces look-up table and search contrary column vector table four kind of look-up table; Wherein search the column vector table and comprise and search column vector table 1, search column vector table 2, search column vector table 3, search column vector table 4, search contrary column vector table and comprise and search contrary column vector table 1, search contrary column vector table 2, search contrary column vector table 3, search contrary column vector table 4; Byte replace the contrary input of replacing look-up table of look-up table, byte, output port respectively with AES encryption and decryption module in the 10th output of taking turns arithmetic element, AES encryption and decryption module the input of 11th round arithmetic element be connected; Take turns in the 2nd of AES encryption and decryption module, the 3rd take turns, the 4th take turns, the 5th take turns, the 6th take turns, the 7th take turns, the 8th take turns, the 9th take turns, the 10th take turns arithmetic element, each is taken turns search column vector table and the output of searching contrary column vector table, input port by data wire respectively with AES encryption and decryption module in the input of previous round arithmetic element, AES encryption and decryption module the output of last round of arithmetic element be connected.
5. the super high-speed A ES processor based on FPGA according to claim 1, is characterized in that, described register module comprises 11 expanded keys registers of encrypting module and 11 expanded keys registers of deciphering module; Each of encrypting module take turns expanded keys register and deciphering module each take turns the expanded keys register and be connected with the input port that each takes turns arithmetic element respectively by data/address bus.
6. the super high-speed A ES processor based on FPGA according to claim 1, is characterized in that, 256 bit input ports of described output module are connected with 128 Bit data lines of encrypting module output and 128 Bit data lines of deciphering module output respectively; The output of 128 bits of output module is connected with the output of processor by data/address bus.
7. based on the super high-speed A ES processor implementation method of FPGA, comprise the steps:
(1) initialization data table
According to the data of the expanded keys register of byte substitution table, contrary byte substitution table and encrypting module, calculate and search vector table, search the expanded keys register data of contrary column vector table and deciphering module;
(2) initial setting up
The user calculates the clock frequency of system works according to the speedometer of deal with data, the clock of this frequency is connected to the clock port of processor, makes processor be in reset mode for reset signal of system;
(3) receive data
The input data sequence of intending encryption and decryption is temporary to interface memory block buffer module, under the control of control module, the data sequence of first round arithmetic element receiving interface memory block buffer module output; Operation times setting side 1 with the encryption and decryption module completes initialization operation;
(4) reading out data
Under the control of control module, will read out with expanded keys register data corresponding to operation times in expanded keys register data corresponding with operation times in encrypting module and deciphering module;
(5) select the processing mode of data
5a) judge whether operation times equals 1, if so, execution in step 5b) operation, otherwise, execution in step 5c) operation;
5b) read the expanded keys register data corresponding with operation times from encrypting module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, give simultaneously the arithmetic element corresponding with operation times with the data of reading with the data of interface memory block buffer module output, obtain the operation result corresponding with operation times in encrypting module;
5c) read the expanded keys register data corresponding with operation times from encrypting module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching the output of column vector table corresponding to operation times, obtain the result of computing corresponding with operation times in encrypting module; Read the expanded keys register data corresponding with operation times from deciphering module, with the data of reading with give simultaneously the arithmetic element corresponding with operation times with the data of searching contrary column vector table output corresponding to operation times, obtain the result of computing corresponding with operation times in deciphering module;
(6) judge whether encryption and decryption is completed
Judge whether operation times equals 11, if so, complete encryption and decryption data, the operation of execution in step (7); Otherwise, do not complete encryption and decryption data, operation times adds 1, the operation of execution in step (4);
(7) Output rusults
Output module receives the result from the encryption and decryption module arithmetic, under the control of control module, selects output encrypted result or decrypted result.
8. the super high-speed A ES processing method based on FPGA according to claim 7, is characterized in that, the data of searching the column vector table in described step (1) obtain according to following steps:
The first step is set as 1 with the calculation times of searching data in the column vector table;
Second step is read the data corresponding with calculation times from the byte substitution table, with the data of reading respectively with [02,01,01,03]
T, [03,02,01,01]
T, [01,03,02,01]
T, [01,01,03,02]
TMultiplying each other obtains four data, then four data that will obtain store into respectively and search vector table 1, search vector table 2, search vector table 3, search memory space corresponding with calculation times in vector table 4;
In the 3rd step, whether the calculation times that data in the column vector table are searched in judgement equals 256, if so, has completed four calculating of searching the vector table data; Otherwise calculation times adds 1, carries out second step.
9. the super high-speed A ES processing method based on FPGA according to claim 7, is characterized in that, the data of searching contrary column vector table in described step (1) obtain according to following steps:
The first step is set as 1 with the calculation times of searching data in contrary column vector table;
Second step is read the data corresponding with calculation times from contrary byte substitution table, with the data of reading respectively with [0E, 09,0D, 0B]
T, [0B, 0E, 09,0D]
T, [0D, 0B, 0E, 09]
T, [09,0D, 0B, 0E]
TMultiplying each other obtains four data, then four data that will obtain store into respectively and search reverse scale 1, search reverse scale 2, search reverse scale 3, search reverse scale 4 memory space corresponding with calculation times;
In the 3rd step, whether the calculation times that data in contrary column vector table are searched in judgement equals 256, if so, has completed four calculating of searching reverse scale data; Otherwise calculation times adds 1, carries out second step.
10. the super high-speed A ES processing method based on FPGA according to claim 7, is characterized in that, in described step (1), the expanded keys register data of deciphering module obtains according to following steps:
The first step is set as 2 with the calculation times of the expanded keys register data of deciphering module;
Second step, sense data from the expanded keys register corresponding with calculation times of encrypting module, the data of reading are multiplied each other with contrary mixed linear transformation matrix obtains the data of 1 128 bit, then stores the data that obtain into expanded keys register corresponding with calculation times in deciphering module;
The 3rd step judged whether the calculation times of the expanded keys register data of deciphering module equals 10, if so, carried out for the 4th step; Otherwise calculation times adds 1, carries out second step;
In the 4th step, sense data from the 1st, the 11st expanded keys register of encrypting module directly stores the data of reading respectively into the 1st, the 11st expanded keys register of deciphering module.
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