CN103413164B - A kind of method for realizing data encrypting and deciphering function with embedded programmable logic gate array in intelligent card chip - Google Patents
A kind of method for realizing data encrypting and deciphering function with embedded programmable logic gate array in intelligent card chip Download PDFInfo
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Abstract
The invention discloses a kind of method for realizing data encrypting and deciphering function with embedded programmable logic gate array in intelligent card chip.Including system bus, channel, embedded microcontroller and smart card interface module, wherein, described device also includes the hardware enciphering and deciphering algoritic module being made up of deciphering module and encrypting module；The embedded microcontroller accesses the smart card interface module by the system bus, to receive the first data, and after first data are decrypted using the deciphering module, post-processing is carried out to the first decrypted data, operated with the reception for completing data；After the second data for needing to send are encrypted the embedded microcontroller by the encrypting module, the second encrypted data are transmitted by the channel, operated with the transmission for completing data.
Description
Technical field
The present invention relates to a kind of method that data encrypting and deciphering function is realized in intelligent card chip, more particularly to one kind is in intelligence
Can the interior method that data encrypting and deciphering function is realized with embedded programmable logic gate array of the core of the card piece.
Background technology
Due to containing substantial amounts of user's personal information in intelligent card chip, add so user data typically can all be first passed through
It is close, then it can be just transmitted on channel, to prevent being stolen by third party.Smart card can also after the information of encryption is received
It will be used for handling after the information decryption of encryption, here it is the data encrypting and deciphering process of smart card.The data encrypting and deciphering process is usual
It is to be operated by a data encryption/decryption module on piece, this module can be realized using hardware circuit, also may be used
To be realized using software algorithm.
As shown in figure 1, this is the intelligent card chip schematic diagram that data encrypting and deciphering algorithm is realized with hardware circuit；It is specific former
Manage and be：By bus, embedded microcontroller accesses program area and data field, and the data that will be sent are hard by data encrypting and deciphering
It is put on channel and is transmitted after the encryption of part module.After smart card receives the data come on self-channel, it is first by this data
Subsequent treatment is carried out again after being decrypted by data encrypting and deciphering hardware module.Because data encrypting and deciphering algorithm is realized by hardware circuit
, so the processing speed of data encrypting and deciphering is very fast, in the data communication system that can be used for high speed.But due to its hardware
The algorithm of circuit is fixed, once so key is cracked, whole sheet smart card is just scrapped, can be pacified in other words to the data of user
Full property brings very big danger, it is necessary to which costly man power and material helps user's weight for smart card issuer
Newly change card.
As shown in Fig. 2 this is the intelligent card chip schematic diagram that data encrypting and deciphering algorithm is realized with software algorithm；It is specific former
Manage and be：By bus, embedded microcontroller accesses program area and data field, and data encrypting and deciphering algorithm is realized by software, solidifies
On piece in certain section of space of program area, when data will be encrypted for smart card, this data encrypting and deciphering algorithm software will
It is embedded into the controller that declines to call and perform, the data after encryption can be placed on channel and be transmitted.When smart card is received
Come after the data on self-channel, microcontroller can first call data encrypting and deciphering algorithm software to decrypt it, then carry out again follow-up
Processing.Because data encrypting and deciphering algorithm is realized by software algorithm, so flexibility is very powerful, even if key is broken,
Terminal can also re-download one section of new data encrypting and deciphering algorithm software immediately to smart card, so, greatly disappear
Card cost is changed except smart card issuing business.But because it is that software is realized, so when data encrypting and deciphering algorithm is extremely complex
When, the program area shared by software will become very large, so as to add the area of intelligent card chip, and then cause intelligence
The increase of card chip cost, and enciphering and deciphering algorithm calls by embedded microcontroller, so processing speed is relative to by hard
Can be many slowly for the enciphering and deciphering algorithm of part circuit realiration, the data communication system of high speed is not suitable for sometimes.
Chinese patent（Authorization Notice No.：CN100369017C）Disclose a kind of static RAM programmable gate array
The encryption device and encryption method of chip, the encryption device of the invention include a piece of FLASH fpga chips and in FLASH
The handshake circuit realized in FPGA and SRAMFPGA and in FLASH fpga chips, remaining logic is used to realize system
Part LSL in function, further to improve the security of system.The invention be based on SRAM can
Encryption method on programmed logic door chip, therefore it inevitably has the defect of SRAM, such as works as it
During power down, the information of its storage inside just lost, and need to re-start the loading of information after upper electricity again, this can virtually
Increase the time of ciphering process, be not suitable for the data communication system of high speed.
The content of the invention
In view of the above problems, the present invention provides one kind and realized in intelligent card chip with embedded programmable logic gate array
The method of data encrypting and deciphering function.
The technical proposal for solving the technical problem of the invention is：
A kind of device for realizing data encrypting and deciphering function, described device includes system bus, channel, embedded microcontroller
And smart card interface module, wherein, described device also includes the hardware enciphering and deciphering algorithm being made up of deciphering module and encrypting module
Module；
The embedded microcontroller accesses the smart card interface module by the system bus, to receive the first number
According to, and after first data are decrypted using the deciphering module, post-processing is carried out to the first decrypted data,
Operated with the reception for completing data；
After the second data for needing to send are encrypted the embedded microcontroller by the encrypting module, it will add
Second data of close mistake are transmitted by the channel, are operated with the transmission for completing data.
The described device for realizing data encrypting and deciphering function, wherein, made using embedded programmable logic gate array module
For the hardware enciphering and deciphering algoritic module.
The described device for realizing data encrypting and deciphering function, wherein, can be using non-volatile memory cells as described embedding
Enter the configuration memory cell of formula programmable gate array module.
The described device for realizing data encrypting and deciphering function, wherein, the non-volatile memory cells be phase transition storage,
Ferroelectric memory, resistance-type memory, magnetic media memory or flash memories.
The described device for realizing data encrypting and deciphering function, wherein, the embedded programmable logic gate array module
Minimum unit can be not include sequential logic, with very in combinational logic, i.e. the embedded programmable logic gate array module
Reduce the area of chip in big degree.
The described device for realizing data encrypting and deciphering function, wherein, described device also includes a host computer, the host computer
In software program is installed；
The software program generates configuration file according to the embedded programmable logic gate array module resource.
The described device for realizing data encrypting and deciphering function, wherein, described device also includes a data cell and a program
Unit, the embedded microcontroller carries out the read-write of data by the system bus to the data cell and program unit
Operation.
The described device for realizing data encrypting and deciphering function, wherein, the host computer passes through the configuration file described
Smart card interface module is stored to the data cell, and the embedded microcontroller reads matching somebody with somebody of being stored in the data cell
File is put, to carry out write operation to the embedded programmable logic gate array module, to update the embedded programmable
The data encrypting and deciphering algorithm of logic gate array module.
The described device for realizing data encrypting and deciphering function, wherein, described device also includes a direct memory access (DMA) mould
Block；
The smart card interface module includes a buffer unit；
The host computer stores the configuration file to the buffer unit by the smart card interface module, described
The configuration file stored in buffer unit described in direct memory access (DMA) module calls, with to the embedded programmable gate
Array module carries out write operation, to update the data encrypting and deciphering algorithm of the embedded programmable logic gate array module.
The described device for realizing data encrypting and deciphering function, wherein, the configuration file includes high speed algorithm unit and low
Short-cut counting method unit；
The device for realizing data encrypting and deciphering function algorithm includes the first algoritic module and the second algoritic module, described the
One algoritic module is realized that second algoritic module is real by software algorithm by the embedded programmable logic gate array module
It is existing；
High speed algorithm is written into first algoritic module, to carry out the processing of high speed complex data；
Low speed algorithm is written into second algoritic module, to carry out the processing of low speed simple data.
The data encrypting and deciphering algorithm formed by the configuration file includes high speed algorithm,
A kind of method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein,
The software program is based on a hardware enciphering and deciphering algoritic module resource and generates configuration file, and this configuration file is led to
Cross the smart card interface module and be transferred to the intelligent card chip；
The configuration file is temporarily stored into a data cell by embedded microcontroller by the interface of intelligent card chip；
The configuration file being stored in the data cell is transferred, the hardware enciphering and deciphering module is write, makes it have number
According to encryption and decryption functions.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, using it is embedded can
Programmed logic Gate Array module is used as the hardware enciphering and deciphering algoritic module.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it can use non-volatile
Property memory cell as the embedded programmable logic gate array module configuration memory cell.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it is described non-volatile
Memory cell is phase transition storage, ferroelectric memory, resistance-type memory, magnetic media memory or flash memories.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it can use purely logical
Combine the minimum unit as the embedded programmable logic gate array module.
A kind of method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein,
The software program is based on a hardware enciphering and deciphering algoritic module resource and generates configuration file, and this configuration file is led to
Cross the smart card interface module and be transferred to the intelligent card chip；
The configuration file is temporarily stored into the slow of intelligent card interface by embedded microcontroller by the interface of intelligent card chip
On memory cell；
Direct memory access (DMA) module calls are stored in the configuration file in the buffer unit, are written into the hardware
Encryption/decryption module, makes it have data encrypting and deciphering function.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, using it is embedded can
Programmed logic Gate Array module is used as the hardware enciphering and deciphering algoritic module.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it can use non-volatile
Property memory cell as the embedded programmable logic gate array module configuration memory cell.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it is described non-volatile
Memory cell is phase transition storage, ferroelectric memory, resistance-type memory, magnetic media memory or flash memories.
The described method being updated in intelligent card chip to data enciphering and deciphering algorithm, wherein, it can use purely logical
Combine the minimum unit as the embedded programmable logic gate array module.
A kind of data decryption method, applied on intelligent card chip, wherein,
Smart card interface module receives the user data by encryption that another intelligent card chip is sent；
Embedded microcontroller reads the use by encryption that the smart card interface module is received by system bus
User data；
Operation is decrypted to the user data by encryption using the deciphering module in hardware enciphering and deciphering algoritic module；
Post-treatment operations are carried out to the user data of decrypted reception.
Described data decryption method, wherein, added using embedded programmable logic gate array module as the hardware
Decipherment algorithm module.
Described data decryption method, wherein, it can be patrolled using non-volatile memory cells as the embedded programmable
Collect the configuration memory cell of Gate Array module.
Described data decryption method, wherein, the non-volatile memory cells be phase transition storage, ferroelectric memory,
Resistance-type memory, magnetic media memory or flash memories.
Described data decryption method, wherein, the minimum unit of the embedded programmable logic gate array module can be with
Not include sequential logic in pure combinational logic, i.e. the embedded programmable logic gate array module, largely to subtract
The area of small chip.
Described data decryption method, wherein, by one according to the embedded programmable logic gate array module resource
The configuration file of generation is programmed to the programmable gate array module.
A kind of data ciphering method, wherein, applied on intelligent card chip, wherein, embedded microcontroller transfers needs
The not encrypted user data being transmitted；
Operation is encrypted to not encrypted user data using the encrypting module in hardware enciphering and deciphering algorithm；
User data after encryption is put in channel, to be transmitted.
Described data ciphering method, wherein, added using embedded programmable logic gate array module as the hardware
Decipherment algorithm module.
Described data ciphering method, wherein, it can be patrolled using non-volatile memory cells as the embedded programmable
Collect the configuration memory cell of Gate Array module.
Described data ciphering method, wherein, the non-volatile memory cells be phase transition storage, ferroelectric memory,
Resistance-type memory, magnetic media memory or flash memories.
Described data ciphering method, wherein, the minimum unit of the embedded programmable logic gate array module can be with
Not include sequential logic in pure combinational logic, i.e. the embedded programmable logic gate array module, largely to subtract
The area of small chip.
Described data ciphering method, wherein, by one according to the embedded programmable logic gate array module resource
The configuration file of generation is programmed to the programmable gate array module.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
The present invention solves the problem of speed of service is slow when data encrypting and deciphering algorithm is realized with software, also causes real with hardware
After existing data encrypting and deciphering algorithm, the situation that key cancels once the intelligent card chip that is cracked is improved.And it can use
Non-volatile memory cells realize the configuration memory cell in embedded programmable logic gate array, so that smart card
Area reduces, and lower power consumption greatly reduces cost, more smart card can be made to reach the purpose quickly started after electricity.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is the intelligent card chip schematic diagram that data encrypting and deciphering algorithm is realized with hardware circuit；
Fig. 2 is the intelligent card chip schematic diagram that data encrypting and deciphering algorithm is realized with software algorithm；
Fig. 3 is that one kind in the embodiment of the present invention 1 realizes data encrypting and deciphering algorithm with embedded programmable logic gate array
Intelligent card chip schematic diagram；
Fig. 4 is that one kind in the embodiment of the present invention 2 realizes data encrypting and deciphering algorithm with embedded programmable logic gate array
Intelligent card chip schematic diagram；
Fig. 5 is traditional use SRAM cell as in the programmable gate array for switching selection
The schematic diagram of wiring channel；
Fig. 6 is programmable gate array of traditional use SRAM cell as data input
The schematic diagram of interior lookup table；
Fig. 7 is used as wiring channel in the programmable gate array for switching selection for the present invention using phase-changing memory unit
Schematic diagram；
Fig. 8 is used as lookup table in the programmable gate array of data input for the present invention using phase-changing memory unit
Schematic diagram；
Fig. 9 is traditional programmable gate array modular unit schematic diagram with sequential logic unit；
Figure 10 is programmable gate array modular unit schematic diagram of the present invention without sequential logic unit；
Figure 11 for the present invention in reduce the programmable gate array area method schematic diagram；
Figure 12 A be the embodiment of the present invention 1 in by the programmable gate array configuration file be implanted into programmable gate
The step schematic diagram of array；
Figure 12 B be the embodiment of the present invention 2 in by the programmable gate array configuration file be implanted into programmable gate
The step schematic diagram of array.
Embodiment
The invention provides a kind of device for realizing data encrypting and deciphering function.Fig. 3 is one kind insertion proposed by the present invention
Formula programmable gate array realizes the intelligent card chip schematic diagram of data encrypting and deciphering algorithm；As shown in figure 3, total including system
Line, channel（It is not shown）, embedded microcontroller and smart card interface module, wherein, described device also includes hardware
Also include a deciphering module and an encrypting module in enciphering and deciphering algorithm module, the hardware enciphering and deciphering algoritic module.Apparatus of the present invention
Also include a data cell and a program unit, embedded microcontroller is by system bus to the data cell and program list
Member conducts interviews, to carry out the read-write operation of data and program.
Following data interaction can be realized by above-mentioned component：
Embedded microcontroller can be conducted interviews by system bus to smart card interface module, and receive the first number
According to first data can be the user data being not yet decrypted after encrypting, can be to first data by deciphering module
It is decrypted, the first data after decryption can be used for the processing in later stage, i.e., the above-mentioned device for realizing data encrypting and deciphering function
The reception operation of complete paired data.
Correspondingly, the second data for needing to send can be passed through by embedded microcontroller in hardware enciphering and deciphering algorithm
AES be encrypted, second data can be not encrypted user data, and second data can after encryption
To be transmitted by channel, at this moment, the present invention realizes the transmission operation of the complete paired data of device of data encrypting and deciphering function.
It is preferred that, the reception of above-mentioned the first data and the second data can have data to add with transmission in two identicals
Decrypt in the device of function and carry out, and its process for receiving and sending can be reciprocal.
Further, above-mentioned intelligent card interface includes a buffer unit, and temporarily storage is can be used in the buffer unit
User profile after encryption.
After user data after encryption is received by intelligent card interface, it is temporarily stored into the buffer unit；Embedded microcontroller
Device can be conducted interviews by system bus to intelligent card interface, to read the user being temporarily stored into after encrypted in the buffer unit
The user data is sent to hardware enciphering and deciphering algoritic module by data, embedded microcontroller, by the hardware enciphering and deciphering algorithm mould
User data after encryption is decrypted block, and the user data after decryption is used for follow-up processing by embedded microcontroller.
After embedded microcontroller gets not encrypted user profile, embedded microcontroller is by the user profile
Hardware enciphering and deciphering algoritic module is sent to, the user data of unencryption is encrypted by the hardware enciphering and deciphering algoritic module, plus
User data after close is put on channel by embedded microcontroller, to be transmitted.
For above-mentioned hardware enciphering and deciphering algoritic module, embedded programmable logic gate array module is preferably used, should
Embedded programmable logic gate array module can have specific data encrypting and deciphering function after programming.In addition, the present apparatus is also
Including an external smart card server terminal, store and some compiled based on embedded in the smart card server terminal
Journey logic gate array resource and the specific data encrypting and deciphering algorithm for compiling completion.
For the security of the data encrypting and deciphering that further optimizes the present apparatus, the smart card server terminal uses following two
Kind of method improves the security of data：
1st, smart card server terminal regularly calculates the data encrypting and deciphering in embedded programmable logic gate array module
Method is updated replacement, to enable the data encrypting and deciphering algorithm in embedded programmable logic gate array module every one section
Time is just replaced, so as to improve the security of data encrypting and deciphering algorithm on one's own initiative；
2nd, after the key of smart card is cracked, i.e. original data in embedded programmable logic gate array module add
After decipherment algorithm is decrypted, now original data encrypting and deciphering algorithm has not had the function of encryption and decryption data, loses pair
The protection of data.In this case, smart card server terminal can be at this moment in time to embedded programmable gate
Data encrypting and deciphering algorithm in array module is updated replacement, rather than again etc. scheduled renewal time be just updated,
This is passively to carry out safety to data to remedy.
It can be seen that, by the smart card server terminal of a peripheral hardware in the present apparatus, it can both be compiled on one's own initiative to embedded
Data encrypting and deciphering algorithm in journey logic gate array module updates with being timed, again can be in original data encrypting and deciphering algorithm
After being cracked, timely respond to be updated original algorithm, be combined by active protection and passive remedy, can be flexible
Ground is replaced to the data encrypting and deciphering algorithm in embedded logic Gate Array module, even if so that when smart card encryption and decryption
After algorithm is cracked, intelligent card chip can be without scrapping, but is continuing with, and then can extend the use longevity of smart card
Life.
The renewal for carrying out data encrypting and deciphering algorithm by smart card server terminal includes：Will configuration text in a host computer
Part is stored into data cell by smart card interface module, and what is then stored in embedded microcontroller reading data cell matches somebody with somebody
File is put, to carry out write operation to embedded programmable logic gate array module, and then embedded programmable gate is updated
Data encrypting and deciphering algorithm in array module.
Further, in order to improve processing speed of the embedded logic Gate Array module to data, and smart card is improved
Upper electroresponse speed, the present invention using nonvolatile memory as the memory in embedded logic Gate Array module, with
The traditional static random-access memory of substitution, to data storage enciphering and deciphering algorithm.These nonvolatile memories can be
Phase transition storage (phase change memory, referred to as：PCM), ferroelectric memory (Ferroelectric random
Access memory, referred to as：FRAM), resistance-type memory (Resistive Random Access Memory, abbreviation：
ReRAM), magnetic media memory (magnetic RAM, abbreviation：MRAM), flash memories (Flash) etc..Because these are non-easily
The property lost memory can remain on the storage to data, the i.e. storage to data enciphering and deciphering algorithm in the case of power down, this
Allow for that during the upper electricity next time of smart card after a power failure data need not be reloaded again, greatly improve the upper electricity of smart card
Response speed.
With reference to specific embodiment, the present invention is described in detail.
Embodiment 1
In order that device has data encrypting and deciphering function, it is necessary first to assign data to embedded logic Gate Array module and add
Decipherment algorithm, as illustrated in fig. 12, is completed by following steps：
Step S1, on a host computer by the data encrypting and deciphering algorithm based on embedded programmable logic gate array resource
Compiling is completed, and generates embedded programmable logic gate array configuration file（BIT FILE）；
Step S2, by the interface of the intelligent card chip embedded programmable logic gate array configuration file, and send
To the intelligent card chip；
The embedded programmable logic gate array configuration file received is temporarily stored into smart card by step S3, intelligent card chip
In data cell in chip；
The embedded programmable logic gate array configuration file that step S4, intelligent card chip will be stored in data cell is compiled
In journey to embedded programmable logic gate array module, and then make embedded programmable logic gate array module that there is specific number
According to encryption and decryption functions.
The specific encryption and decryption of embedded programmable logic gate array module is imparted by above-mentioned step S1~step S4
Algorithm function so that the programmable gate array module turns into a hardware enciphering and deciphering algoritic module in whole device.
Then, user data is implemented to add by having been assigned the embedded logic Gate Array module of data encrypting and deciphering algorithm
Close and decryption, its specific method is as follows：
Intelligent card interface can be conducted interviews by system bus by embedded microcontroller, smart card is temporarily stored into read
User data after encrypted in buffer unit in excuse, and sent out the user data by the embedded microcontroller
Embedded logic Gate Array module is given, then, the user data after encryption is carried out by the embedded logic Gate Array module
Decryption, the user data after decryption is used for follow-up processing by embedded microcontroller again.
After embedded microcontroller gets not encrypted user profile, embedded microcontroller is by the user profile
Embedded logic Gate Array module is sent to, then, the user data of unencryption is entered by the embedded logic Gate Array module
Row encryption, it is encrypted after user data be put in by embedded microcontroller on channel, to be transmitted.
In order to further improve the security of data encrypting and deciphering algorithm, a smart card service is additionally provided with the present embodiment
Device terminal, regularly can be added the data in embedded programmable logic gate array module by the smart card server terminal
Decipherment algorithm is updated.Or after the key of smart card is cracked, the smart card server terminal can be immediately to insertion
Data encrypting and deciphering algorithm in formula logic gate array module is updated, to realize neatly and targetedly lift intelligence
The security to user data processing can be blocked, while also extending the service life of smart card.
Because embedded logic Gate Array module is the core of the embodiment of the present invention, therefore below to embedded logic gate array
Row module optimizes to be different from traditional embedded logic Gate Array module.
In order to improve the processing speed to data of embedded logic Gate Array module, deposited in the present embodiment using phase transformation
Reservoir is as the memory in embedded logic Gate Array module, to be stored to programmable gate configuration file.Below
Comparative illustration is carried out to the phase transition storage in traditional static random-access memory and the present embodiment.
Comparative illustration is mainly carried out in terms of following two：
1st, in Programmadle logic Gate Array module in terms of the switch of wiring channel.As shown in figure 5, it is to be visited with static random
Ask that memory cell switchs wiring channel schematic diagram in the programmable gate array of selection.Such as when switch is brilliant with N-type
Body pipe is made, then increase level in its grid, and switch is turned on, and allows signal to pass through from source electrode and drain electrode, if adding in grid
Low level, switch is shut off, and prevents signal to pass through from source electrode and drain electrode.So, as long as passing through configuration file（BIT FILE）
The configuration memory cell that output is connected into switch gate is programmed to logical one or logical zero, you can the flow direction of control signal,
Serve the effect of laying-out and wiring passage.Wiring channel configuration memory cell is with static state in traditional programmable gate array
Random access storage device（SRAM）Realize, cellar area is 120F2, under deep-submicron processing procedure, and its electric leakage also can be very big.Such as
Shown in Fig. 7, it is to use phase transition storage（PCM）Unit switchs wiring channel in the programmable gate array of selection and illustrated
Figure.Phase transition storage is a kind of new nonvolatile memory, and its cellar area is about 10F2, under deep-submicron processing procedure,
Its electric leakage is very small.So, use phase transition storage（PCM）To substitute static random-access memory（SRAM）Patrolled as programmable
Wiring channel configuration memory cell in gate array is collected, the area of embedded programmable logic gate array can be greatly reduced, and
And static leakage current is greatly reduced so as to fit in the demand of smart card super low-power consumption.
2nd, in terms of the look-up table in Programmadle logic Gate Array module.As shown in fig. 6, it is to be stored with static random-access
Device unit does lookup table in the programmable gate array of data input and realizes schematic diagram.Lookup table is programmable gate
In another basic logic unit in array, figure it is one simple four and selects a circuit, SRAM records defeated in the case of four kinds
Go out value.Likewise, as shown in figure 8, it is to be searched in the programmable gate array for make data input of phase-changing memory unit
Form realizes schematic diagram, and SRAM is substituted as lookup table configuration memory cell in programmable gate array with PCM, can be with
The area of embedded programmable logic gate array is greatly reduced, and greatly reduces static leakage current so as to fit in intelligence
The demand of energy card super low-power consumption.
Further, because embedded programmable logic gate array module is the module of semi-custom, therefore, when it is in reality
Logic redundancy can be produced while existing data encrypting and deciphering algorithm, in other words, when data encrypting and deciphering algorithm is very complicated,
Resource in programmable gate array module is accomplished by more, and this virtually increases the physical surface of intelligent card chip
Product, two kinds of feasible prioritization schemes are proposed for the problem, in the present embodiment from different perspectives.
Prioritization scheme 1：Because traditional embedded programmable logic gate array module is by combinatorial logic unit and sequential
The Gate Array module for the combined rear generation of minimum unit that logic unit is constituted.And most data encrypting and deciphering algorithm is only
Realized by combinatorial logic unit, thus consider in the present embodiment will almost inoperative sequential logic unit from insertion
Removed in formula programmable gate array module, as shown in Fig. 9~10.Can greatly reduce by this method it is embedded can
The area of programmed logic Gate Array module, therefore when embedded programmable logic gate array module needs to realize relative complex add
When decrypting computing, the area of the reduction can be used for depositing more Programmadle logic gate array resources, and this guarantees in face
Embedded programmable logic gate array module can carry out increasingly complex data encrypting and deciphering algorithm in the case that product is certain.
Prioritization scheme 2：According to the complexity of data encrypting and deciphering algorithm, data encrypting and deciphering algorithm is split as two portions
Point.A part is complicated algorithm part, and its data processing amount is very huge, and needs to carry out high-speed computation；Another part is
Relatively easy algorithm, its data processing amount is not very big, and need not carry out high-speed computation.For the spy of above two algorithm
Levy, in the present embodiment realize high speed complicated algorithm part using embedded programmable logic gate array module, and it is relative
Low speed simple algorithm part then uses traditional software algorithm to realize, as shown in figure 11.So when embedded microcontroller is being adjusted
During with complicated data encrypting and deciphering algorithm, its method that can be alternately combined using software and hardware is handled, and this both reduces intelligence
The physical area of energy the core of the card piece, in turn ensure that the speed of data processing.
Technical scheme disclosed above can have the calculation of conventional hardware data encrypting and deciphering concurrently to a certain extent in the present embodiment
The speed of method and the flexibility of traditional software enciphering and deciphering algorithm.Below by several aspects by the technical side of the embodiment of the present invention
Case and conventional art are compared explanation.
As shown in table 1, this is to realize data encrypting and deciphering algorithm and the present invention with hardware or software on traditional smart card
Propose it is a kind of with embedded programmable logic gate array realize enciphering and deciphering algorithm between comparison.Because embedded programmable is patrolled
Volume array uses semicustom technology, so it realizes that area can be less than with shared by software algorithm realizes data encrypting and deciphering
Program unit physical size size, but because the data encrypting and deciphering algorithm realized with hardware circuit is the skill based on full custom
Art, so the area after being realized with hardware is minimum.In speed, the algorithm realized with software be called by microcontroller and
Processing, so its speed is most slow；And the mode realized with hardware circuit is ultrafast in speed, because its speed exists
All it was optimised when design；The mode that use embedded programmable logic gate array proposed by the present invention is realized, by
It is semi-custom in it, so can be less than or equal to use hard-wired mode in speed, but can be significantly faster than and be realized with software
Mode.Consider from safe flexibility, the mode realized with software is the most flexible, in theory, uses software algorithm
Any data encrypting and deciphering algorithm can be realized；For the mode realized with hardware circuit, due to it once passing through technique system
Cheng Hou, will be got off by permanent cured, so it does not have any flexibility；And proposed by the present invention patrolled with embedded programmable
The mode that gate array is realized is collected, flexibility is also very high, it is possible to achieve any data encrypting and deciphering algorithm, simply when algorithm is more multiple
It is miscellaneous, then the area that it is required is also bigger, in other words, under the qualifications of certain area, it is proposed by the present invention to realize
The flexibility of mode can be below or equal to the mode realized with software.
| Implementation | Area | Speed | Safe flexibility |
| Hardware | It is small | It is ultrafast | Nothing |
| Software | Greatly | Slowly | It is high |
| The present invention | In | It hurry up | Middle height |
Table 1
Embodiment 2
The embodiment of the present invention 2 also includes a direct memory in example 2 with being in place of the difference of embodiment 1
Access module (direct memory access, referred to as：DMA), as shown in figure 4, the direct memory access (DMA) module wherein
One end is connected to the output end of the buffer unit of smart card excuse, and the other end is then connected to embedded programmable logic gate array mould
The input of block.In this way, data encrypting and deciphering algorithm function is assigned not to embedded programmable logic gate array module
The participation by embedded microcontroller is needed, but by direct memory access (DMA) module directly by embedded programmable logic
The configuration file of Gate Array module is rapidly programmed in the embedded programmable logic gate array module.As shown in Figure 12 B, have
Body is realized by following steps：
Step S1, on a host computer by the data encrypting and deciphering algorithm based on embedded programmable logic gate array resource
Compiling is completed, and generates embedded programmable logic gate array configuration file（BIT FILE）；
Step S2, by the interface of the intelligent card chip embedded programmable logic gate array configuration file, and send
To the intelligent card chip；
The embedded programmable logic gate array configuration file received is temporarily stored in the intelligence by step S3, intelligent card chip
On the buffer unit of energy card chip interface；
The embedded programmable logic that step S4, intelligent card chip will be stored on smart card chip interface buffer unit again
Gate array configuration file is by direct memory access (DMA) module programming to embedded programmable logic gate array module, having it
There is specific data encrypting and deciphering function.
The specific encryption and decryption of embedded programmable logic gate array module is imparted by above-mentioned step S1~step S4
Algorithm function so that the programmable gate array module turns into a hardware enciphering and deciphering algoritic module in whole device.
Then, user data is implemented to add by having been assigned the embedded logic Gate Array module of data encrypting and deciphering algorithm
Close and decryption, its specific method is in the same manner as in Example 1：
Intelligent card interface can be conducted interviews by system bus by embedded microcontroller, smart card is temporarily stored into read
User data after encrypted in buffer unit in excuse, and sent the user data by the embedded microcontroller
Embedded logic Gate Array module is given, then, the user data after encryption is solved by the embedded logic Gate Array module
Close, the user data after decryption is used for follow-up processing by embedded microcontroller again.
After embedded microcontroller gets not encrypted user profile, embedded microcontroller is by the user profile
Embedded logic Gate Array module is sent to, then, the user data of unencryption is entered by the embedded logic Gate Array module
Row encryption, it is encrypted after user data be put in by embedded microcontroller on channel, to be transmitted.
It is same as Example 1, a smart card server terminal is again provided with embodiment 2, is serviced by the smart card
Data encrypting and deciphering algorithm in embedded programmable logic gate array module regularly can be updated by device terminal.Or work as
After the key of smart card is cracked, the smart card server terminal can be immediately to the data in embedded logic Gate Array module
Enciphering and deciphering algorithm is updated.
In example 2, the improvement for embedded programmable logic gate array module is in the same manner as in Example 1, therefore
This is no longer repeated.
In summary, the present invention solves the problem of speed of service is slow when data encrypting and deciphering algorithm is realized with software, also makes
Handy hardware realizes after data encrypting and deciphering algorithm that the situation that key cancels once the intelligent card chip that is cracked is improved.
And the configuration memory cell in embedded programmable logic gate array can be realized with non-volatile memory cells, so that
The area for obtaining smart card reduces, and lower power consumption greatly reduces cost, more smart card can be made to reach what is quickly started after electricity
Purpose.
For a person skilled in the art, read after described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.In power
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (6)
1. a kind of device for realizing data encrypting and deciphering function, described device include system bus, channel, embedded microcontroller and
Smart card interface module, it is characterised in that the hardware that described device also includes being made up of deciphering module and encrypting module adds
Decipherment algorithm module, the hardware enciphering and deciphering algoritic module is realized using embedded programmable logic gate array module；
The embedded microcontroller accesses the smart card interface module by the system bus, to receive the first data,
And after first data are decrypted using the deciphering module, decrypted first data were carried out at the later stage
Reason, is operated with the reception for completing data；
, will be encrypted after the second data for needing to send are encrypted the embedded microcontroller by the encrypting module
Second data be transmitted by the channel, with complete data transmission operate；
The device for realizing data encrypting and deciphering function is used as the embedded programmable logic using non-volatile memory cells
The configuration memory cell of Gate Array module；
The device for realizing data encrypting and deciphering function is patrolled the embedded programmable using the non-volatile memory cells
The look-up table in Gate Array module in the switch and the embedded programmable logic gate array module of wiring channel is collected to carry out
Optimization.
2. the device as claimed in claim 1 for realizing data encrypting and deciphering function, it is characterised in that described device also includes on one
Position machine；
The host computer generates configuration file according to the embedded programmable logic gate array module resource.
3. the device as claimed in claim 2 for realizing data encrypting and deciphering function, it is characterised in that described device also includes a number
According to unit and a program unit, the embedded microcontroller is by the system bus to the data cell and described program
Unit carries out the read-write operation of data.
4. the device as claimed in claim 3 for realizing data encrypting and deciphering function, it is characterised in that described device also includes first
Algoritic module and the second algoritic module；
First algoritic module realizes that it is written into high speed algorithm using the embedded programmable logic gate array module,
To carry out the processing of high speed complex data；
Second algoritic module realizes that it is written into low speed algorithm, to carry out low speed simple data using traditional software algorithm
Processing；
The high speed algorithm is split by data encrypting and deciphering algorithm with the low speed algorithm and formed.
5. a kind of carried out more in the device for realizing data encrypting and deciphering function as claimed in claim 1 to data enciphering and deciphering algorithm
New method, it is characterised in that
One host computer is based on hardware enciphering and deciphering algoritic module resource described in one and generates configuration file, and the configuration file is passed through
Smart card interface module is transferred to intelligent card chip described in one；
The configuration file is temporarily stored into a data cell by the embedded microcontroller by the smart card interface module；
The configuration file being stored in the data cell is transferred, the hardware enciphering and deciphering algoritic module is write, makes it have number
According to encryption and decryption functions.
6. a kind of carried out more in the device for realizing data encrypting and deciphering function as claimed in claim 1 to data enciphering and deciphering algorithm
New method, it is characterised in that
One host computer is based on hardware enciphering and deciphering algoritic module resource described in one and generates configuration file, and the configuration file is passed through
Smart card interface module is transferred to intelligent card chip described in one；
The configuration file is temporarily stored into the intelligent clamping by the embedded microcontroller by the smart card interface module
On the buffer unit of mouth mold block；
Direct memory access (DMA) module calls are stored in the configuration file in the buffer unit, are written into the hardware
Enciphering and deciphering algorithm module, makes it have data encrypting and deciphering function.
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| CN109932953A (en) * | 2017-12-19 | 2019-06-25 | 陈新 | Intelligent supercomputer programmable controller |
| CN108280372A (en) * | 2018-02-23 | 2018-07-13 | 深圳国微技术有限公司 | A kind of safety chip |
| CN111339544B (en) * | 2019-04-24 | 2023-03-14 | 上海安路信息科技股份有限公司 | Offline downloading device and offline downloading method |
| CN112668026B (en) * | 2020-12-31 | 2023-12-22 | 兴唐通信科技有限公司 | Anti-irradiation satellite-borne TCM (TCM) device |
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