CN103151259A - Method for removing passivation layer of chip - Google Patents
Method for removing passivation layer of chip Download PDFInfo
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- CN103151259A CN103151259A CN2013100722319A CN201310072231A CN103151259A CN 103151259 A CN103151259 A CN 103151259A CN 2013100722319 A CN2013100722319 A CN 2013100722319A CN 201310072231 A CN201310072231 A CN 201310072231A CN 103151259 A CN103151259 A CN 103151259A
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Abstract
The invention relates to a method for removing a passivation layer of a chip. The method comprises the following steps of: acquiring ingredients and thickness of the passivation layer of the chip; protecting areas of other devices except for the chip; judging the components of the outmost passivation layer of the chip; inspecting the processed chip again through an optical microscope or energy disperse spectroscopy and checking whether the passivation layer or the components thereof exists in the surface of the chip; and if the passivation layer exists, repeating the steps to carry out processing, and finally cleaning the chip. According to the method disclosed by the invention, different removal modes of different ingredients of passive layers are integrally considered, the passive layer of the chip is removed by targetedly adopting different modes, so that the passivation layer removal effect of the chip is favorable, and the purpose that the method is used for removing various passivation layer materials and composite materials can be achieved.
Description
Technical field
The present invention relates to a kind of removal method of chip passivation layer, relate in particular to a kind ofly in integrated circuit (IC) chip reliability consideration, remove the method for chip passivation layer in order to the structure of studying chip internal.
Background technology
In the chip manufacturing process of modern semiconductors integrated circuit (IC)-components, electric property and reliability in order to improve chip adopt SiO usually at chip surface
2, SiN
x, phosphorosilicate glass (PSG) is made Passivation Treatment, forms passivation layer.In addition, along with the development of ic manufacturing technology level, the factors such as the so-called soft error of chip, signal delay, reduction manufacturing cost make polyimides (PI) be used widely at microelectronic.Facts have proved, the current collection with PI passivation protection floor becomes the road chip to have very low leakage current, stronger mechanical performance and resistance to chemical corrosion.Simultaneously, the PI film also can block moisture effectively, increases the moisture resistant ability of components and parts, thereby has improved the electric property of chip, has reduced production cost, has obtained very large economic benefit.Therefore, in modern large scale integrated circuit, usually adopt SiO
2, SiN
x, phosphorosilicate glass, the polyimides multiple material is as the surface passivation layer of chip.
And in integrated circuit (IC) chip reliability consideration work, usually need the passivation layer of chip surface is removed, with the research chip internal structure.Such as in integrated circuit (IC) chip failure analysis work, it is inner that the chip failure position usually is positioned at the chip sandwich construction, in order to search accurately the chip failure reason, must in conjunction with the electrical testing means, carry out delamination to chip and process.In this process, the problem that at first will solve is exactly to remove the passivation material of chip surface.In Destructive Physical Analysis work, according to the test requirements document of scanning electronic microscope examination in GJB548-2005 and MIL-STD-883, every one deck metallization quality of chip is checked.This also requires us to remove the passivation layer of chip surface and internal structure.In the IC reliability research work, seek a kind of to metal layer harmless, to various passivation material and combined material all suitable passivation layer removal method just seem especially important.
Present common way is mainly to adopt RIE dry etching means.Bombard the chip surface passivation material by energetic plasma, adopt physical method to remove passivation layer, this way is for SiO
2, SiN
xMaterial and phosphorosilicate glass etc. are very convenient quick, but for polyimide film material, it is helpless that the RIE dry etching technology often seems.
Summary of the invention
For solving defective of the prior art, the object of the present invention is to provide a kind of can be simultaneously to SiO
2, SiN
xMaterial, the method that phosphorosilicate glass and polyimide film material passivation layer are removed.
For achieving the above object, the present invention has adopted following technical scheme:
A kind of removal method of chip passivation layer is characterized in that, comprises the following steps:
Step 1 obtains chip passivation composition of layer and thickness; Check by light microscope or the energy disperse spectroscopy bonding region to chip, at first obtain the composition of the surface passivation layer of chip, secondly according to color and the reflective difference of bonding region and peripheral region, the thickness of acquisition bonding region passivation material;
Step 2 is protected other device areas beyond chip; Adopt stable chemical nature, be not subjected to the thin-film material of etching or corrosion impact to cover chip other device areas in addition;
Step 3, the composition of the surface passivation layer of judgement chip; If be SiO
2, SiN
xOr the phosphorosilicate glass composition, adopt the RIE dry etching that chip is processed; If be the polyimides composition, adopt acid solution wet etching method or superlaser etching method that chip is processed;
Step 4 checks the chip after step 3 is processed again by light microscope or energy disperse spectroscopy, check whether chip surface also has passivation layer and composition thereof; If also have passivation layer, repeating step two and three is processed;
Step 5 is cleaned chip; Adopt organic solvent that device chip is cleaned.
As preferably, the thin-film material in described step 2 is polytetrafluoroethylene.
As preferably, the described RIE dry etching in described step 3 is isotropic etching, and the etching gas of employing is CF
4+ O
2, proportioning is 2:1, etching power is 80W, etching pressure 300 mTorr.
As preferably, in the acid solution wet etching method of described step 3, chip is placed in the wet chemistry mail opener, carry out splash with acid solution at chip surface and process.
As preferably, described acid solution is sulfuric acid or nitric acid, during greater than 5um, uses sulfuric acid when passivation layer thickness, during less than 5um, uses nitric acid when passivation layer thickness.
As preferably, in acid solution wet etching method, corrosion temperature is 80-90 ℃, and etching time is 50-70 second.
As preferably, in described step 5, described organic solvent is absolute ethyl alcohol or acetone.
The present invention can reach following effect: the removing method that has considered the heterogeneity passivation layer is different, adopted targetedly diverse ways to remove chip passivation layer, make the chip passivation layer removal effect good, can reach all suitable to the removal of various passivation material and combined material.
Embodiment
Below in conjunction with embodiment, the present invention is made clear, complete explanation.
It is different that the present invention considers the removing method of different passivation material, and provide a kind of can be simultaneously to SiO
2, SiN
xMaterial, the method that phosphorosilicate glass and polyimide film material passivation layer are removed.
When taking the device that needs the removal chip passivation layer, check by light microscope or the energy disperse spectroscopy bonding region to chip, obtain the composition of the surface passivation layer of chip, then according to color and the reflective difference of chip bonding district and peripheral region, obtain the metallization material of bonding region and the thickness of passivation material.The bonding region of general chip is inner exposed metal layer material, Al, Au or Cu, by microscope and energy disperse spectroscopy, contrast bonding region and the color of peripheral region, reflective difference condition, can roughly judge the thickness of bonding region metallization material and passivation material.
Before removing passivation layer; in order to prevent from damaging or affecting the other parts of device in etching passivation layer process; should protect the remainder of device; therefore; adopted stable chemical nature, not played a protective role by PTFE film material covering chip other device areas in addition of etching or corrosion impact.Here the selection of thin-film material has multiple, so long as stable chemical nature, and not all can use by the thin-film material that RIE etching or acid liquid corrosion affect.According to the device chip size, polytetrafluoroethylmaterial material is carried out suitable cutting out, make it the exposed chip part, need simultaneously can the protected key plying and other position of device be not subjected to the impact of etching or corrosion.
The composition of the surface passivation layer of judgement chip; If be SiO
2, SiN
xOr the phosphorosilicate glass composition, adopt the RIE dry etching that chip is processed; If be the polyimides composition, adopt acid solution wet etching method or superlaser etching method that chip is processed; The RIE dry etching here is isotropic etching, by selecting different etching gas composition and proportioning, reaches passivation material large tracts of land, the even purpose of removing.Answer one-tenth component selections, proportional control and the etch period of attentive response gas in the removal process.Usually the etching gas composition that adopts is CF
4+ O
2, gas mixing ratio is 2:1, etching power is 80W, etching pressure 300 mTorr.In acid solution wet etching method, chip is placed in the wet chemistry mail opener, adopt various acid solutions to carry out splash at chip surface and process, according to the judgement to passivation material thickness, for the thicker passivation material of thickness, be generally greater than 5um, usually the H of selective etching speed
2SO
4As the corrosion acid solution, for the passivation material of thinner thickness, the selective etching acid solution is HNO usually
3Etching time is generally at 50-70 about second, and corrosion temperature is 80-90 ℃.
To again check by light microscope or energy disperse spectroscopy through the chip of above-mentioned processing, check whether chip surface also has passivation layer and composition thereof; If also have passivation layer, the processing procedure that repeats above-mentioned protection and remove passivation layer continues processing to chip, until the chip surface passivation layer is removed or reaches certain requirement.
After the passivation layer processing finishes, adopt absolute ethyl alcohol, acetone and other organic solvent that device chip is cleaned.
The below is three specific embodiments.
Embodiment one:
In the present embodiment, we carry out Destructive Physical Analysis as example take a plastic packaged integrated circuit device.According to the correlation test requirement of MIL-STD-883, adopt scanning electron microscopy that the metallization quality of device inside chip is checked.Because the device inside chip surface is manufactured with passivation layer, passivation material is non-conductive, and therefore, scanning electron microscopy can't directly check the metal quality of chip, must take certain passivation layer to remove means and could implement inspection.
Compare inspection by bonding region and peripheral region to chip.The metallization material of preliminary judgement chip is Al, and passivation material is SiO
2By energy disperse spectroscopy, the chip surface passivation layer is carried out analysis of components, confirm that passivation material is single SiO
2
After adopting the RIE dry etching, the chip surface metal layer is high-visible, can adopt scanning electron microscopy that the chip metallization quality is checked.
Embodiment two:
In the present embodiment, at first adopt HNO
3The polyimide film passivation layer of chemical wet etching chip surface, the SiO of rear employing RIE dry etching passivation layer lower floor
2, SiN
xOr phosphorosilicate glass.The concrete technology condition is: corrosion temperature is 80-90 ℃, and etching time is 50-70 second.
Chip scanning electron micrograph after the acid solution wet etching is observed, and still has around the metallization bar and does not corrode clean SiO
2Passivation material.If continue this moment to use acid solution to corrode, etching time is difficult to control, easily to aluminum metallization material body injury.Therefore, should select at this moment the RIE dry etching to continue SiO
2Passivation material is removed.
Adopt the RIE dry etching to remaining SiO
2Passivation material is proceeded etching.Etching condition is: etching gas CF
4: O
2=40:20, etching power 80W, etching pressure 300 mTorr.
Chip surface metal layer after treatment is high-visible.
Embodiment three:
In removing the passivation layer process, to protect the bonding of chip and device other position all the time.According to the chip area size, corrosion resistant thin-film material is cut out, cut out out the hole of a chip area size in the centre.Surrounding at protective film adopts adhesive plaster to be fixed.In etching process, protecting tool set-up is positioned on device chip, guarantee the aligned chip of protecting tool set-up thin film center.
Claims (7)
1. a chip passivation layer removal method, is characterized in that, comprises the following steps:
Step 1 obtains chip passivation composition of layer and thickness; Check by light microscope or the energy disperse spectroscopy bonding region to chip, at first obtain the composition of the surface passivation layer of chip, secondly according to color and the reflective difference of bonding region and peripheral region, the thickness of the passivation material of acquisition bonding region;
Step 2 is protected other device areas beyond chip; Adopt stable chemical nature, be not subjected to the thin-film material of etching or corrosion impact to cover chip other device areas in addition;
Step 3, the composition of the surface passivation layer of judgement chip is if be SiO
2, SiN
xOr the phosphorosilicate glass composition, adopt the RIE dry etching that chip is processed; If be the polyimides composition, adopt acid solution wet etching method or superlaser etching method that chip is processed;
Step 4 checks the chip after step 3 is processed again by light microscope or energy disperse spectroscopy, check whether chip surface also has passivation layer and composition thereof; If also have passivation layer, repeating step two and three is processed;
Step 5 is cleaned chip; Adopt organic solvent that device chip is cleaned.
2. a kind of chip passivation layer removal method according to claim 1, it is characterized in that: the thin-film material in described step 2 is polytetrafluoroethylene.
3. a kind of chip passivation layer removal method according to claim 1, it is characterized in that: the described RIE dry etching in described step 3 is isotropic etching, and the etching gas of employing is CF
4+ O
2, proportioning is 2:1, etching power is 80W, etching pressure 300 mTorr.
4. a kind of chip passivation layer removal method according to claim 1, is characterized in that: in the acid solution wet etching method of described step 3, chip is placed in the wet chemistry mail opener, carries out splash with acid solution at chip surface and process.
5. a kind of chip passivation layer removal method according to claim 4, it is characterized in that: described acid solution is sulfuric acid or nitric acid, during greater than 5um, uses sulfuric acid when passivation layer thickness, during less than 5um, uses nitric acid when passivation layer thickness.
6. according to claim 4 or 5 a kind of described chip passivation layer removal methods, it is characterized in that: in acid solution wet etching method, corrosion temperature is 80-90 ℃, etching time is 50-70 second.
7. a kind of chip passivation layer removal method according to claim 1, it is characterized in that: in described step 5, described organic solvent is absolute ethyl alcohol or acetone.
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Cited By (11)
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| CN104425238A (en) * | 2013-08-30 | 2015-03-18 | 中国科学院微电子研究所 | Hole forming method of single event effect test chip |
| CN104931513A (en) * | 2015-07-16 | 2015-09-23 | 四川蓝彩电子科技有限公司 | Method for checking internal circuit structure of encapsulated circuit components |
| CN106128939A (en) * | 2016-08-01 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | The method processing abnormal MIM capacitor dielectric layer |
| CN106876296A (en) * | 2017-01-03 | 2017-06-20 | 航天科工防御技术研究试验中心 | A kind of semiconductor device failure localization method |
| CN108987246A (en) * | 2017-05-31 | 2018-12-11 | 上海新微技术研发中心有限公司 | Method for removing chip packaging structure |
| CN109585343A (en) * | 2018-11-30 | 2019-04-05 | 京东方科技集团股份有限公司 | The stripping means of film layer is encapsulated in a kind of display panel |
| CN111089776A (en) * | 2019-12-23 | 2020-05-01 | 青岛歌尔微电子研究院有限公司 | Unsealing method of silver wire plastic package device |
| CN111207973A (en) * | 2020-01-14 | 2020-05-29 | 长江存储科技有限责任公司 | Unsealing method of chip |
| CN111710627A (en) * | 2020-05-28 | 2020-09-25 | 北京芯可鉴科技有限公司 | Chip packaging pretreatment method and chip analysis method |
| CN113945442A (en) * | 2021-10-15 | 2022-01-18 | 上海季丰电子股份有限公司 | Method for taking crystal grain in gallium arsenide chip packaging structure and application |
| CN117080066A (en) * | 2023-10-13 | 2023-11-17 | 深圳基本半导体有限公司 | Method for removing layer on surface layer of silicon carbide chip |
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| CN104425238A (en) * | 2013-08-30 | 2015-03-18 | 中国科学院微电子研究所 | Hole forming method of single event effect test chip |
| CN104931513A (en) * | 2015-07-16 | 2015-09-23 | 四川蓝彩电子科技有限公司 | Method for checking internal circuit structure of encapsulated circuit components |
| CN106128939A (en) * | 2016-08-01 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | The method processing abnormal MIM capacitor dielectric layer |
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| CN109585343A (en) * | 2018-11-30 | 2019-04-05 | 京东方科技集团股份有限公司 | The stripping means of film layer is encapsulated in a kind of display panel |
| CN111089776A (en) * | 2019-12-23 | 2020-05-01 | 青岛歌尔微电子研究院有限公司 | Unsealing method of silver wire plastic package device |
| CN111207973A (en) * | 2020-01-14 | 2020-05-29 | 长江存储科技有限责任公司 | Unsealing method of chip |
| CN111710627A (en) * | 2020-05-28 | 2020-09-25 | 北京芯可鉴科技有限公司 | Chip packaging pretreatment method and chip analysis method |
| CN111710627B (en) * | 2020-05-28 | 2024-03-01 | 北京芯可鉴科技有限公司 | Chip packaging pretreatment method and chip analysis method |
| CN113945442A (en) * | 2021-10-15 | 2022-01-18 | 上海季丰电子股份有限公司 | Method for taking crystal grain in gallium arsenide chip packaging structure and application |
| CN113945442B (en) * | 2021-10-15 | 2022-05-20 | 上海季丰电子股份有限公司 | Method for taking crystal grain in gallium arsenide chip packaging structure and application |
| CN117080066A (en) * | 2023-10-13 | 2023-11-17 | 深圳基本半导体有限公司 | Method for removing layer on surface layer of silicon carbide chip |
| CN117080066B (en) * | 2023-10-13 | 2024-01-26 | 深圳基本半导体有限公司 | Method for removing layer on surface layer of silicon carbide chip |
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