CN103151005A - Driving method of liquid crystal display - Google Patents
Driving method of liquid crystal display Download PDFInfo
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- CN103151005A CN103151005A CN2013100368964A CN201310036896A CN103151005A CN 103151005 A CN103151005 A CN 103151005A CN 2013100368964 A CN2013100368964 A CN 2013100368964A CN 201310036896 A CN201310036896 A CN 201310036896A CN 103151005 A CN103151005 A CN 103151005A
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Abstract
The invention provides a driving method of a liquid crystal display, and the liquid crystal display includes a liquid crystal panel component, a plurality of scanning lines and data lines which are limited in a cross mode, a source electrode actuator, a grid electrode actuator and a time schedule controller. An image processor is arranged inside the time schedule controller, the image processor outputs a normal picture frame in a cross mode and produces a black picture frame, and scanning frequencies of the normal picture frame and the adjacent black picture frame are different. When pictures of the display are output, the adjacent two pictures utilize different picture frame scanning frequencies; due to the fact that the picture frame scanning frequencies directly affect the charging time of pixels, the faster the picture frame scanning frequency is, the shorter the charging time is. By increasing the black picture frame scanning frequency and decreasing the normal picture frame scanning frequency, the driving method of the liquid crystal display can greatly increase the charging time of the pixels of the normal picture frame. Frequency doubling is carried out over clock signals which are input from the exterior and are provided for an internal circuit to carry out a picture frame scanning frequency modulation, so that the purpose of regulating a duty ratio between the two adjacent pictures is achieved.
Description
Technical field
The present invention relates to a kind of driving method of liquid crystal display, relate in particular to the driving method of black plug driving circuit.
Background technology
Black insertion technology is mainly used at present and solves the image smear that continues escope, the conventional cathode ray tube display adopts the pulsed display mode, impact light-emitting phosphor by electron beam, the aura residence time is extremely short, response time is only 1～3 millisecond, continue escope such as liquid crystal display, utilize liquid crystal molecule to reverse the break-make of controlling light, draw auspicious lower lasting output light in one, the impact that the lasting escope of this kind persists due to human eye vision, the serious smear of image can occur when causing Picture switch, therefore can improve this motion blur phenomenon by black insertion technology.
Black insertion technology inserts a black picture between display frame, utilize this mode to imitate the pulsed display mode and improve the image smear, because black insertion technology is to increase a black picture, picture update rate can increase to twice, take the liquid crystal display of full HD resolution 1920*1080, picture update rate 60Hz as example, the duration of charging of its pixel is about 15 microseconds, if the collocation black insertion technology duration of charging is remaining 7.5 microseconds only, easily cause the picture element undercharge, therefore adopt black insertion technology need first overcome the problem of picture element duration of charging deficiency.
Figure 1 shows that the drives schematic diagram of available liquid crystal display, liquid crystal display comprises: liquid crystal panel assembly (PANEL) 10, be connected to source electrode driver (Data Drive IC) 20 and the gate drivers (Scan Drive IC) 30 of liquid crystal panel assembly 10, be connected to the grayscale voltage maker (Gamma Voltage Generator) 40 of source electrode driver 20, the time schedule controller (TCON) 50 that is used for control gate driver 30 and source electrode driver 20, and the DC-DC power supply (DC/DC) 60 that power supply is provided for liquid crystal display.Liquid crystal panel assembly 10 comprise lower display panel and the upper display panel of mutual correspondence and be folded in display panel and lower display panel between liquid crystal.
Suppose that the liquid crystal display horizontal direction has m bar sweep trace, vertical direction has n bar data line, is combined into the liquid crystal display of a n*m pixel, and sweep trace and data line intersect and limit a plurality of film crystal pipe unit PX.A plurality of film crystal pipe unit PX are matrix form and arrange, film crystal pipe unit PX is connected with display signal line, display signal line is disposed on lower display panel, and comprises that the multi-strip scanning line G0 that transmits signal is to many data line S1 of Gm and transmission of data signals to Sn.Sweep trace G0 extends in the horizontal direction and is parallel to each other to Gm, and data line S1 extends in vertical direction and is parallel to each other to Sn.
Each pixel PX comprises thin film transistor (TFT), liquid crystal capacitance and memory capacitance, thin film transistor (TFT) comprises the grid (Gate) that forms, the source electrode (Source) that is connected with data line and the drain electrode (Drain) that is connected with pixel electrode together with sweep trace, memory capacitance is connected to thin film transistor (TFT) abreast.
Grayscale voltage maker 40 generates the grayscale voltage relevant to the transparency of pixel PX, and grayscale voltage is provided for each pixel PX, and grayscale voltage comprises with respect to the positive polarity voltage of common electric voltage Vcom and reverse voltage.
Time schedule controller 50 control gate drivers 30 and source electrode driver 20, time schedule controller 50 receives received image signal (R, G, B) and input control signal, demonstration with the control inputs picture signal, for example, vertical synchronizing signal Vsync, horizontal-drive signal Hsync, clock control signal CLK and the data from the external graphics controller (not shown) can make signal DE.Time schedule controller 50 is according to the operating conditions of liquid crystal panel assembly 10, suitably process received image signal and input control signal, produce grid control signal CONT1 and data controlling signal CONT2, grid control signal CONT1 is sent to gate drivers 30, and the picture signal DAT of data controlling signal CONT2 and processing is sent to source electrode driver 20.
Grid control signal CONT1 comprises when scanning initialize signal STV exports gate-on voltage Von with initialization scan and at least one clock signal C PV to control.Grid control signal CONT1 can also comprise the duration (duration) of output enable signal OE to define gate turn-on signal Von.
Data controlling signal CONT2 comprise horizontal-drive signal with notification source driver 20 for the beginning of the data transmission of one group of pixel, be written into signal LOAD and with indication source electrode driver 20, data voltage be applied to S1 to Sn and data clock signal HCLK.Data controlling signal CONT2 can also comprise that reverse signal RSV is with the polarity with respect to common electric voltage Vcom reversal data voltage.
Liquid crystal display described according to Fig. 1 is by received image signal (R, G, B) and input timing control signal, with the demonstration of control inputs picture signal.
Available liquid crystal Display Driver mode adopts the mode of lining by line scan, there is sweep trace to open thin film transistor (TFT) on liquid crystal display on horizontal direction, sweep signal is called again signal (Gate output), there is data line that pixel data voltage is provided on vertical direction, data-signal is called again source signal (Source output), data line can be with the from top to bottom output line by line of data of image, sweep trace can from top to bottom be opened thin film transistor (TFT) line by line, makes in the view data writing pixel.
Fig. 2 is the drive waveforms of conventional liquid crystal, STV is the signal that gate drivers 30 triggers, CPV is the clock signal CLK of gate drivers 30, adopt the positive edge of CPV to trigger during driving, when the positive edge of CPV is triggered to STV and is high levle, article one, sweep trace output signal (Gate output1) can be sent the high voltage level with the thin film transistor (TFT) conducting on article one horizontal line in panel, and collocation source signal (Source output) is sent article one horizontal line data of image, data voltage is write in article one horizontal pixel, general display upper film transistor turns voltage is 20V～30V, close voltage be about-5V～-7V, after each sweep trace output signal (Gate output N) is sent the high voltage level, can trigger next sweep trace output signal (Gate output N+1) and send the high voltage level when the positive edge of next CPV, so from top to bottom sequentially line by line with the data writing pixel, after data write to the last item horizontal line pixel, can send again the high levle trigger pip by STV after a period of time, this time is called vertical blank (V Blank), the cycle of STV is one and draws the auspicious time, with resolution 1366*768, the liquid crystal display of picture update rate 60Hz, each draws the auspicious time is the 1/60=16.67 millisecond, each draws auspicious lower every horizontal duration of charging is the 1/60/806=20.67 microsecond, 806 add vertical blank (38) for the number of horizontal display line (768), adopt black insertion technology if calculate according to this this liquid crystal display, picture update rate can doubly increase to 120Hz (60 normal picture picture frames, 60 black picture frames), each auspicious lower every horizontal duration of charging of picture is the 1/120/806=10.34 microsecond, every the horizontal duration of charging has reduced by 10.34 microseconds, easily cause the pixel undercharge.
Fig. 3 is the driven of available liquid crystal display and the schematic diagram of black plug type of drive contrast, and driven only has the image picture frame; Black plug drives for the picture frame turnover rate is doubled, and inserts a black plug picture frame between the image picture frame, can improve image streaking, also can be applicable to switching regulator glasses three-dimensional display.
There is following shortcoming in it:
1, the dutycycle of normal pictures and black picture is that 1:1 can't adjust.
2, double to make the duration of charging to reduce by half the picture frame number, easily cause panel picture element undercharge or panel resolution to improve.
Summary of the invention
The object of the present invention is to provide the sweep frequency that changes adjacent two picture frames, the dutycycle of regulation and control normal picture and black picture, the driving method that accelerates efficient and the liquid crystal display in the duration of charging that the increase image writes picture of black picture writing pixel.
The invention provides a kind of driving method of liquid crystal display, liquid crystal display comprises: liquid crystal panel assembly, the some sweep traces that intersect to limit and data line, the source electrode driver that is connected to the liquid crystal panel assembly and gate drivers, be used for the time schedule controller of control gate driver and source electrode driver, be provided with image processor in described time schedule controller, image processor intersects to be exported normal picture frame and produces black picture frame, and normal picture frame is different from adjacent black picture frame sweep frequency.
Dutycycle when wherein, normal picture frame is exported from adjacent black picture frame is different.
Wherein, be provided with phase-locked loop, picture buffer, described image processor, frequency multiplier, frequency eliminator one and frequency eliminator two in described time schedule controller, driving method is as follows: view data inputs to phase-locked loop and picture buffer simultaneously by the outside; The phase-locked loop offers reference clock signal CLK of view data, and reference clock signal CLK offers image processor and frequency multiplier; View data can be sent to image processor after picture buffer; Frequency multiplier is with reference to the clock signal frequency multiplication and offer frequency eliminator one and frequency eliminator two; The clock signal that frequency eliminator one produces, and the clock signal that produces of frequency eliminator two all offer image processor, and reference when reference when the clock signal that frequency eliminator one produces is exported as data for the normogram block diagram, the clock signal that frequency eliminator two produces are exported for black picture frame view data; The black picture frame of the image processor normal picture frame of output and generation also sequentially offers source electrode driver and gate drivers and drives the liquid crystal panel assembly.
The present invention is when the picture output of display, adjacent two pictures adopt different picture frame sweep frequencies, directly affect the duration of charging of pixel due to the picture frame sweep frequency, the picture frame sweep frequency more the charging quickly time shorter, the present invention deceives the picture frame sweep frequency by increase and reduces normal picture frame sweep frequency, can significantly increase the duration of charging of the pixel of normal picture frame; Although the black picture frame pixel duration of charging reduces, under black insertion technology is used, open simultaneously multi-strip scanning line (two more than sweep trace) under the black plug picture, carry out writing of black voltage, because full frame is all the rank voltage that shines together mutually, the problem without wrongly writing voltage can increase the pixel duration of charging; By offering the modulation that internal circuit carries out the picture frame sweep frequency after the clock signal frequency multiplication with outside input, with the purpose of the dutycycle that reaches adjacent two pictures of regulation and control.
Description of drawings
Fig. 1 is the drives schematic diagram of available liquid crystal display;
Fig. 2 is the drive waveforms figure of conventional liquid crystal;
Fig. 3 is the driven of available liquid crystal display and the schematic diagram of black plug type of drive contrast;
Fig. 4 is the circuit structure diagram that black plug of the present invention drives;
Fig. 5 is the drive waveforms figure of the first embodiment of liquid crystal display of the present invention;
Fig. 6 is the drive waveforms figure of the second embodiment of liquid crystal display of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
The present invention discloses a kind of liquid crystal display, as shown in Figure 1, liquid crystal display comprises: the source electrode driver of liquid crystal panel assembly (PANEL) 10, liquid crystal panel assembly 10 (Data Drive IC) 20 and gate drivers (Scan Drive IC) 30, be connected to source electrode driver 20 grayscale voltage maker (Gamma Voltage Generator) 40, be used for control gate driver 30 and the time schedule controller (TCON) 50 of source electrode driver 20 and the DC-DC power supply (DC/DC) 60 that power supply is provided for liquid crystal display.Liquid crystal panel assembly 10 comprise lower display panel and the upper display panel of mutual correspondence and be folded in display panel and lower display panel between liquid crystal.
Fig. 4 is the circuit structure diagram that black plug of the present invention drives, can be through phase-locked loop 101 and picture buffer 102 after the input of external image data, the function of phase-locked loop 101 is can be synchronous when outside and internal image data are processed, the function of picture buffer 102 is the external image data to be stored to process for image processor in internal memory use, phase-locked loop 101 with can produce a reference clock signal CLK after external image signal is synchronizeed, this reference clock signal (CLK) can offer image processor 103 and frequency multiplier 104, frequency multiplier 104 can and offer frequency eliminator 1 and frequency eliminator 2 106 with reference to the clock signal frequency multiplication, and phase-locked loop 101 is with reference to clock signal clk, and frequency multiplier 104 inputs to image processor 103 with reference clock signal vertical synchronization after frequency multiplication, the clock signal that frequency eliminator 1 produces offers image processor 103, purpose is the reference when supplying the output of normal picture picture frame image data, the clock signal that frequency eliminator 2 106 produces also offers image processor 103, purpose is the reference when supplying black picture frame image data output, and image processor 103 functions are that the black picture frame of output image picture frame and generation also sequentially offers source electrode driver 20 with gate drivers 30 and drives liquid crystal panel assembly 10.
Phase-locked loop 101, picture buffer 102, image processor 103, frequency multiplier 104, frequency eliminator 1 and frequency eliminator 2 106 are equipped with in time schedule controller (TCON) 50.
When view data is inputted by the outside, synchronize with external signal by phase-locked loop 101; And deposit the image of input in picture buffer 102, and can provide a reference clock signal CLK after phase-locked loop 101 is synchronous, reference clock signal CLK function is the fundamental frequency when supplying with other circuit operation; View data can be delivered to image processor 103 after depositing picture buffer 102 in, can additionally insert a black picture during image processor 103 output picture, does not need the black picture of outside input.
The described driving method of Fig. 4 is as follows:
View data inputs to phase-locked loop 101 and picture buffer 102 simultaneously by the outside;
Phase-locked loop 101 offers reference clock signal CLK of view data, and reference clock signal CLK offers image processor 103 and frequency multiplier 104; View data can be sent to image processor 103 after picture buffer 102;
Phase-locked loop 101 with reference to clock signal clk, and frequency multiplier 104 reference clock signal vertical synchronization after frequency multiplication is inputed to image processor 103;
The clock signal that frequency eliminator 1 produces, and the clock signal that produces of frequency eliminator 2 106 all offer image processor 103, and reference when reference when the clock signal that frequency eliminator 1 produces is exported as data for the normogram block diagram, the clock signal that frequency eliminator 2 106 produces are exported for black picture frame view data;
The image processor 103 normal picture frames of output and the black picture frame of generation also sequentially offer source electrode driver 20 with gate drivers 30 and drive liquid crystal panel assembly 10.
In the present embodiment, frequency multiplier 104 is taken advantage of four times with reference to clock signal frequency, but in actual design, frequency multiplier 104 also can be taken advantage of six times, octuple or more times with reference to clock signal frequency, the cycle of frequency eliminator 1 neither 3/4*TCLK so, the cycle of frequency eliminator 2 106 neither 1/4*TCLK, and normal picture frame carries out adjusted design according to actual needs with the dutycycle that adjacent black picture frame is exported.
Figure 5 shows that the schematic diagram of the first embodiment of the drive waveforms of black plug driving circuit shown in Figure 4, CLK is the reference clock signal that phase-locked loop 101 produces, its cycle is TCLK, CLKx4 is the clock signal that reference clock signal produces after frequency multiplier 104, the CLKx4 frequency is 4 times of CLK, its cycle is 1/4TCLK, and this multiplying power explains take dutycycle as 3:1 at the present embodiment according to the dutycycle design of normal picture frame and the output of black picture frame.
STV is that gate drivers 20 drives trigger pip, and CPV is the clock signal that gate drivers 20 drives, and is mainly with reference to STV and CPV during the gate driver circuit action, twice high levle of STV output under the time of a picture auspicious (1Frame) in Fig. 6.
During STV high levle output for the first time, the frequency of CPV operation is f display, the reference clock signal of this moment is the clock signal of frequency eliminator 1, clock signal period is 3/4TCLK, source electrode driver 20 output this moment normal picture picture frames, the liquid crystal panel assembly is according to conventional ADS driving mode data writing one by one from top to bottom; During STV high levle output for the second time, the frequency of CPV operation is f black, the reference clock signal of this moment is the clock signal of frequency eliminator 2 106, the clock signal cycle is 1/4TCLK, this moment, picture frames were deceived in source electrode driver 20 outputs, and the liquid crystal panel assembly from top to bottom writes black picture one by one according to the conventional ADS driving mode.
the clock signal of its CPV action time institute's reference of normal picture picture frame and black picture frame is different, the ratio of its operating frequency f display and f black is 1:3, suppose that the display picture element duration of charging without black insertion technology is Tcharge, traditional black insertion technology type of drive of arranging in pairs or groups is because the ratio of normal picture picture frame and black picture frame is 1:1, its image picture frame duration of charging is all 1/2Tcharge mutually with the black plug duration of charging, adopting the image picture frame duration of charging of the present invention is 3/4Tcharge, more traditional black insertion technology increases 1/4TCLK, can improve the pixel undercharge, the black picture frame pixel duration of charging is 1/4Tcharge, more traditional black insertion technology reduces 1/4TCLK.
Due to pixel undercharge under black picture frame, this shortcoming is improved by the embodiment of the present invention two, by the ratio of embodiment one by adjustment frequency eliminator one and frequency eliminator two, can regulate and control the pixel duration of charging ratio of normal picture picture frame and black picture frame, the technology of the present invention can be according to the charge characteristic of panel pixel, multiplying power by design frequency multiplier and frequency eliminator makes panel reach the best image characteristic.
Figure 6 shows that the schematic diagram of the second embodiment of the drive waveforms of black plug driving circuit shown in Figure 4, CLK is the reference clock signal that phase-locked loop 101 produces, its cycle is TCLK, CLKx4 is the clock signal that reference clock signal produces after frequency multiplier 104, the CLKx4 frequency is 4 times of CLK, its cycle is 1/4TCLK, this multiplying power is according to the dutycycle design of normal picture frame and the output of black picture frame, the present embodiment explains take dutycycle as 3:1, STV is that gate drivers 20 drives trigger signals, CPV is the clock signal that gate drivers 20 drives, mainly with reference to STV and CPV during the gate driver circuit action, twice high levle of STV output under the time of a picture auspicious (1Frame) in Fig. 7.
During STV high levle output for the first time, the frequency of CPV operation is f display, the reference clock signal of this moment is the clock signal of frequency eliminator 1, clock signal period is 3/4TCLK, this moment source electrode driver output image picture frame, the liquid crystal panel assembly is according to conventional ADS driving mode data writing one by one from top to bottom; During STV high levle output for the second time, the frequency of CPV operation is f black, the reference clock signal of this moment is the clock signal of frequency eliminator 2 106, clock signal period is 1/4TCLK, the black picture frame of source signal output this moment, keep at least two CPV cycles during STV output high levle, make gate drivers output become the width at least two CPV cycles, can open pixel at least two sweep traces in the same time, the liquid crystal panel assembly from top to bottom writes black picture.
In the present embodiment, keep four CPV cycles during STV output high levle, make gate drivers output become the width in four CPV cycles, can open pixel at least four sweep traces in the same time, the liquid crystal panel assembly from top to bottom writes black picture.
Because the pixel on each sweep trace under black picture frame all will write black voltage, therefore opening simultaneously the multi-strip scanning line does not have the problem of wrongly writing voltage, second STV output high levle width on-fixed in the present embodiment, can adjust width according to the condition of different panels, this practice can thoroughly solve the problem of deceiving pixel duration of charging deficiency under picture in motion embodiment one.
The present invention is when the picture output of display, adjacent two pictures adopt different picture frame sweep frequencies, directly affect the duration of charging of pixel due to the picture frame sweep frequency, the picture frame sweep frequency more the charging quickly time shorter, the present invention deceives the picture frame sweep frequency by increase and reduces normal picture frame sweep frequency, can significantly increase the duration of charging of the pixel of normal picture frame; Although the black picture frame pixel duration of charging reduces, under black insertion technology is used, open simultaneously multi-strip scanning line (two more than sweep trace) under the black plug picture, carry out writing of black voltage, because full frame is all the rank voltage that shines together mutually, the problem without wrongly writing voltage can increase the pixel duration of charging; By offering the modulation that internal circuit carries out the picture frame sweep frequency after the clock signal frequency multiplication with outside input, with the purpose of the dutycycle that reaches adjacent two pictures of regulation and control.
Advantage of the present invention is as follows:
1. hardware and the transmission of data form of the input of front end image need not be revised, the function of inserting black picture can be reached easily.
2. reduce the data traffic of front end input, can reduce the frequency of cabling and reduction clock signal.
3. adjust the ratio of frequency multiplier and frequency eliminator, can adjust easily the ratio of inserting black picture.
4. can open simultaneously the multi-strip scanning line under the black plug picture frame, increase the duration of charging of ability and the growth normal pictures of writing pixel black voltage.
Claims (10)
1. the driving method of a liquid crystal display, liquid crystal display comprises: liquid crystal panel assembly, the some sweep traces that intersect to limit and data line, the source electrode driver that is connected to the liquid crystal panel assembly and gate drivers, be used for the time schedule controller of control gate driver and source electrode driver, it is characterized in that: be provided with image processor in described time schedule controller, image processor intersects to be exported normal picture frame and produces black picture frame, and normal picture frame is different from adjacent black picture frame sweep frequency.
2. the driving method of liquid crystal display according to claim 1, it is characterized in that: the dutycycle when normal picture frame is exported with adjacent black picture frame is different.
3. the driving method of liquid crystal display according to claim 1, it is characterized in that: be provided with phase-locked loop, picture buffer, described image processor, frequency multiplier, frequency eliminator one and frequency eliminator two in described time schedule controller, driving method is as follows:
View data inputs to phase-locked loop and picture buffer simultaneously by the outside;
The phase-locked loop offers reference clock signal CLK of view data, and reference clock signal CLK offers image processor and frequency multiplier; View data can be sent to image processor after picture buffer;
Frequency multiplier is with reference to the clock signal frequency multiplication and offer frequency eliminator one and frequency eliminator two;
The clock signal that frequency eliminator one produces, and the clock signal that produces of frequency eliminator two all offer image processor, and reference when reference when the clock signal that frequency eliminator one produces is exported as data for the normogram block diagram, the clock signal that frequency eliminator two produces are exported for black picture frame view data;
The black picture frame of the image processor normal picture frame of output and generation also sequentially offers source electrode driver and gate drivers and drives the liquid crystal panel assembly.
4. the driving method of liquid crystal display according to claim 3 is characterized in that: the phase-locked loop with reference to clock signal clk, and frequency multiplier with frequency multiplication after the reference clock signal vertical synchronization input to image processor.
5. the driving method of liquid crystal display according to claim 3 is characterized in that: described frequency multiplier is taken advantage of four times and export to frequency eliminator one and frequency eliminator two with reference to the clock signal clk frequency; Frequency eliminator one with the clock signal of frequency multiplication again frequency reducing be 3/4ths, its cycle is 3/4*TCLK; 2 106 clock signal frequency reducings with frequency multiplication of frequency eliminator are 1/4th, and its cycle is 1/4*TCLK; The dutycycle of normal picture frame and the output of black picture frame is 3:1.
6. the driving method of liquid crystal display according to claim 3, it is characterized in that: setting STV is the gate driver drive trigger pip, CPV is the clock signal of gate driver drive, the frequency of CPV operation is fdisplay when STV high levle output for the first time, the reference clock signal of this moment is the clock signal of frequency eliminator one, clock signal period is 3/4TCLK, and source electrode driver output normal picture picture frame, liquid crystal panel assembly be data writing one by one from top to bottom; When STV high levle output for the second time, the frequency of CPV operation is fblack, and the reference clock signal of this moment is the clock signal of frequency eliminator two, and the clock signal cycle is 1/4TCLK, the black picture frame of source electrode driver output, the liquid crystal panel assembly from top to bottom writes black picture one by one.
7. the driving method of liquid crystal display according to claim 3, it is characterized in that: setting STV is the gate driver drive trigger pip, CPV is the clock signal of gate driver drive, the frequency of CPV operation is fdisplay when STV high levle output for the first time, the reference clock signal of this moment is the clock signal of frequency eliminator one, clock signal period is 3/4TCLK, and source electrode driver output normal picture picture frame, liquid crystal panel assembly be data writing one by one from top to bottom; The frequency of CPV operation is f black when STV high levle output for the second time, the reference clock signal of this moment is the clock signal of frequency eliminator two, clock signal period is 1/4TCLK, the black picture frame of source signal output this moment, keep at least two CPV cycles during STV output high levle, make gate drivers output become the width at least two CPV cycles, can open pixel at least two sweep traces in the same time, the liquid crystal panel assembly from top to bottom writes black picture.
8. the driving method of liquid crystal display according to claim 7, is characterized in that: keep four CPV cycles during STV output high levle, make gate drivers output become the width in four CPV cycles, can open four pixels on sweep trace in the same time.
9. the driving method of according to claim 6-8 described arbitrary liquid crystal display, it is characterized in that: the ratio of operating frequency fdisplay and f black is 1:3.
10. the driving method of according to claim 1-3 described arbitrary liquid crystal display, is characterized in that: the adjacent two different vertical scanning frequencies of pictures employing.
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| CN103617785A (en) * | 2013-11-29 | 2014-03-05 | 青岛海信电器股份有限公司 | Three-dimensional liquid crystal display device and display control method |
| CN103928010A (en) * | 2014-05-04 | 2014-07-16 | 深圳市华星光电技术有限公司 | Data driving circuit for driving liquid crystal display panel and driving method of liquid crystal display panel |
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