CN103137547A - Si/NiSi 2 substrate material on insulator and preparation method thereof - Google Patents

Si/NiSi 2 substrate material on insulator and preparation method thereof Download PDF

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Publication number
CN103137547A
CN103137547A CN201110384239XA CN201110384239A CN103137547A CN 103137547 A CN103137547 A CN 103137547A CN 201110384239X A CN201110384239X A CN 201110384239XA CN 201110384239 A CN201110384239 A CN 201110384239A CN 103137547 A CN103137547 A CN 103137547A
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layer
nisi
preparation
backing material
substrate
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俞文杰
张波
赵清太
狄增峰
张苗
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

The invention provides a Si/ CoSi 2 substrate material on an insulator and a preparation method thereof. The preparation method comprises that NiSi 2 is generated through the fact that an annealing reaction is conducted on a Ni substrate and a Si substrate, the NiSi 2 is transferred through an intelligent peeling technology, a layer of metal silicide NiSi 2 is inserted between a BOX layer and a top layer of silicon of a traditional silicon on insulator (SOI) substrate, so that a heavy doping buried layer of a collector region in a conventional SOI bipolar transistor is replaced, and the purposes of reducing the thickness of the top layer of the silicon, simplifying a technology and the like are achieved. The technology of the preparation method is simple and is suitable for large-scale industrial production.

Description

Si/NiSi on a kind of insulator 2Backing material and preparation method thereof
Technical field
The invention belongs to semiconductor applications, particularly relate to Si/NiSi on a kind of insulator 2Backing material and preparation method thereof.
Background technology
SOI (SiliNin-On-Insulator, the silicon on dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and backing to bury oxide layer.By forming semiconductive thin film on insulator, the SOI material had advantages of body silicon incomparable: can realize the medium isolation of components and parts in integrated circuit, thoroughly eliminate the parasitic latch-up in the Bulk CMOS circuit; Adopt integrated circuit that this material is made to have also that parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little and be specially adapted to the advantage such as low voltage and low power circuits, therefore can say that SOI might become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.
At the bottom of traditional SOI substrate comprises backing, top layer silicon on insulating barrier and insulating barrier, the manufacturing of general bipolar circuit, BiCMOS circuit need to be made collector region heavy doping buried regions in the traditional SOI top layer silicon, to reduce collector resistance and the puncture voltage that increases substrate, but, such manufacturing process steps is complicated, and has taken the space of part top layer silicon, has increased the thickness of top layer silicon.
Summary of the invention
The shortcoming of prior art, the object of the present invention is to provide Si/NiSi on a kind of insulator in view of the above 2Backing material and preparation method thereof inserts layer of metal silicide NiSi between the insulating barrier of traditional SOI substrate and top layer silicon 2, replacing the collector region heavy doping buried regions in conventional SOI bipolar transistor, thereby reach the thickness that reduces the required top layer silicon of bipolar circuit, simplify the purpose such as technique.
Reach for achieving the above object other relevant purposes, the invention provides Si/NiSi on a kind of insulator 2The preparation method of backing material, described preparation method comprises the following steps at least: 1) a Si substrate is provided, forms the Ni layer at a described Si substrate surface, then anneal for the first time so that a described Si substrate and the reaction of described Ni layer generate NiSi 2Layer is then removed unreacted described Ni layer; 2) at described NiSi 2Layer surface forms a SiO 2Then layer carries out the H Implantation and peels off the interface to form at a described Si substrate; 3) provide and have the 2nd SiO 2The 2nd Si substrate of layer, and described the 2nd SiO of bonding 2Layer and a described SiO 2The layer, then anneal for the second time so that a described Si substrate from the described interface peel of peeling off, at last to the stripper surface polishing to complete preparation.
In preparation method of the present invention, described step 1) also comprise a described Si substrate is carried out the step that the wet chemistry ablution of standard cleans.
Preferably, described step 1) in, the described Ni layer of deposit in vacuum environment, the Ni layer thickness of deposit is 1～4nm.
In preparation method of the present invention, described annealing atmosphere for the first time is N 2Atmosphere, annealing temperature are 300～1000 ℃, and annealing time is 10～60 seconds.
In preparation method of the present invention, selecting mol ratio is the H of 4: 1 2SO 4: H 2O 2Solution adopts wet etching to remove described Ni layer, and etch period is 1 minute.
In preparation method of the present invention, the using plasma deposition technique is at the described SiO of surface deposition 2Layer, thickness is 100～600nm.Described step 2) form a described SiO in 2Also comprise the step that it was annealed 1 hour after layer under 900 ℃.Described step 2) also comprise a described SiO after the H Implantation in 2The step that layer carries out polishing.
In preparation method of the present invention, adopt thermal oxidation process to form described the 2nd SiO2 layer at described the 2nd Si substrate surface, thickness is 200～300nm.
In preparation method of the present invention, described annealing atmosphere for the second time is N 2Atmosphere, annealing temperature are 200～800 ℃, and annealing time is 30 minutes.
In preparation method of the present invention, described step 3) also comprise and anneal for the third time to strengthen described the 2nd SiO 2Layer and a described SiO 2The step of the bonding of layer.Described annealing atmosphere for the third time is N 2Atmosphere, annealing temperature are 500～1000 ℃, and annealing time is 30～240 minutes.
The present invention also provides Si/NiSi on a kind of insulator 2Backing material is characterized in that, comprises at least: the Si substrate; In conjunction with the insulating barrier of described Si substrate surface; Be incorporated into the NiSi of described surface of insulating layer 2Layer; And be incorporated into described NiSi 2The Si top layer on layer surface.
Si/NiSi on insulator of the present invention 2In backing material, described NiSi 2The thickness of layer is 3～10nm.The thickness of described Si top layer is 5～200nm.
As mentioned above, Si/NiSi on insulator of the present invention 2Backing material and preparation method thereof has following beneficial effect: by Ni and Si substrate are carried out annealing reaction generation NiSi 2, and by smart-cut process, it is shifted, to insert layer of metal silicide NiSi between the BOX of traditional SOI substrate layer and top layer silicon 2, replacing the collector region heavy doping buried regions in conventional SOI bipolar transistor, reduce top layer silicon thickness, simplify the purpose such as technique thereby reach.Technique of the present invention is simple, is applicable to large-scale industrial production.
Description of drawings
Fig. 1～Fig. 3 is shown as Si/NiSi on insulator of the present invention 2Preparation method's step 1 of backing material) structural representation that presents in.
Fig. 4～Fig. 5 is shown as Si/NiSi on insulator of the present invention 2Preparation method's step 2 of backing material) structural representation that presents in.
Fig. 6～Fig. 9 is shown as insulator Si/NiSi of the present invention 2Preparation method's step 3 of backing material) structural representation that presents in.
The element numbers explanation
111 the one Si substrates
112 Ni layers
113 NiSi 2Layer
114 the one SiO 2Layer
122 SiO 2Layer
121 Si substrates
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under spirit of the present invention not deviating from.
See also Fig. 1 to Fig. 9.Need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Embodiment 1
As Fig. 1～shown in Figure 9, the invention provides a kind of insulator Si/NiSi 2The preparation method of backing material, described preparation method comprises the following steps at least:
See also Fig. 1～Fig. 3, as shown in the figure, at first carry out step 1), a Si substrate 111 is provided, a described Si substrate 111 is common Silicon Wafer, then a described Si substrate 111 is carried out the wet chemistry ablution cleaning of standard, to remove its surperficial foreign ion and blemish, form Ni layer 112 in a described surperficial method by deposit of Si substrate 111 under the environment of vacuum, the Ni layer thickness of deposit is 1～4nm, in the present embodiment, the thickness of described Ni layer 112 is 3nm.Then above-mentioned resulting structures is annealed for the first time, annealing is at N 2Carry out under atmosphere, annealing temperature is 300～1000 ℃, and annealing time can be 10～60 seconds, and in the present embodiment, annealing temperature is 550 ℃, so that a described Si substrate 111 generates NiSi with described Ni layer 112 reaction 2Layer 113, then selecting mol ratio is the H of 4: 1 2SO 4: H 2O 2Solution adopts wet etching to remove described unreacted Ni layer 112;
See also Fig. 4～Fig. 5, as shown in the figure, then carry out step 2), at described NiSi 2The surperficial using plasma deposition technique of layer 114 forms a SiO 2Layer 114, in the present embodiment, a described SiO 2The thickness of layer 114 is 100～600nm; Then according to demand with specific energy with specific angle to a described SiO 2Layer 114 carries out the H Implantation, peels off the interface to form at a Si substrate 111, then to a described SiO 2 Layer 114 uses the chemical mechanical polishing method to carry out polishing, with its thickness of attenuate, at last above resulting structures is annealed, and annealing temperature is 900 ℃, and annealing time is 1 hour, so that its easier bonding;
See also Fig. 6～Fig. 9, as shown in the figure, carry out step 3 at last), provide to have the 2nd SiO 2The 2nd Si substrate 121 of layer 122, in the present embodiment, described the 2nd Si substrate 122 is common Silicon Wafer, then described silicon wafer surface is carried out thermal oxidation to obtain the 2nd SiO 2Layer 122, in the present embodiment, described the 2nd SiO 2The thickness of layer 122 is 200～300nm, described the 2nd SiO of bonding 2Layer 122 and a described SiO 2 Layer 114 is to form bonding SiO 2The layer 123, then anneal for the second time so that a described Si substrate 111 from the described interface peel of peeling off, in concrete implementation process, at N 2In atmosphere, the later structure of para-linkage is annealed for the second time, annealing temperature is 200～800 ℃, annealing time is 30 minutes, in the present embodiment, annealing temperature is 500 ℃, the described H ion of peeling off near interface is assembled gradually and formed bubble, air bubble expansion finally makes a described Si substrate 111 peel off separation at the interface, then, the structure after separating is annealed for the third time, annealing atmosphere is N 2Atmosphere, annealing temperature are 500～1000 ℃, and annealing time is 30～240 minutes, and in the present embodiment, annealing temperature is 800 ℃, to strengthen described the 2nd SiO 2Layer 122 and a described SiO 2Bond strength between layer 114 is to form bonding SiO 2Layer 123, last, the described Si substrate 111 surface employing chemical mechanical polishing methods after peeling off are carried out polishing to complete Si/NiSi on described insulator 2The backing material preparation.
See also Fig. 9, as shown in the figure, the present invention also provides Si/NiSi on a kind of insulator 2Backing material comprises at least: Si substrate 111; In conjunction with the insulating barrier 122 on described Si substrate 121 surfaces; Be incorporated into the NiSi of described surface of insulating layer 2Layer 113; And be incorporated into described NiSi 2The Si top layer 111 on layer 113 surface, described NiSi 2The thickness of layer is 3～10nm, and the thickness of described Si top layer is 5～200nm, in the present embodiment, and described NiSi 2The thickness of layer 113 is 6nm.The thickness of described Si top layer 111 is 100nm.
Embodiment 2
See also Fig. 1～Fig. 9, as shown in the figure, Si/NiSi on described insulator 2The preparation method's of backing material basic step such as embodiment 1, wherein, the thickness of described Ni layer 112 is selected 1nm, and described annealing temperature is for the first time selected 300 ℃, and described annealing is for the second time selected 200 ℃, and described annealing is for the third time selected 500 ℃.
See also Fig. 9, as shown in the figure, Si/NiSi on described insulator 2The basic structure of backing material such as embodiment 1, wherein, described NiSi 2The thickness of layer 113 is 3nm.The thickness of described Si top layer 111 is 5nm.
Embodiment 3
See also Fig. 1～Fig. 9, as shown in the figure, Si/NiSi on described insulator 2The preparation method's of backing material basic step such as embodiment 1, wherein, the thickness of described Ni layer 112 is selected 4nm.Described annealing temperature is for the first time selected 1000 ℃, and described annealing is for the second time selected 800 ℃, and described annealing is for the third time selected 1000 ℃.
See also Fig. 9, as shown in the figure, Si/NiSi on described insulator 2The basic structure of backing material such as embodiment 1, wherein, described NiSi 2The thickness of layer 113 is 10nm.The thickness of described Si top layer 111 is 200nm.
In sum, Si/NiSi on insulator of the present invention 2Backing material and preparation method thereof is by carrying out annealing reaction generation NiSi to Ni and Si substrate 2, and by smart-cut process, it is shifted, to insert layer of metal silicide NiSi between the BOX of traditional SOI substrate layer and top layer silicon 2, replacing the collector region heavy doping buried regions in conventional SOI bipolar transistor, reduce top layer silicon thickness, simplify the purpose such as technique thereby reach.Technique of the present invention is simple, is applicable to large-scale industrial production.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can under spirit of the present invention and category, modify or change above-described embodiment.Therefore, have in technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of completing under disclosed spirit and technological thought, must be contained by claim of the present invention.

Claims (15)

1. Si/NiSi on an insulator 2The preparation method of backing material is characterized in that, described preparation method comprises the following steps at least:
1) provide a Si substrate, form the Ni layer at a described Si substrate surface, then anneal for the first time so that a described Si substrate and the reaction of described Ni layer generate NiSi 2Layer is then removed unreacted described Ni layer;
2) at described NiSi 2Layer surface forms a SiO 2Then layer carries out the H Implantation and peels off the interface to form at a described Si substrate;
3) provide and have the 2nd SiO 2The 2nd Si substrate of layer, and described the 2nd SiO of bonding 2Layer and a described SiO 2The layer, then anneal for the second time so that a described Si substrate from the described interface peel of peeling off, at last to the stripper surface polishing to complete preparation.
2. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: described step 1) also comprise the step of a described Si substrate being carried out the wet chemistry ablution cleaning of standard.
3. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: described step 1), and the described Ni layer of deposit in vacuum environment, the Ni layer thickness of deposit is 1～4nm.
4. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: described annealing atmosphere for the first time is N 2Atmosphere, annealing temperature are 300～1000 ℃, and annealing time is 10～60 seconds.
5. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: selecting mol ratio is the H of 4: 1 2SO 4: H 2O 2Solution adopts wet etching to remove described unreacted Ni layer, and etch period is 1 minute.
6. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: the using plasma deposition technique is at the described SiO of surface deposition 2Layer, thickness is 100～600nm.
7. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: form a described SiO described step 2) 2Also comprise the step that it was annealed 1 hour after layer under 900 ℃.
8. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: also comprise a described SiO after the H Implantation described step 2) 2The step that layer carries out polishing.
9. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: adopt thermal oxidation process to form described the 2nd SiO at described the 2nd Si substrate surface 2Layer, thickness is 200～300nm.
10. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: described annealing atmosphere for the second time is N 2Atmosphere, annealing temperature are 200～800 ℃, and annealing time is 30 minutes.
11. Si/NiSi on insulator according to claim 1 2The preparation method of backing material is characterized in that: described step 3) also comprise and anneal for the third time to strengthen described the 2nd SiO 2Layer and a described SiO 2The step of the bonding of layer.
12. Si/NiSi on insulator according to claim 11 2The preparation method of backing material is characterized in that: described annealing atmosphere for the third time is N 2Atmosphere, annealing temperature are 500～1000 ℃, and annealing time is 30～240 minutes.
13. Si/NiSi on an insulator 2Backing material is characterized in that, comprises at least: the Si substrate; In conjunction with the insulating barrier of described Si substrate surface; Be incorporated into the NiSi of described surface of insulating layer 2Layer; And be incorporated into described NiSi 2The Si top layer on layer surface.
14. Si/NiSi on insulator according to claim 13 2Backing material is characterized in that: described NiSi 2The thickness of layer is 3～10nm.
15. Si/NiSi on insulator according to claim 13 2Backing material is characterized in that: the thickness of described Si top layer is 5～200nm.
CN201110384239XA 2011-11-28 2011-11-28 Si/NiSi 2 substrate material on insulator and preparation method thereof Pending CN103137547A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742200A (en) * 2019-01-11 2019-05-10 京东方科技集团股份有限公司 A kind of preparation method of display panel, display panel and display device

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EP0256397A1 (en) * 1986-07-31 1988-02-24 Hitachi, Ltd. Semiconductor device having a burried layer
EP0712155A2 (en) * 1994-11-09 1996-05-15 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
WO1997049131A1 (en) * 1996-06-20 1997-12-24 Btg International Limited Semiconductor device with buried conductive silicide layer
US20020173118A1 (en) * 2001-05-16 2002-11-21 Atmel Germany Gmbh Method for manufacturing buried areas
US20060128116A1 (en) * 2004-12-14 2006-06-15 Sung Ku Kwon Manufacturing method of silicon on insulator wafer
US20100176453A1 (en) * 2009-01-12 2010-07-15 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614558A (en) * 1964-09-23 1971-10-19 Philips Corp Semiconductor devices with more than one semiconductor circuit element in one body
CN86102691A (en) * 1985-04-19 1986-12-17 三洋电机株式会社 Semiconductor device and manufacture method thereof
EP0256397A1 (en) * 1986-07-31 1988-02-24 Hitachi, Ltd. Semiconductor device having a burried layer
EP0712155A2 (en) * 1994-11-09 1996-05-15 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
WO1997049131A1 (en) * 1996-06-20 1997-12-24 Btg International Limited Semiconductor device with buried conductive silicide layer
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742200A (en) * 2019-01-11 2019-05-10 京东方科技集团股份有限公司 A kind of preparation method of display panel, display panel and display device

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Application publication date: 20130605