The manufacture method of the parasitic PNP device of the self-isolation type in SiGe HBT technique
Technical field
The present invention relates to a kind of manufacture method of semiconductor device.
Background technology
In radio frequency applications, need more and more higher device feature frequency, although RFCMOS can realize upper frequency in the technology of advanced person, but be difficult to meet radio frequency requirement completely, realize the characteristic frequency of more than 40GHz as being difficult to, and the R&D costs of advanced technologies are also very high; Compound semiconductor can realize very high characteristic frequency device, but due to the shortcoming that material cost is high, size is little, adds that most compounds semiconductor is poisonous, limits its application.Silicon-germanium heterojunction bipolar transistor (SiGe HBT) is then the fine selection of hyperfrequency device, and first it utilizes that SiGe and Si's can be with difference, improves the Carrier Injection Efficiency of emitter region, the current amplification factor of increased device; Next utilizes the highly doped of SiGe base, reduces base resistance, improves characteristic frequency; SiGe technique is basic mutually compatible with silicon technology in addition, and therefore SiGe HBT has become the main force of hyperfrequency device.
Conventional SiGe HBT adopts highly doped collector region buried regions, to reduce collector region resistance, adopts the parasitic capacitance between deep trench isolation reduction collector region and substrate in addition, improves the frequency characteristic of HBT.This device technology mature and reliable, but major defect has: and 1, extension cost in collector region is high; 3, deep trench isolation complex process, and cost is higher;
Summary of the invention
Technical problem to be solved by this invention is to provide the manufacture method of the parasitic PNP device of self-isolation type in a kind of SiGe HBT technique, and it can effectively reduce collector leakage stream, substantially improves device performance.
In order to solve above technical problem, the invention provides the manufacture method of the parasitic PNP device of self-isolation type in a kind of SiGe HBT technique, comprising the following steps: step one, employing deep trap inject with substrate isolation to reduce collector region leakage current; Step 2, make N-type and the counterfeit buried regions of P type and doping collector region, bottom shallow-trench isolation high dose, low-yield inject boron ion or phosphonium ion impurity, through the diffusion of Overheating Treatment rear impurity, form the counterfeit buried regions of N and P type; Step 3, utilize P type substrate formed P type collector region, drawn by dark contact hole by the counterfeit buried regions of P type; Step 4, silicon-germanium heterojunction bipolar transistor SiGe HBT collector region form N-type base, are drawn by dark contact hole by the counterfeit buried regions of N-type; Step 5, utilize formation emitter region, silicon-germanium heterojunction bipolar transistor SiGe HBT epitaxial p type silicon-germanium heterojunction bipolar transistor SiGe base, and drawn by silicon-germanium heterojunction bipolar transistor SiGe HBT base.
Beneficial effect of the present invention is: deep trap self-isolation structure can effectively reduce collector leakage stream, substantially improves device performance.
In step one, deep trap implanted dopant is phosphorus, and implantation dosage is 1e
14~ 5e
15cm
-2, Implantation Energy is 500kev ~ 3000kev; P trap implanted dopant is boron, and implantation dosage is 1e
12~ 5e
13cm
-2, Implantation Energy is 200kev ~ 500kev.
N-type and the counterfeit buried regions of P type in step 2, PBL passes through 1e
14~ 1e
16cm
-2high dose, be less than the low-energy P type of 15keV and inject, the impurity of injection is boron or boron fluoride, as the connection of P type collector region; NBL passes through 1e
14~ 1e
16cm
-2high dose, be less than the low-energy N-type of 15keV and inject, the impurity of injection is phosphorus, as the connection of N-type base.
P type collector region utilizes P type substrate to be formed; N-type base is formed by silicon-germanium heterojunction bipolar transistor SiGe HBT collector region, and the impurity of injection is phosphorus or the arsenic of N-type, and implantation dosage is 5e
11~ 5e
13cm
-2, Implantation Energy is 50kev ~ 500kev.
Formed by silicon-germanium heterojunction bipolar transistor SiGe HBT epitaxial p type SiGe base, implanted dopant is boron or boron fluoride, and implantation dosage is 5e
11~ 5e
13cm
-2, Implantation Energy is 50kev ~ 500kev.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is self-isolation type vertical parasitic PNP device structural representation of the present invention;
Fig. 2 is parasitic PNP pipe output characteristic curve schematic diagram when working in forward amplification region;
Fig. 2 (a) is parasitic PNP pipe output characteristic curve schematic diagram when working in forward amplification region;
Fig. 2 (b) is when not adopting the parasitic PNP pipe of deep trap self-isolation structure to work in forward amplification region, the relation schematic diagram of collector current IC and base current IB and base emitter voltage VBE;
Fig. 3 (a) is the device sectional view after shallow slot etching, counterfeit buried regions (Pseudo Buried Layer) injection, shallow slot filling;
Fig. 3 (b) is the device sectional view after N-type deep trap, the injection of P trap;
Fig. 3 (c) is the device sectional view after SiGe HBT collector region is injected;
Fig. 3 (d) be germanium and silicon epitaxial after device sectional view;
Fig. 3 (e) is the device sectional view after contact hole is drawn.
Description of reference numerals in accompanying drawing:
1-P type substrate, 2-shallow-trench isolation, the counterfeit buried regions of 3--P type, the counterfeit buried regions of 4-N-type, 5-N-type deep trap injects, and 6-P trap injects, and 7-SiGe HBT collector region is injected, 8-SiGe extension, 9-dark contact hole, 10-contact hole, 11-metal connecting line,
Embodiment
The present invention proposes the device of the self-isolation type vertical parasitic PNP in a kind of SiGe HBT technique, can be used as the output device in high speed, high-gain HBT circuit, adopt deep trap to inject with substrate isolation to reduce collector region leakage current, can be embodied as circuit without the need to extra process conditions provides how a kind of device is selected.It makes the counterfeit buried regions (Pseudo Buried Layer) related in SiGe HBT technique, the transmitting collection polysilicon of SiGe extension and HBT.
Three of PNP triode is extremely base stage (Base) respectively, emitter (Emitter) and collector electrode (Collector).As shown in figure, collector region utilizes P type substrate to be formed to parasitic PNP device structure of the present invention; N-type base is formed by SiGe HBT collector region, and emitter region is formed by SiGe HBT epitaxial p type SiGe base, and collector region and base are drawn by dark contact hole by counterfeit buried regions, and emitter is drawn by SiGe HBT base.
Concrete technical scheme of the present invention:
1. adopt deep trap to inject with substrate isolation to reduce collector region leakage current;
2. do not have high-octane N/P trap to inject and collector region epitaxial loayer in device, the substitute is and make N-type and the counterfeit buried regions of P type (Pseudo Buried Layer) and collector region of adulterating;
3. high dose (1e bottom shallow-trench isolation
14~ 1e
16cm
-2), low-yield (being less than 15keV) inject boron ion or phosphonium ion impurity, through the diffusion of Overheating Treatment rear impurity, formed the counterfeit buried regions of N and P type (NBL and PBL);
4.P type collector region utilizes P type substrate to be formed, and is drawn by dark contact hole by the counterfeit buried regions of P type;
5.N type base is formed by SiGe HBT collector region, is drawn by dark contact hole by the counterfeit buried regions of N-type;
6. what the formation of emitter region utilized is SiGe HBT epitaxial p type SiGe base, and is drawn by it.
This parasitic PNP pipe output characteristic curve is good, and as Fig. 2 (a), Early voltage reaches higher level.
Output characteristic curve (VC is collector voltage, and IC is collector current) when the parasitic PNP pipe of Fig. 2 (a) works in forward amplification region
When Fig. 2 (b) does not adopt the parasitic PNP pipe of deep trap self-isolation structure to work in forward amplification region, the relation (above current/voltage value all takes absolute value) of collector current IC and base current IB and base emitter voltage VBE
Because this PNP pipe collector region is formed by substrate, do not adopt deep trap self-isolation collector leakage stream comparatively large, as shown in Fig. 2 (b), and the deep trap self-isolation structure that the present invention proposes can effectively reduce collector leakage stream, substantially improves device performance.
The main technological steps of vertical parasitic PNP of the present invention:
Processing step 1: select lightly doped P type substrate silicon chip 1, makes isolation technology by shallow trench etching, after shallow trench 2 etches, carries out high dose (1e respectively
14~ 1e
16cm
-2), the N-type of low-yield (being less than 15keV) and p type impurity inject in order to form counterfeit buried regions (Pseudo Buried Layer) (NBL and PBL) (4,3), it distinguishes base and the collector region exit of PNP pipe in corresponding the present invention, then with silica-filled shallow slot (as Suo Shi Fig. 3 (a)).
Processing step 2: carry out N-type deep trap 5 and to inject and P trap 6 injects, (as Suo Shi Fig. 3 (b)).
Processing step 3: the base of collector region injection as this PNP pipe carrying out SiGe HBT in active area, (as Suo Shi Fig. 3 (c)).
Processing step 4: side carries out SiGe extension, (as Suo Shi Fig. 3 (d)) on the active area.
Processing step 5: draw the counterfeit buried regions of N-type 4 and the counterfeit buried regions 3 of P type respectively as base stage and collector electrode through STI by dark contact hole, emitter is drawn by SiGe HBT base 8, and device is shaping (as Suo Shi Fig. 3 (e)) finally.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.