CN103137189B

CN103137189B - Distributed self-timing circuit

Info

Publication number: CN103137189B
Application number: CN201210563552.4A
Authority: CN
Inventors: 拜福君; 付妮
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2012-12-21
Filing date: 2012-12-21
Publication date: 2016-11-23
Anticipated expiration: 2032-12-21
Also published as: CN103137189A

Abstract

The present invention relates to the distributed self-timing circuit of application in a kind of SRAM.Comprising at least 1 redundancy including redundant columns, redundant columns has been disposed adjacent drop-down discharge circuit row；Drop-down discharge circuit in drop-down discharge circuit row is identical with the redundancy number in redundant columns and one_to_one corresponding is arranged；Each drop-down discharge circuit is connected on the duplication bit line segment of corresponding redundancy.The invention provides the distributed self-timing circuit that a kind of stability is high, save arrangement space.

Description

Distributed self-timing circuit

Technical field

The present invention relates to a kind of self-timing circuit, particularly relate to the distribution of application in a kind of SRAM Formula self-timing circuit.

Background technology

Self-timing circuit technology based on duplication bit line is commonly used in SRAM designs.Generally Drop-down discharge circuit, for simulating the electric discharge to bit line of the normal memory element.Voltage detector is used for detecting Replicate on bit line all voltage, produce feedback signal when it reaches the magnitude of voltage set, indicate control circuit battle array Row neutrality line voltage difference meets requirement, and sense amplifier can start working (such as Fig. 1).Although whole timing Length mainly by replicating the strong and weak decision of the load of bit line and drop-down discharge circuit, but drop-down electric discharge The length of timing is also had an impact by the position of circuit.Due to the restriction of chip layout, general drop-down discharge circuit Being placed on the two ends of redundant columns, no matter be placed on which end, self-timing circuit simulation is all from drop-down electric discharge The discharge process of the memory element that circuit is nearest.The time delay that precisely self-timing circuit produces with from oneself Near memory element is normally read and write required time delay and is mated most, and what the memory element the most remote with distance needed Time delay is not more mated.This do not mate the loss even capability error that may result in chip performance.

Summary of the invention

In order to solve the technical problem in the presence of background technology, the present invention proposes a kind of distributed self-timing Circuit.The discharge process of each line storage unit can be simulated exactly, it is ensured that what self-timing circuit produced prolongs Time mate with the time delay needed for read-write all the time, thus improve the stability of chip.

The technical solution of the present invention is:

A kind of distributed self-timing circuit, including redundant columns, it is characterized in that redundant columns comprises at least 1 Individual redundancy, redundant columns has been disposed adjacent drop-down discharge circuit row；Drop-down electric discharge electricity in drop-down discharge circuit row Road is identical with the redundancy number in redundant columns and one_to_one corresponding is arranged；Each drop-down discharge circuit is connected to and it On the duplication bit line segment of corresponding redundancy.Duplication bit line segment in each redundancy is sequentially connected with composition and replicates position Line DBL.Distributed self-timing circuit also includes replicating column selection and precharging circuit, voltage detector.Redundant columns warp Replicate bit line DBL to be connected to replicate column selection and precharging circuit.

The invention have the advantage that

1. improve stability.Owing to each drop-down discharge circuit and a redundancy are disposed adjacent and superfluous at this Remaining place is connected to replicate bit line DBL.Therefore can simulate the discharge process of each line storage unit exactly, protect The time delay that card self-timing circuit produces is mated with the time delay needed for read-write all the time, thus improves the stability of chip.

2. save arrangement space.Owing to drop-down discharge circuit uses the electricity of the discharge path being similar to memory element Line structure, it is possible to be that each line storage unit mates a drop-down discharge circuit easily in domain, And do not result in bigger chip area increase.Additionally, due to the drop-down electric discharge that need not necessarily lie in redundant columns two ends Circuit, can save chip area.

Accompanying drawing explanation

Fig. 1 is the self-timing circuit figure of the former SRAM of the present invention.

Fig. 2 is the self-timing circuit figure of the present invention.

Fig. 3 is a drop-down discharge circuit figure of the present invention.

Fig. 4 is duplication column selection and the precharging circuit of the present invention, the circuit diagram of voltage detector.

Detailed description of the invention

Seeing Fig. 2, the present invention increases a drop-down electric discharge electricity near the redundant columns of normal memory cell array Lu Lie.Drop-down discharge circuit row in each drop-down discharge circuit can be independent work completion timing.Often Individual drop-down discharge circuit and aliging with the every a line being adjacent in array.Each drop-down electric discharge electricity after alignment Road is corresponding with a line of memory cell array, and memory element has how many row to need exist for how many drop-down electric discharge electricity Road: the most drop-down electric discharge open by by this corresponding row wordline (WL_0, WL_1 ..., WL_N) solely Stand and control rather than by replicating wordline DWL co-controlling；The most drop-down discharge circuit and duplication bit line The connection of DBL also is located at the position of this row rather than the two ends of redundant columns.No matter which is written and read, Can use the drop-down discharge circuit corresponding with this row to simulate the discharge process of one's own profession normal memory cell, Thus ensure that the time delay that self-timing circuit produces is coupling all the time.It addition, replicate wordline DWL or necessity , only be used for control replicate bit line DBL preliminary filling: the most drop-down discharge circuit row in which start work Make, be required for the preliminary filling stopping replicating bit line DBL.Replicate column selection and precharging circuit be connected to replicate bit line DBL, Being controlled to be pre-charged DBL by replicating wordline DWL, DBL is connected to voltage detector through replicating column selection.

Seeing Fig. 3, a drop-down discharge circuit employing of the present invention is similar to the discharge path of memory element Circuit structure.When DWL is ' 1 ', pull-down circuit is effective.Owing to the structure of drop-down discharge circuit is single with storage Unit is similar, it is possible to be that each line storage unit mates a drop-down discharge circuit easily in domain, And do not result in bigger chip area increase.Drop-down discharge circuit uses the electric discharge being similar to memory element to lead to The domain structure on road.Each drop-down discharge circuit is identical with the domain height of memory element.General storage list The edge of unit is redundancy unit, and we are further added by a contour drop-down discharge circuit at the edge of redundancy unit, Due to the similarity in structure, it is not necessary to extra cabling just can realize following two purpose on domain: one The drop-down discharge circuit of aspect can share same wordline, on the other hand, drop-down discharge circuit with memory element Can be connected to the most nearby replicate on bit line.

See duplication column selection and preliminary filling, voltage detector circuit diagram that Fig. 4, Fig. 4 are the present invention.

Transistor PPRE is precharging circuit, DWL signal control, and when DWL is ' 1 ', stops DBL Preliminary filling；When DWL is ' 0 ', transistor PPRE turns on, and DBL is charged to supply voltage VDD in advance.Brilliant It is column selection circuit that body pipe NPS and PPS constitutes a complementary transmission gate, and they are in normally open here. DBL is connected with RDBL through transmission gate, and RDBL is as the input of voltage detector INV.INV is output as Feedback signal ST.

Voltage detector uses the phase inverter of a standard, and circuit structure is simple, saves area.Standard reversed phase The reversal point of device is probably at 1/2 supply voltage VDD.Work as input signal, i.e. replicate bit line, voltage be less than During 1/2 supply voltage, the feedback signal of phase inverter output is ' 1 ', is otherwise ' 0 ', thus completes to replicate position The detection of voltage and identification on line.When timing starts, replicating bit line and be charged to VDD in advance, output feedback signal is ' 0 ', after duplication wordline DWL is opened, replicate bit line and start to start electric discharge via drop-down discharge circuit, when multiple After bit line processed is pulled down to reversal point 1/2*VDD, output feedback signal is ' 1 '.

Claims

1. a distributed self-timing circuit, including redundant columns, it is characterised in that: described redundancy Row comprise at least 1 redundancy, and described redundant columns has been disposed adjacent drop-down discharge circuit row；Described Drop-down discharge circuit in drop-down discharge circuit row is identical with the redundancy number in redundant columns and one One is correspondingly arranged；Described drop-down discharge circuit is independently to be controlled by the wordline being expert at；Under each Discharge circuit is drawn to be connected on the duplication bit line segment of corresponding redundancy；Described drop-down electric discharge Circuit is positioned at the position of this row with the connection replicating bit line segment, is not the two ends of redundant columns.

Distributed self-timing circuit the most according to claim 1, it is characterised in that: described Distributed self-timing circuit also includes replicating column selection and precharging circuit, voltage detector.

Distributed self-timing circuit the most according to claim 2, it is characterised in that: described Duplication bit line segment in redundancy is sequentially connected with composition and replicates bit line DBL.

Distributed self-timing circuit the most according to claim 3, it is characterised in that: described Redundant columns is replicated bit line DBL and is connected to replicate column selection and precharging circuit.