CN103137057B - Image display system and gate driver circuit - Google Patents
Image display system and gate driver circuit Download PDFInfo
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- CN103137057B CN103137057B CN201110409167.XA CN201110409167A CN103137057B CN 103137057 B CN103137057 B CN 103137057B CN 201110409167 A CN201110409167 A CN 201110409167A CN 103137057 B CN103137057 B CN 103137057B
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Abstract
The present invention proposes a kind of image display system and gate driver circuit。This gate driver circuit includes forward input circuit, reverse input circuit and control circuit。Forward input circuit receives forward input signal and forward reset signal, and the voltage potential of the voltage potential and forward reset signal inputting signal according to forward when forward scan controls the voltage potential of end points。Reverse input circuit reception reversely input signal and reversely reset signal, and when reverse scan, the voltage potential of end points is controlled according to the reversely voltage potential of input signal and the voltage potential of reverse reset signal。Control circuit is coupled to control end points, and receives the first clock signal, in order to export the first clock signal or certain voltage signal as gate drive signal according to the voltage potential controlling end points in an exit point selectivity of shift register。
Description
Technical field
The present invention is about a kind of shift register module, especially in regard to the bidirectional shift register module of a kind of scanning sequency that can be different operation。
Background technology
Shift register (shiftregister) is widely used in data drive circuit and gate driver circuit, receives the sequential of data signal in order to control each data wire respectively, and is that each gate line produces scanning signal。In data drive circuit, shift register chooses signal extremely each data wire in order to export one so that image data can sequentially be written into each data wire。On the other hand, in gate driver circuit, shift register is in order to produce scan signal to each gate line, and the signal of video signal in order to be sequentially supplied to each data wire writes the pixel of a picture element matrix。
In recent years, the integrated gate drivers of non-crystalline silicon (AmorphousSiliconGatedriver is called for short ASG) technology is developed。ASG technology is directly to be integrated on display floater by gate driver circuit in the processing procedure of non-crystalline silicon, and to replace the use of gate drivers chip, this technology is referred to as the gate drivers (GatedriverOnPanel is called for short GOP) on panel。Therefore, apply ASG technology, the element of liquid crystal display can be reduced, and then manufacturing cost can be reduced and shorten the manufacturing cycle。
The function of simple scanning is all only had at present with the product of GOP。But, single scanning order cannot meet the demand of image display system product now。Accordingly, it would be desirable to a kind of brand-new shift register framework, it different scanning order can produce output signal。
Summary of the invention
According to one embodiment of the invention, a kind of image display system, including: a gate driver circuit, in order to produce multiple gate drive signal to drive multiple pixels of the picture element matrix being positioned on a substrate。Gate driver circuit includes a two-way shift register module, and bidirectional shift register module includes the shift register of multi-stage serial connection。Wherein when forward scan, shift register sequentially exports gate drive signal with one first order, and when reverse scan, shift register sequentially exports gate drive signal with one second order。At least one of shift register includes forward input circuit, reverse input circuit and control circuit。Forward input circuit receives forward input signal and forward reset signal, and the voltage potential of the voltage potential and forward reset signal inputting signal according to forward when forward scan controls the voltage potential of end points。Reverse input circuit reception reversely input signal and reversely reset signal, and when reverse scan, the voltage potential of end points is controlled according to the reversely voltage potential of input signal and the voltage potential of reverse reset signal。Control circuit is coupled to control end points, and receives the first clock signal, in order to export the first clock signal or certain voltage signal as gate drive signal according to the voltage potential controlling end points in an exit point selectivity of shift register。
According to another embodiment of the present invention, a kind of gate driver circuit, is made on a substrate, in order to produce multiple gate drive signal to drive multiple pixels of the picture element matrix being positioned on substrate, including a two-way shift register module, it includes the shift register of multi-stage serial connection。Wherein at least one of shift register includes forward input circuit, reverse input circuit and control circuit。Forward input circuit receives forward input signal and forward reset signal, and the voltage potential of the voltage potential and forward reset signal inputting signal according to forward when forward scan controls the voltage potential of end points。Reverse input circuit reception reversely input signal and reversely reset signal, and when reverse scan, the voltage potential of end points is controlled according to the reversely voltage potential of input signal and the voltage potential of reverse reset signal。Control circuit is coupled to control end points, and receives the first clock signal, in order to export the first clock signal or certain voltage signal as gate drive signal according to the voltage potential controlling end points in an exit point selectivity of shift register。
Accompanying drawing explanation
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 shows conventional liquid crystal schematic diagram。
Fig. 2 shows the bidirectional shift register module diagram according to one embodiment of the invention。
Fig. 3 shows the shift register block chart according to one embodiment of the invention。
Fig. 4 shows the shift-register circuit figure according to one embodiment of the invention。
Fig. 5 shows shift-register circuit figure described according to another embodiment of the present invention。
Fig. 6 shows the signal waveforms when forward scan of the shift register as shown in Figure 5。
Fig. 7 shows shift-register circuit figure described according to another embodiment of the present invention。
Fig. 8 shows the signal waveforms when reverse scan of the shift register as shown in Figure 7。
Main element symbol description:
100～electronic installation；
101～display pannel；
102～input block；
110-1,110-2～gate driver circuit；
120～data drive circuit；
130～picture element matrix；
140～control chip；
200～bidirectional shift register module；
300, SR [1], SR [2], SR [3], SR [X-2], SR [X-1], SR [X]～shift register；
301,501,701～forward input circuit；
302,502,702～reverse input circuit；
303,503,703～control circuit；
411,412,413,421,422,423,431,432,433 and 434～switch；
CK, IN_F, IN_R, N, OUT, P, RSET_F, RSET_R, VG～end points；
CK1, CK2, CK3, CK4, CK5, CK6, N (1), N (2), N (3), N (4), N (5), N (6), N (k-3), N (k-1), N (k), N (k+1), N (k+3), N (X-5), N (X-3), N (X-2), N (X-1), N (X), OUT (1), OUT (2), OUT (3), OUT (k), OUT (X-2), OUT (X-1), OUT (X), P (3), P (X-2), VGL～signal；
M1, M2, M3, M4, M5, M6, M7, M8, M9, M10～transistor；
STV1, STV2～initial pulse wave。
Detailed description of the invention
Fig. 1 shows the numerous embodiments of the image display system according to one embodiment of the invention。As it is shown in figure 1, image display system can include a display pannel 101, wherein display pannel 101 includes gate driver circuit 110-1 and 110-2, data drive circuit 120, picture element matrix 130 and a control chip 140。Gate driver circuit 110-1 and 110-2 is in order to produce multiple gate drive signal to drive multiple pixels of picture element matrix 130。Data drive circuit 120 is in order to produce multiple data drive signal to provide data to multiple pixels of picture element matrix 130。Control chip 140 is in order to produce multiple control signal, including clock signal and initial pulse wave etc.。According to one embodiment of the invention, picture element matrix 130 is positioned on a substrate, gate driver circuit 110-1 and 110-2 is with the integrated gate drivers (AmorphousSiliconGatedriver of non-crystalline silicon, it being called for short ASG) fabrication techniques is on this substrate, to form the gate drivers (GatedriverOnPanel is called for short GOP) on panel。
Additionally, the image display system according to the present invention potentially includes in an electronic installation 100。Electronic installation 100 can include aforementioned display device panel 101 and an input block 102。Input block 102 is used for receiving signal of video signal, to control display pannel 101 show image。According to embodiments of the invention, electronic installation 100 has numerous embodiments, including: a mobile phone, a digital camera, a personal digital assistant, a removable computer, a desktop computer, a television set, a vapour vehicle display, a portable disc player or any device including image display function。
According to one embodiment of the invention, gate driver circuit 110-1 and 110-2 can include a two-way shift register module (paragraphs below will be described in detail) respectively, its can be different scanning sequency (such as, forward scan order and reverse scan order) sequentially output gate drive signal is to each gate line, in order to be sequentially supplied in the pixel of signal of video signal writing pixel matrix 130 of each data wire。It should be noted that no matter be forward scan or reverse scan, gate driver circuit 110-1 and 110-2 proposed by the invention all can operate simultaneously, in order to bilateral driving picture element matrix 130, to promote driving force。But, the present invention is not limited to the design of bilateral driving。Such as, in other embodiments of the invention, gate driver circuit also can only be implemented on picture element matrix 130, for instance, the picture element matrix 130 of Fig. 1 only comprises monolateral gate driver circuit 110-1 or 110-2, in order to monolateral driving picture element matrix 130。
Fig. 2 shows the bidirectional shift register module diagram according to one embodiment of the invention, and wherein bidirectional shift register module is configured in gate driver circuit 110-1 and 110-2 as shown in Figure 1。Bidirectional shift register module 200 includes the shift register 300 of X level concatenation, and shift register SR [1] as depicted, SR [2], SR [3] ... SR [X-2], SR [X-1] and SR [X], wherein X is a positive integer。Each shift register includes several clock input point CK, voltage signal inputs point VG, forward signal input endpoint IN_F, non-inverting signal input thereof point IN_R, exit point OUT, signal transmission end points N, forward reset signal input endpoint RSET_F and reverse reset signal input endpoint RSET_R respectively。Wherein the signal transmission end points N of shift registers at different levels is by gate drive signal identical with exit point OUT for output, in order to the pulse of gate drive signal to be sequentially transmitted between shift register at different levels。
Operationally, bidirectional shift register module 200 is when forward scan, each shift register 300 sequentially exports gate drive signal with one first order, such as, shift register SR [1] to SR [X] will sequentially export gate drive signal OUT (1), OUT (2), OUT (3) ... OUT (X-2), OUT (X-1) and OUT (X)。On the other hand, when reverse scan, each shift register 300 sequentially exports gate drive signal with one second contrary order, such as, shift register SR [X] to SR [1] sequentially exports gate drive signal OUT (X), OUT (X-1), OUT (X-2) ... OUT (3), OUT (2) and OUT (1)。
Bidirectional shift register module 200 receives multiple control signal from control chip 140, including clock signal CK1, CK2, CK3, CK4, CK5 and CK6, initial pulse wave STV1, STV2 and determining voltage signal VGL。Generally speaking, it is overlapping that clock signal CK1, CK2, CK3, CK4, CK5 and CK6 have half pulse period between two, such as, oscillogram with reference to Fig. 6, front half pulse of clock signal CK2 and rear half pulse overlap of clock signal CK1, and front half pulse overlap of rear half pulse of clock signal CK2 and clock signal CK3, and generally clock signal CK1, CK3 and CK5 provide the shift register to strange (idol) several levels, and clock signal CK2, CK4 and CK6 provide the shift register to even (very) several levels。
Initial pulse wave STV1 and STV2 is in order to initial bidirectional shift register module 200, as shown in the figure, first order shift register SR [1] of bidirectional shift register module 200 receives initial pulse wave STV1 in forward signal input endpoint IN_F and inputs signal as forward, and afterbody shift register SR [X] receives initial pulse wave STV2 as reversely inputting signal in non-inverting signal input thereof point IN_R。In addition, shift register SR [2]-SR [X-1] receives previous stage shift register respectively at forward signal input endpoint IN_F and inputs signal in the gate drive signal exported as forward, and receives gate drive signal that rear stage shift register exports as reversely inputting signal in non-inverting signal input thereof point IN_R。
As for forward reset signal and reverse reset signal, in presently preferred embodiments of the present invention, the shift register gate drive signal that generally two-stage or rear three grades of shift registers export after forward reset signal input endpoint RSET_F receives is as forward reset signal, and the gate drive signal that two-stage or first three grade of shift register export before reverse reset signal input endpoint RSET_R receives is as reverse reset signal。But, the present invention is not limited to above-mentioned implementation。Such as, shift register also can receive after one or the gate drive signal that exports of multi-stage shift register as forward reset signal, and receive gate drive signal that previous or multi-stage shift register exports as reverse reset signal。Furthermore it is noted that in bidirectional shift register module one or more shift register end to end forward and reversely reset signal coupling method also can do special design, to avoid producing timing error。Relevant method for designing is referred to other document of the art, does not repeat in this。
Fig. 3 shows the shift register block chart according to one embodiment of the invention。Shift register 300 includes forward input circuit 301, reverse input circuit 302 and control circuit 303。Forward input circuit 301 is in order to receive forward input signal and a forward reset signal, and a voltage potential of the voltage potential and forward reset signal inputting signal according to forward when forward scan controls a voltage potential of end points。Reverse input circuit 302 in order to receive reversely input signal and a reverse reset signal, and when reverse scan the voltage potential of a voltage potential control control end points according to the voltage potential with reverse reset signal that reversely input signal。Control circuit 303 is coupled to control end points, and receives one first clock signal, in order to export the first clock signal or certain voltage signal as gate drive signal according to the voltage potential controlling end points in an exit point selectivity of shift register。
According to one embodiment of the invention, forward input circuit 301 is mutually symmetrical with in structure with reverse input circuit 302, wherein when forward scan, forward input circuit 301 controls the circuit of the voltage of end points for major control, and reversely input circuit 302 can become the circuit of auxiliary, in order to assist the operation of forward input circuit 301。Similarly, when reverse scan, reverse input circuit 302 controls the circuit of the voltage of end points for major control, and forward input circuit 301 can become the circuit of auxiliary, in order to assist the operation of reverse input circuit 302。
Fig. 4 shows the shift-register circuit figure according to one embodiment of the invention。In this embodiment, shift register 300 represents the shift register of kth level in bidirectional shift register module。Forward input circuit 301 includes switch 411,412 and 413。Switch 411 and 412 is coupled between control end points P and forward signal input endpoint IN_F, and switchs 413 and be coupled between control end points P and voltage signal inputs point VG。In this embodiment, the signal N (k-1) that forward signal input endpoint IN_F reception (k-1) level shift register of the shift register of kth level exports inputs signal as forward, the signal N (k+3) that forward reset signal input endpoint RSET_F reception (k+3) level shift register exports is as forward reset signal, and forward input circuit 301 more receives clock signal CK1 as another control signal。
As above-mentioned, the signal transmission end points N of shift registers at different levels is by gate drive signal identical with exit point OUT for output, in order to the pulse of gate drive signal to be sequentially transmitted between shift register at different levels。Therefore the signal N (k-1) that (k-1) level shift register exports is gate drive signal OUT (k-1), similarly, the signal N (k+3) that (k+3) level shift register exports is gate drive signal OUT (k+3)。Additionally, voltage signal inputs point VG receives determining voltage signal VGL from control chip 130, in an embodiment of the present invention, determining voltage signal VGL is a low voltage signal。
According to one embodiment of the invention, switch 411 switches its conducting state according to the voltage potential of signal N (k-1), switch 412 switches its conducting state according to the voltage potential of clock signal CK1, and switchs 413 and switch its conducting state according to the voltage potential of signal N (k+3)。When switching 411 and/or 412 conducting, forward input circuit 301 charges according to the voltage potential of signal N (k-1) and controls the voltage of end points P, in addition, when clock signal CK1 has high voltage potential, switch 412 more can help the voltage controlling end points P to maintain a voltage potential of determining voltage signal VGL。On the other hand, when switching 413 conducting, control end points P and will be coupled to determining voltage signal VGL in order to discharge。
According to one embodiment of the invention, reverse input circuit 302 is structurally mutually symmetrical with forward input circuit 301, including switch 421,422 and 423。Switch 421 and 422 couples and is connected between control end points P and non-inverting signal input thereof point IN_R, and switchs 423 and be coupled between control end points P and voltage signal inputs point VG。In this embodiment, the signal N (k+1) that non-inverting signal input thereof point IN_R reception (k+1) level shift register of the shift register of kth level exports is as reversely inputting signal, the signal N (k-3) that reverse reset signal input endpoint RSET_F reception (k-3) level shift register exports is as reverse reset signal, and reverse input circuit 302 more receives clock signal CK5 as another control signal。
Switch 421 switches its conducting state according to the voltage potential of signal N (k+1), and switch 422 switches its conducting state according to the voltage potential of clock signal CK5, and switchs 423 and switch its conducting state according to the voltage potential of signal N (k-3)。When switching 421 and/or 422 conducting, reverse input circuit 302 charges according to the voltage potential of signal N (k+1) and controls the voltage of end points P。Additionally, when clock signal CK5 has high voltage potential, switch 422 more can help the voltage controlling end points P to maintain a voltage potential of determining voltage signal VGL。On the other hand, when switching 423 conducting, control end points P and will be coupled to determining voltage signal VGL in order to discharge。
Control circuit 303 comprises switch 431,432,433 and 434, is respectively coupled to the exit point OUT exporting gate drive signal OUT (k) and transmits end points N with the signal in order to export signal N (k)。Switch 431 and 432 switches its conducting state according to the voltage potential controlling end points P, when switching 431 and 432 conducting, and the control circuit 303 voltage according to voltage potential charging exit point OUT and the signal transmission end points N of clock signal CK3。Switch 433 and 434 bases are different from other clock signal of clock signal CK3 (such as, CK1 or CK5) voltage potential switch its conducting state, when switching 433 and 434 conducting, exit point OUT will be coupled to determining voltage signal VGL in order to discharge with signal transmission end points N。Binding signal oscillogram, paragraphs below will do more detailed introduction for shift register in the operation of forward scan and anti-phase scanning respectively。
Fig. 5 shows shift-register circuit figure described according to another embodiment of the present invention。Fig. 6 shows the signal waveforms when forward scan of the shift register as shown in Figure 5。In this embodiment, shift register SR [3] represents the shift register of 3rd level in bidirectional shift register module, it includes forward input circuit 501, reverse input circuit 502 and control circuit 503, and on-off circuit therein is all implemented with transistor, such as, nmos pass transistor M1-M10。When forward scan, first transistor M3 turns on because of the pulse of clock signal CK1 pull-up, controls end points P and is coupled to forward input signal N (2)。Now being still maintained at low voltage potential owing to forward inputs signal N (2), the voltage therefore controlling end points P is maintained at low voltage potential。After the pulse of forward input signal N (2) is arrived at, transistor M1 is switched on, and starts the voltage controlling end points P is charged to the first high voltage potential (in Fig. 6 the waveform of signal P (3))。
Having high voltage potential owing to controlling end points P, transistor M7 and M8 can be switched on so that the pulse of clock signal CK3 can be transferred to exit point OUT and signal transmission end points N。Therefore, in the period that transistor M7 and M8 is switched on, gate drive signal OUT (3) and signal N (3) will have identical phase place with clock signal CK3。In addition, the pulse in clock signal CK3 with high voltage potential is interval, the voltage of control end points P can more further pass through parasitic capacitance (or the electric capacity additionally coupled) and be filled by clock signal CK3 high to the second high voltage potential, in order to improve the grid voltage of transistor M7 and M8 further。Higher grid voltage helps speed up the charge/discharge speed of exit point OUT and signal transmission end points N。
After the end-of-pulsing of clock signal CK3, owing to the drain voltage of transistor M7 and M8 returns to low voltage potential, the voltage controlling end points P starts to be discharged back the first high voltage potential by the second high voltage potential。Then, after the pulse of forward reset signal N (6) is arrived at, transistor M5 is switched on, and is coupled to the determining voltage signal VGL with low voltage potential by controlling end points P, further the tension discharge controlling end points P is returned low voltage potential。
As above-mentioned, when forward scan, forward input circuit is the circuit that major control controls the voltage of end points, and reversely input circuit can become the circuit of auxiliary, in order to assist the operation of forward input circuit。Transistor M2 and the M4 of reverse input circuit can be turned on by pulse respectively that be referenced to Fig. 5, signal N (4) and clock signal CK5, in order to the charge and discharge of assist control end points P。
Fig. 7 shows shift-register circuit figure described according to another embodiment of the present invention。Fig. 8 shows the signal waveforms when reverse scan of the shift register as shown in Figure 7。In this embodiment, shift register SR [X-2] represents the shift register of (X-2) level in bidirectional shift register module, it includes forward input circuit 701, reverse input circuit 702 and control circuit 703, and on-off circuit therein is all implemented with transistor, such as, nmos pass transistor M1-M10。When reverse scan, by the running of the initial bidirectional shift register module of initial pulse wave STV2, and the pulse sequence reverse (as shown in Figure 8) of clock signal CK1-CK6。First transistor M4 turns on because of the pulse of clock signal CK6 pull-up, controls end points P and is coupled to forward input signal N (X-1)。Now being still maintained at low voltage potential owing to reversely inputting signal N (X-1), the voltage therefore controlling end points P is maintained at low voltage potential。After the pulse of reversely input signal N (X-1) is arrived at, transistor M2 is switched on, and starts the voltage controlling end points P is charged to the first high voltage potential (in Fig. 8 the waveform of signal P (X-2))。
Having high voltage potential owing to controlling end points P, transistor M7 and M8 can be switched on so that the pulse of clock signal CK4 can be transferred to exit point OUT and signal transmission end points N。Therefore, in the period that transistor M7 and M8 is switched on, gate drive signal OUT (X-2) and signal N (X-2) will have identical phase place with clock signal CK4。In addition, the pulse in clock signal CK4 with high voltage potential is interval, the voltage of control end points P can more further pass through parasitic capacitance (or the electric capacity additionally coupled) and be filled by clock signal CK4 high to the second high voltage potential, in order to improve the grid voltage of transistor M7 and M8 further。Higher grid voltage helps speed up the charge/discharge speed of exit point OUT and signal transmission end points N。
After the end-of-pulsing of clock signal CK4, owing to the drain voltage of transistor M7 and M8 returns to low voltage potential, the voltage controlling end points P starts to be discharged back the first high voltage potential by the second high voltage potential。Then, after the pulse of forward reset signal N (X-5) is arrived at, transistor M6 is switched on, and is coupled to the determining voltage signal VGL with low voltage potential by controlling end points P, further the tension discharge controlling end points P is returned low voltage potential。
As above-mentioned, when reverse scan, reverse input circuit is the circuit that major control controls the voltage of end points, and forward input circuit can become the circuit of auxiliary, in order to assist the operation of reverse input circuit。Transistor M1 and the M3 of reverse input circuit can be turned on by pulse respectively that be referenced to Fig. 7, signal N (X-3) and clock signal CK2, in order to the charge and discharge of assist control end points P。
According to embodiment of the present invention, by using forward input circuit mutually symmetrical with in structure and reverse input circuit and proper arrangement control signal (such as, clock signal CK1-CK6) sequential, shift registers at different levels can respectively according to different Sequential output gate drive signals, therefore gate driver circuit 110-1 and 110-2 can be sequentially driven each gate line with different scanning sequencies (such as, forward scan order and reverse scan order) respectively。
Although the present invention discloses as above with preferred embodiment; so it is not limited to the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little amendment and perfect, therefore protection scope of the present invention is when with being as the criterion that claims define。
Claims (14)
1. an image display system, including:
One gate driver circuit, in order to produce multiple gate drive signal to drive multiple pixels of the picture element matrix being positioned on a substrate, this gate driver circuit includes a two-way shift register module, this bidirectional shift register module includes the shift register of multi-stage serial connection, wherein when forward scan, described shift register sequentially exports this gate drive signal with one first order, and when reverse scan, described shift register sequentially exports this gate drive signal with one second order, and at least one of wherein said shift register includes:
One forward input circuit, receive forward input signal and a forward reset signal, and a voltage potential of the voltage potential and this forward reset signal inputting signal according to this forward when forward scan controls a voltage potential of end points, wherein this forward input circuit has one first switch, this first switch is a first transistor, one first end of this first transistor couples this control end points, one second end of this first transistor and a grid are all coupled to receive a forward signal input endpoint of this forward input signal, and this voltage potential that this first switch inputs signal according to this forward switches its conducting state；
One reverse input circuit, receive one and reversely input signal and a reverse reset signal, and a voltage potential of the voltage potential and this reverse reset signal reversely inputting signal according to this when reverse scan controls this voltage potential of this control end points, wherein this reverse input circuit has one the 4th switch, 4th switch is a transistor seconds, one first end of this transistor seconds couples this control end points, one second end of this transistor seconds and a grid are all coupled to receive this non-inverting signal input thereof point reversely inputting signal, and the 4th switch reversely inputs this voltage potential of signal and switches its conducting state according to this；And
One control circuit, it is coupled to this control end points, and receive one first clock signal, export this first clock signal or certain voltage signal as this gate drive signal in order to this voltage potential according to this control end points in an exit point selectivity of this shift register。
2. image display system as claimed in claim 1, it is characterised in that this forward input circuit is mutually symmetrical with in structure with this reverse input circuit。
3. image display system as claimed in claim 1, also includes a display pannel, and wherein this display pannel includes:
This gate driver circuit；
This picture element matrix；
One data drive circuit, in order to produce multiple data drive signal to provide data to the described pixel of this picture element matrix；And
One control chip, produces one first initial pulse wave and one second initial pulse wave, in order to this bidirectional shift register module initial,
Wherein the first order shift register of this bidirectional shift register module receives this first initial pulse wave and inputs signal as this forward, afterbody shift register receives this second initial pulse wave and reversely inputs signal as this, and this gate drive signal that at least one reception previous stage shift register of described shift register exports inputs signal as this forward, and this gate drive signal that reception rear stage shift register exports reversely inputs signal as this。
4. image display system as claimed in claim 1, it is characterised in that this forward input circuit also includes:
One second switch, is coupled between this control end points and this forward signal input endpoint, and the voltage potential according to one second clock signal switches its conducting state；And
One the 3rd switch, is coupled between this control end points and this determining voltage signal, and this voltage potential according to this forward reset signal switches its conducting state。
5. image display system as claimed in claim 1, it is characterised in that this reverse input circuit also includes:
One the 5th switch, is coupled between this control end points and this non-inverting signal input thereof point, and the voltage potential according to one the 3rd clock signal switches its conducting state；And
One the 6th switch, is coupled between this control end points and this determining voltage signal, and this voltage potential according to this reverse reset signal switches its conducting state。
6. image display system as claimed in claim 4, it is characterised in that when forward scan, this first switch is first switched on this second switch, in order to a voltage of this control end points that charges, then the 3rd switch is switched on, in order to this voltage of this control end points that discharges。
7. image display system as claimed in claim 5, it is characterised in that when reverse scan, 4th switch is first switched on the 5th switch, in order to a voltage of this control end points that charges, then the 6th switch is switched on, in order to this voltage of this control end points that discharges。
8. image display system as claimed in claim 1, it is characterised in that this gate driver circuit be with non-crystalline silicon integrated gate drivers (AmorphousSiliconGatedriver, ASG) fabrication techniques on this substrate。
9. a gate driver circuit, is made on a substrate, in order to produce multiple gate drive signal to drive multiple pixels of the picture element matrix being positioned on this substrate, including:
One two-way shift register module, including the shift register of multi-stage serial connection, at least one of wherein said shift register includes:
One forward input circuit, receive forward input signal and a forward reset signal, and a voltage potential of the voltage potential and this forward reset signal inputting signal according to this forward when forward scan controls a voltage potential of end points, wherein this forward input circuit has one first switch, this first switch is a first transistor, one first end of this first transistor couples this control end points, one second end of this first transistor and a grid are all coupled to receive a forward signal input endpoint of this forward input signal, and this voltage potential that this first switch inputs signal according to this forward switches its conducting state；
One reverse input circuit, receives one and reversely inputs signal and a reverse reset signal, and a voltage potential of the voltage potential and this reverse reset signal reversely inputting signal according to this when reverse scan controls this voltage potential of this control end points；And
One control circuit, it is coupled to this control end points, and receive one first clock signal, this first clock signal or certain voltage signal is exported as this gate drive signal in an exit point selectivity of this shift register in order to this voltage potential according to this control end points, wherein this forward input circuit has one the 4th switch, 4th switch is a transistor seconds, one first end of this transistor seconds couples this control end points, one second end of this transistor seconds and a grid are all coupled to receive this non-inverting signal input thereof point reversely inputting signal, and the 4th switch reversely inputs this voltage potential of signal and switches its conducting state according to this。
10. gate driver circuit as claimed in claim 9, it is characterised in that this forward input circuit is mutually symmetrical with in structure with this reverse input circuit。
11. gate driver circuit as claimed in claim 9, it is characterised in that this forward input circuit also includes:
One second switch, is coupled between this control end points and this forward signal input endpoint, and the voltage potential according to one second clock signal switches its conducting state；And
One the 3rd switch, is coupled between this control end points and this determining voltage signal, and this voltage potential according to this forward reset signal switches its conducting state。
12. gate driver circuit as claimed in claim 9, it is characterised in that this reverse input circuit also includes:
One the 5th switch, is coupled between this control end points and this non-inverting signal input thereof point, and the voltage potential according to one the 3rd clock signal switches its conducting state；And
One the 6th switch, is coupled between this control end points and this determining voltage signal, and this voltage potential according to this reverse reset signal switches its conducting state。
13. gate driver circuit as claimed in claim 9, it is characterized in that, when forward scan, this forward input circuit inputs signal according to this forward and charges a voltage of this control end points, and this reverse input circuit according to this reversely input signal assist this forward input circuit to charge this voltage of this control end points。
14. gate driver circuit as claimed in claim 9, it is characterized in that, when reverse scan, this reverse input circuit according to this reversely input signal charge a voltage of this control end points, and this forward input circuit inputs signal according to this forward and assists this reverse input circuit to charge this voltage of this control end points。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110409167.XA CN103137057B (en) | 2011-11-25 | 2011-11-25 | Image display system and gate driver circuit |
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| CN104240628B (en) * | 2013-06-17 | 2017-03-01 | 群创光电股份有限公司 | Display pannel and bidirectional shift register circuit |
| CN106328075B (en) * | 2015-06-25 | 2019-05-31 | 群创光电股份有限公司 | Image display system and gate driving circuit |
| CN113823212B (en) * | 2021-09-28 | 2022-05-31 | 惠科股份有限公司 | Driving method and circuit of display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881803A (en) * | 2005-05-20 | 2006-12-20 | 日本电气株式会社 | Bootstrap circuit, and shift register, scanning circuit, display device using the same |
| CN101079243A (en) * | 2006-05-25 | 2007-11-28 | 三菱电机株式会社 | Shift register circuit and image display apparatus equipped with the same |
| US7515134B2 (en) * | 2005-02-01 | 2009-04-07 | Seiko Epson Corporation | Bidirectional shift register |
| CN101894588A (en) * | 2010-01-11 | 2010-11-24 | 友达光电股份有限公司 | Bidirectional shift register and its driving method |
-
2011
- 2011-11-25 CN CN201110409167.XA patent/CN103137057B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7515134B2 (en) * | 2005-02-01 | 2009-04-07 | Seiko Epson Corporation | Bidirectional shift register |
| CN1881803A (en) * | 2005-05-20 | 2006-12-20 | 日本电气株式会社 | Bootstrap circuit, and shift register, scanning circuit, display device using the same |
| CN101079243A (en) * | 2006-05-25 | 2007-11-28 | 三菱电机株式会社 | Shift register circuit and image display apparatus equipped with the same |
| CN101894588A (en) * | 2010-01-11 | 2010-11-24 | 友达光电股份有限公司 | Bidirectional shift register and its driving method |
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Address after: 518100 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant after: Qunkang Technology (Shenzhen) Co., Ltd. Applicant after: Innolux Display Group Address before: 518100 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant before: Qunkang Technology (Shenzhen) Co., Ltd. Applicant before: Chimei Optoelectronics Co., Ltd. |
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