CN103136159A - Method used for control and information interaction of multiprocessor system - Google Patents
Method used for control and information interaction of multiprocessor system Download PDFInfo
- Publication number
- CN103136159A CN103136159A CN2011103878673A CN201110387867A CN103136159A CN 103136159 A CN103136159 A CN 103136159A CN 2011103878673 A CN2011103878673 A CN 2011103878673A CN 201110387867 A CN201110387867 A CN 201110387867A CN 103136159 A CN103136159 A CN 103136159A
- Authority
- CN
- China
- Prior art keywords
- processor
- register
- command
- slave
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Multi Processors (AREA)
Abstract
The invention relates to an implementation method used for control and information interaction of a multiprocessor system. The method includes the following steps: (1) configuring hardware semaphore between a master processor and a slave processor; and (2) building an information interaction area for the master processor and the slave processor. The method used for the information interaction of the multiprocessor system is simple, effective and reliable, and the efficiency and reliability of the information interaction of the multiprocessor system can be promoted.
Description
Technical field
The invention belongs to the computer hardware technology field, relate to a kind of control for multiple processor system and information interaction implementation method.
Background technology
At present, multiprocessor research is in hot topic, and carrying out information interaction in multiple processor system has multiple strategy.But the efficient of various interactive strategies is different, and it is larger that reliability also differs, and makes its poor stability.
Summary of the invention
In order to solve the above-mentioned technical matters that exists in background technology, the invention provides a kind of simple method of multiple processor system information interaction effectively reliably, use the present invention can improve efficient and the reliability of multiprocessor information interaction.
Technical solution of the present invention is: the invention provides a kind of control for multiple processor system and information interacting method, its special character is: described control and information interacting method for multiple processor system comprises the following steps:
1) configure hardware semaphore between Master processor and Slave processor;
2) Master processor and Slave processor are set up the information interaction district.
Above-mentioned control and information interacting method for multiple processor system also comprises:
3) Master processor and Slave processor command parameter register R1 and command result register R2.
Above-mentioned steps 1) specific implementation is:
1.1) command parameter register R1 and command result register R2 use identical address at Master processor and Slave processor; Described Slave processor read operation visit order result register R2, described Slave processor write operational access command parameter register R1; Described Master processor read operation visit order parameter register R1, described Master processor write operational access command result register R2; Described command parameter register R1 and command result register R2 power on or the value afterwards that resets is respectively 0 and 1;
1.2) described Slave processor is in the order of handling main frame or need to be to Master processor circular asynchronous event the time, at first read the value of this semaphore, if 1, representing currently has semaphore to use, send an interrupt to the Master processor by operation Slave processor to Master processor interrupt register this moment, produce slave_to_master int, and obtaining by write signal amount register settling signal amount, the value of obtaining semaphore post command parameter register R1 is updated to 1, the value of command result register R2 becomes 0, the variation of command parameter register R1 and command result register R2 must be completed under the operation of Slave processor write is controlled simultaneously, if the value of this semaphore is non-1, representing currently has semaphore unavailable, does not operate on it,
1.3) described Master processor has no progeny in receiving the Slave processor, at first judges the value of this semaphore register, if the value that reads is 1, represents that current interrupt event is asynchronous or command response, otherwise think other queue events; When this semaphore is 1, described Master processor needs the release by write operation settling signal amount after obtaining the reason word, state when discharging this semaphore post command parameter register R1 and command result register R2 and resetting, the variation of the value of command parameter register R1 and command result register R must be completed under the control of main frame write operation simultaneously.
Above-mentioned steps 2) the information interaction district in is used for the information interaction between Master processor and Slave processor; Either party in described Master processor and Slave processor can notify the other side with interrupt mode after write operation is carried out in this information interaction zone; Described information interaction district is the continuous block space of address space, is used for depositing the Master processor pair in information such as the result of the control command of Slave processor and Slave processor, states, supports single the bat and the Burst access mode; Described Master processor and Slave processor information interaction district all carry out single-ended access to this Interspace only.
Above-mentioned steps 3) Master processor write command parameter register in, the read command result register; Described Slave processor read command parameter register, the write order result register; Command parameter register R1 and command result register R2 mainly deposit the order of this Master processor and execution result and the state of Slave processor.
Above-mentioned register is 32bit or 64 access modes.
Above-mentioned register is one or more.
The number of mentioned order parameter register and command result register arranges according to the ICD of system definition.
Advantage of the present invention is:
control and information interacting method for multiple processor system provided by the invention, be mainly used in carrying out information interaction between multiprocessor in multiple processor system, comprise that master processor transferring command transmits execution result to processes such as master processors to slave processor and slave processor, the control and the information interaction mechanism that are used for multiple processor system of invention mainly comprise three modules, respectively hardware semaphore and the interruption between Master processor and Slave processor, Master processor and Slave processor information interaction district and Master processor and Slave processor coomand mode, the command result register.The invention provides a kind of simple method of multiple processor system information interaction effectively reliably, use the present invention can improve efficient and the reliability of multiprocessor information interaction.
Description of drawings
Fig. 1 is the schematic flow sheet of multiple processor system information interacting method provided by the present invention;
Fig. 2 is the schematic diagram of Master processor and the asynchronous time mutex of Slave processor amount.
Embodiment
Referring to Fig. 1, the invention provides a kind of control for multiple processor system and information interacting method, the method mainly comprises three modules, is respectively hardware semaphore between Master processor and Slave processor and interruption, Master processor and Slave processor information interaction district and Master processor and Slave processor coomand mode, command result register.
1) hardware semaphore between Master processor and Slave processor:
This function is mainly in order to guarantee that the Master processor adapts to different access speeds when processing asynchronous event with the Slave processor, guarantee that Master processor and Slave processor are in the coupling of interrupting on processing speed.Obtain this semaphore by the Slave processor, and discharge this semaphore by the Master processor.And this hardware semaphore one end is operated by the Slave processor, realize obtaining of semaphore, an other end is realized the release of semaphore by the Master processor operation.The realization mechanism of this semaphore is as shown in Figure 2:
Illustrate:
Command parameter register R1 and command result register R2 use identical address at Master processor and Slave processor, distinguish concrete access object with read-write, Slave processor read operation access R2 register, write operation access R1 register; Master processor read operation access R1 register, write operation access R2 register;
R1 and R2 power on or the value afterwards that resets is respectively 0 and 1;
the Slave processor is when handling the order of main frame (first with interrupt mode notice master_to_slave int) or need to circulate a notice of asynchronous event to the Master processor, first read the value of this semaphore, if 1, representing currently has semaphore to use, send an interrupt to the Master processor by operation Slave processor to Master processor interrupt register this moment, produce slave_to_master int, and obtaining by write signal amount register settling signal amount, after obtaining semaphore, the R1 register value is updated to 1, the R2 register value becomes 0, the variation of R1 and R2 register must be completed under the operation of Slave processor write is controlled simultaneously,
the Master processor is had no progeny in receiving the Slave processor, at first judge the value of this semaphore register, if the value that reads is 1, represent that current interrupt event is asynchronous or command response, otherwise think other queue events (can be used for data communication and equipment asynchronous interrupt), when this semaphore is 1, the Master processor needs the release by write operation settling signal amount after obtaining the reason word, discharge the state when R1 and R2 register reset after this semaphore, the variation of the value of R1 and R2 register must be completed under the control of main frame write operation simultaneously.
2) Master processor and Slave processor information interaction district
The information interaction district is used for the information interaction between Master processor and Slave processor, after a side carries out write operation to this zone, can notify the other side with interrupt mode.Need the Slave processor to process some operation as the Master processor, all can realize by the operation to the information interaction district.
The information interaction district is the continuous block space of address space, is used for depositing the Master processor pair in information such as the result of the control command of Slave processor and Slave processor, states, supports single the bat and the Burst access mode.
Master processor and Slave processor information interaction district all carry out single-ended access to this space only, and an end is read-only, and the other end is only write.
3) Master processor and Slave processor coomand mode, command result register
Command register block is as replenishing of information interaction district, and the operation of this group register and purposes and information interaction district are substantially similar, Master processor write command parameter register, read command result register; Slave processor read command parameter register, the write order result register.This register is mainly deposited the order of this Master processor and execution result and the state of Slave processor, be conducive to the more effective transmission command of Master processor to the Slave processor, the treatment state of Slave processor also more can effectively feed back to the Master processor simultaneously.Register is 32bit or 64 access modes (arranging according to the difference of system).How much can arranging according to the ICD of system definition of command parameter and command result register.
Table coomand mode, command result register
Claims (8)
1. control and information interacting method that is used for multiple processor system, it is characterized in that: described control and information interacting method for multiple processor system comprises the following steps:
1) configure hardware semaphore between Master processor and Slave processor;
2) Master processor and Slave processor are set up the information interaction district.
2. control and information interacting method for multiple processor system according to claim 1, it is characterized in that: described control and information interacting method for multiple processor system also comprises:
3) Master processor and Slave processor command parameter register R1 and command result register R2.
3. control and information interacting method for multiple processor system according to claim 1 and 2, it is characterized in that: specific implementation described step 1) is:
1.1) command parameter register R1 and command result register R2 use identical address at Master processor and Slave processor; Described Slave processor read operation visit order result register R2, described Slave processor write operational access command parameter register R1; Described Master processor read operation visit order parameter register R1, described Master processor write operational access command result register R2; Described command parameter register R1 and command result register R2 power on or the value afterwards that resets is respectively 0 and 1;
1.2) described Slave processor is in the order of handling main frame or need to be to Master processor circular asynchronous event the time, at first read the value of this semaphore, if 1, representing currently has semaphore to use, send an interrupt to the Master processor by operation Slave processor to Master processor interrupt register this moment, produce slave_to_master int, and obtaining by write signal amount register settling signal amount, the value of obtaining semaphore post command parameter register R1 is updated to 1, the value of command result register R2 becomes 0, the variation of command parameter register R1 and command result register R2 must be completed under the operation of Slave processor write is controlled simultaneously, if the value of this semaphore is non-1, representing currently has semaphore unavailable, does not operate on it,
1.3) described Master processor has no progeny in receiving the Slave processor, at first judges the value of this semaphore register, if the value that reads is 1, represents that current interrupt event is asynchronous or command response, otherwise think other queue events; When this semaphore is 1, described Master processor needs the release by write operation settling signal amount after obtaining the reason word, state when discharging this semaphore post command parameter register R1 and command result register R2 and resetting, the variation of the value of command parameter register R1 and command result register R must be completed under the control of main frame write operation simultaneously.
4. control and information interacting method for multiple processor system according to claim 3 is characterized in that: the information interaction district described step 2) is used for the information interaction between Master processor and Slave processor; Either party in described Master processor and Slave processor can notify the other side with interrupt mode after write operation is carried out in this information interaction zone; Described information interaction district is the continuous block space of address space, is used for depositing the Master processor pair in information such as the result of the control command of Slave processor and Slave processor, states, supports single the bat and the Burst access mode; Described Master processor and Slave processor information interaction district all carry out single-ended access to this Interspace only.
5. control and information interacting method for multiple processor system according to claim 4, is characterized in that: Master processor write command parameter register described step 3), read command result register; Described Slave processor read command parameter register, the write order result register; Command parameter register R1 and command result register R2 mainly deposit the order of this Master processor and execution result and the state of Slave processor.
6. control and information interacting method for multiple processor system according to claim 5, it is characterized in that: described register is 32bit or 64 access modes.
7. control and information interacting method for multiple processor system according to claim 6, it is characterized in that: described register is one or more.
8. control and information interacting method for multiple processor system according to claim 7, it is characterized in that: the number of described command parameter register and command result register arranges according to the ICD of system definition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103878673A CN103136159A (en) | 2011-11-29 | 2011-11-29 | Method used for control and information interaction of multiprocessor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103878673A CN103136159A (en) | 2011-11-29 | 2011-11-29 | Method used for control and information interaction of multiprocessor system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103136159A true CN103136159A (en) | 2013-06-05 |
Family
ID=48496001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103878673A Pending CN103136159A (en) | 2011-11-29 | 2011-11-29 | Method used for control and information interaction of multiprocessor system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103136159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106293825A (en) * | 2016-08-05 | 2017-01-04 | 武汉虹信通信技术有限责任公司 | A kind of multinuclear based on hardware semaphore starts synchronous method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87106124A (en) * | 1986-07-28 | 1988-03-30 | 霍尼韦尔·布尔公司 | The multiple central processor interlock |
| CN1030312A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | In the multiprocessor data handling system to the apparatus and method of main memory sets of signals synchronization of access |
| CN1885282A (en) * | 2005-06-22 | 2006-12-27 | 株式会社瑞萨科技 | Multi-processor system |
-
2011
- 2011-11-29 CN CN2011103878673A patent/CN103136159A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87106124A (en) * | 1986-07-28 | 1988-03-30 | 霍尼韦尔·布尔公司 | The multiple central processor interlock |
| CN1030312A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | In the multiprocessor data handling system to the apparatus and method of main memory sets of signals synchronization of access |
| CN1885282A (en) * | 2005-06-22 | 2006-12-27 | 株式会社瑞萨科技 | Multi-processor system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106293825A (en) * | 2016-08-05 | 2017-01-04 | 武汉虹信通信技术有限责任公司 | A kind of multinuclear based on hardware semaphore starts synchronous method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102077181B (en) | Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems | |
| CN103955441B (en) | Equipment management system, equipment management method and IO (Input/Output) expansion interface | |
| CN101416137B (en) | Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates | |
| CN101901200B (en) | Method for realizing double advanced high-performance bus (AHB) Master interface-based on-chip direct memory access (DMA) controller | |
| JP6475625B2 (en) | Inter-core communication apparatus and method | |
| KR20140079417A (en) | Apparatus and methods for an interconnect power manager | |
| CN108566634A (en) | Reduce method, apparatus and Baffle Box of Bluetooth that Baffle Box of Bluetooth continuously wakes up delay | |
| CN102929363B (en) | A kind of method for designing of high-density blade server | |
| CN204833236U (en) | Support memory system of hybrid storage | |
| CN101625568A (en) | Synchronous data controller based hot standby system of main control unit and method thereof | |
| CN1952900A (en) | Method for synchronizing program flow between processors on programmable general multi-core processor chip | |
| CN105138494B (en) | A kind of multichannel computer system | |
| CN102736594A (en) | Modular design method of unified platform of intelligent power distribution terminal | |
| CN102364444A (en) | System guiding method based on interaction of in-band system and out-of-band system | |
| CN102541616A (en) | Embedded operating system virtual machine and implementation method thereof | |
| CN100517177C (en) | Combined type reset system processing method and device | |
| CN106372029A (en) | Point-to-point on-chip communication module based on interruption | |
| CN201932198U (en) | Computer interlocking control system with parallel double 2-vote-2 structure | |
| CN103136159A (en) | Method used for control and information interaction of multiprocessor system | |
| CN116700445A (en) | Full flash ARM storage server based on distributed storage hardware architecture | |
| CN101324863B (en) | Device and method for controlling synchronous static memory | |
| CN106936901B (en) | A kind of intercommunication system and its implementation based on MSA agreement | |
| CN115168141A (en) | Optical interface management system, method, device, programmable logic device and storage medium | |
| CN106997278A (en) | In a kind of raising solid state hard disc between double-core communication efficiency method | |
| CN113296899A (en) | Transaction master machine, transaction slave machine and transaction processing method based on distributed system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130605 |