CN106997278A - In a kind of raising solid state hard disc between double-core communication efficiency method - Google Patents

In a kind of raising solid state hard disc between double-core communication efficiency method Download PDF

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Publication number
CN106997278A
CN106997278A CN201710131570.8A CN201710131570A CN106997278A CN 106997278 A CN106997278 A CN 106997278A CN 201710131570 A CN201710131570 A CN 201710131570A CN 106997278 A CN106997278 A CN 106997278A
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CN
China
Prior art keywords
fifo
cpu0
cpu1
request
double
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CN201710131570.8A
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Chinese (zh)
Inventor
许毅
姚兰
郑春阳
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Ramaxel Technology Shenzhen Co Ltd
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Ramaxel Technology Shenzhen Co Ltd
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Priority to CN201710131570.8A priority Critical patent/CN106997278A/en
Publication of CN106997278A publication Critical patent/CN106997278A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • G06F3/0607Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)

Abstract

The invention discloses a kind of method for improving communication efficiency between double-core in solid state hard disc, double-core is respectively CPU1 and CPU0, CPU1 and CPU0 co-operates circular list FIFO, circular list depth is N, FIFO is by each node one queue nodes of correspondence, it is characterized in that the request for being currently needed for submitting is formed requesting node list by CPU0 or CPU1, when CPU0 or CPU1 obtains current queue control, then FIFO is mounted to using requesting node list as a queue nodes, when system goes to the queue nodes of activity control, then perform all requests in the requesting node list in queue nodes.Normal practice of the invention by breaking through existing FIFO, CPU is accessed to FIFO every time only operates a request to be adjusted to operable multiple requests, specially one request list, greatly reduces the number of times that CPU accesses FIFO, and contrast prior art has been obviously improved CPU operation FIFO efficiency.

Description

In a kind of raising solid state hard disc between double-core communication efficiency method
Technical field
It is more particularly to a kind of to improve in solid state hard disc communication efficiency between double-core the present invention relates to solid state hard disc control technology Method.
Background technology
The chip SOC of solid-state hard disk SSD is typically all double-core or multinuclear, also referred to as dual processors or multi -CPU, and a core is exactly One CPU, needs to consider the efficiency and security of double intercore communications in the design of firmware.In current firmware design one between double-core As communicated by fifo queue FIFO, in order to ensure security double-core synchronization can not while operate FIFO, if Be that each FIFO is equipped with a signal lock in meter, any one core is operated to be needed to take lock before the FIFO, if the lock by Another core is taken away, then needs to wait the signal lock to be released, this has resulted in communication efficiency between temporal loss, i.e. double-core Reduction.
Fig. 1 is the FIFO round-robin queues schematic diagram of a prior art, and the fifo queue generally comprises following information:It is idle Number:Represent request number idle in FIFO;Number of request:Expression is had been filed on to FIFO number of request;Queue depth N:Represent The open ended request sums of FIFO;Write point P1:Represent the position of next write request;Read point P2:Represent next to read Take the position of request;Lock:CPU could operate FIFO after only taking lock, and another CPU cannot the lock, behaviour during operation Lock is discharged after the completion of work, another CPU can just take lock.
It is now assumed that double-core includes CPU0 and CPU1, CPU0 only submit write request to FIFO, CPU1 is only read from FIFO please Ask.
It is as follows that CPU0 submits request to be operated to FIFO:First attempt to take lock, take lock unsuccessfully to wait if not getting straight To by locking successfully;Lock is then held after taking lock, and is locked, request is written to write-in point position, then write-in point is moved back by One position, idle number subtracts 1, and number of request adds 1;Release lock.
CPU1 read requests operations from FIFO are as follows:First attempt to take lock, take lock unsuccessfully to wait if not getting Until taking lock;Lock is then held after taking lock, and is locked, request is taken out from point is read, point is then read and is moved back by a position Put, idle number adds 1, and number of request subtracts 1, release lock.
From process above it is also seen that operating FIFO to lock why, because CPU0 submits request and CPU1 to read Take request all to operate idle number and number of request, if do not locked, there can be two CPU and operate idle number or number of request simultaneously Moment, then idle number or number of request will become a not expected value.It could be operated just because of lock must be taken FIFO, centre has the process for waiting lock to be released, and causes waste of time, causes communication efficiency to reduce.
The content of the invention
For disadvantages described above, the present invention seeks to how to overcome ensured in the prior art using lock communication security and The problem of operation FIFO only handles one and asks and cause inefficiency every time.
A kind of method for improving communication efficiency between double-core in solid state hard disc is proposed in order to solve the problem above present invention, it is double Core is respectively CPU1 and CPU0, and CPU1 and CPU0 co-operate circular list FIFO, and circular list depth is N, and FIFO is by each Node one queue nodes of correspondence, it is characterised in that the request for being currently needed for submitting is formed requesting node and arranged by CPU0 or CPU1 Table, when CPU0 or CPU1 obtains current queue control, is then mounted to FIFO using requesting node list as a queue nodes, When system goes to the queue nodes of activity control, then perform queue nodes in requesting node list on institute ask the visitor in Ask.
In the raising solid state hard disc between double-core communication efficiency method, it is characterised in that the mechanism that FIFO passes through signal lock CPU0 or CPU1 is controlled to obtain current queue control.
In the raising solid state hard disc between double-core communication efficiency method, it is characterised in that CPU0 only write to circular list Request, CPU1 is only from circular list read requests;CPU0 controls FIFO write-in point to be P1, and CPU1 controls the FIFO reading point to be P2;CPU0 and CPU1 directly judges whether operable FIFO by judging P1 and P2 numerical relation.
The described method for improving communication efficiency between double-core in solid state hard disc, it is characterised in that CPU0 and CPU1 pass through as follows The numerical relation that step carries out P1 and P2 judges to determine how operation, when CPU0 will perform write request operation, calculated FIFO idle number is K, when P1 is less than P2, K=P2-P1-1;When P1 is not less than P2, K=(N-1)-(P1-P2);If K =0 wait, a position is moved after otherwise directly performing write request operation, write-in point;When CPU0 will perform read requests behaviour When making, the number of request for calculating FIFO is H, when P1 is less than P2, H=N- (P2-P1);When P1 is not less than P2, H=P1-P2;Such as Fruit H=0 is then waited, and otherwise directly performs read requests operation, and a position is moved after reading point.
Normal practice of the invention by breaking through existing FIFO, CPU is accessed every time FIFO and only operates a request adjustment For operable multiple requests, specially one request list greatly reduces the number of times that CPU accesses FIFO, contrasts prior art It has been obviously improved CPU operation FIFO efficiency.
Brief description of the drawings
Fig. 1 is the FIFO round-robin queues schematic diagram of a prior art;
Fig. 2 is the FIFO round-robin queues schematic diagram after improving.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.
Fig. 2 is the FIFO round-robin queues schematic diagram after improving, and CPU0 or CPU1 submit FIFO only every time in the prior art It is to submit a request as requesting node, and the present invention is adjusted to the institute for submitting current time correspondence CPU0 or CPU1 needs There is request to form requesting node list, disposably submit to FIFO;When CPU0 or CPU1 obtains current queue control, by queue Node is read out from FIFO, when system goes to the queue nodes of activity control, then performs asking in queue nodes Ask all requests on node listing.Assuming that CPU0 only submits (write-in) request to FIFO, CPU1 only from FIFO read requests, that CPU0 needs all requests that this can be submitted to form request list before accessing FIFO, and then this request list is submitted Into FIFO.What similarly CPU1 was read from FIFO is no longer a request, but a request list, and CPU1 needs to parse this Individual list, splits into it and asks node one by one to handle.In this way, under the total same case of request, CPU0 and CPU1 are accessed FIFO number of times will greatly reduce, so that time-consuming caused by waiting lock to be released will also be reduced, greatly promote what is communicated between CPU Efficiency.
Above disclosed is only an embodiment of the present invention, can not limit the interest field of sheet with this certainly, One of ordinary skill in the art will appreciate that all or part of flow of above-described embodiment is realized, and according to the claims in the present invention institute The equivalent variations of work, still fall within the scope that the present invention is covered.

Claims (4)

1. a kind of method for improving communication efficiency between double-core in solid state hard disc, double-core is respectively CPU1 and CPU0, CPU1 and CPU0 Circular list FIFO is co-operated, circular list depth is N, and FIFO is existed by each node one queue nodes of correspondence, its feature The request for being currently needed for submitting is formed into requesting node list in CPU0 or CPU1, when CPU0 or CPU1 obtains current queue control Power, then be mounted to FIFO, when system goes to the queue section of activity control using requesting node list as a queue nodes During point, then all requests in the requesting node list in queue nodes are performed.
2. the method for communication efficiency between double-core in solid state hard disc is improved according to claim 1, it is characterised in that FIFO passes through The mode of signal lock mechanism controls CPU0 or CPU1 to obtain current queue control.
3. improve the method for communication efficiency between double-core in solid state hard disc according to claim 1, it is characterised in that CPU0 only to Circular list write request, CPU1 is only from circular list read requests;CPU0 controls FIFO write-in point to be P1, CPU1 controls FIFO reading point is P2;CPU0 and CPU1 directly judges whether operable FIFO by judging P1 and P2 numerical relation.
4. the method according to claim 3 for improving communication efficiency between double-core in solid state hard disc, it is characterised in that CPU0 and The numerical relation that CPU1 carries out P1 and P2 as follows judges to determine how operation, when CPU0 will perform write request behaviour When making, the idle number for calculating FIFO is K, when P1 is less than P2, K=P2-P1-1;When P1 is not less than P2, K=(N-1)-(P1- P2);Waited if K=0, a position is moved after otherwise directly performing write request operation, write-in point;When CPU0 will perform reading When taking request operation, the number of request for calculating FIFO is H, when P1 is less than P2, H=N- (P2-P1);When P1 is not less than P2, H= P1-P2;Waited if H=0, otherwise directly perform read requests operation, a position is moved after reading point.
CN201710131570.8A 2017-03-07 2017-03-07 In a kind of raising solid state hard disc between double-core communication efficiency method Pending CN106997278A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109032522A (en) * 2018-07-25 2018-12-18 浪潮电子信息产业股份有限公司 Data reading method of solid state disk and solid state disk
CN109542832A (en) * 2018-11-30 2019-03-29 青岛方寸微电子科技有限公司 Communication system and method between a kind of heterogeneous polynuclear CPU of no lock mechanism

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218313A (en) * 2013-04-02 2013-07-24 杭州华三通信技术有限公司 Method and electric device for interacting cache descriptors
CN105045632A (en) * 2015-08-10 2015-11-11 京信通信技术(广州)有限公司 Method and device for implementing lock free queue in multi-core environment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218313A (en) * 2013-04-02 2013-07-24 杭州华三通信技术有限公司 Method and electric device for interacting cache descriptors
CN105045632A (en) * 2015-08-10 2015-11-11 京信通信技术(广州)有限公司 Method and device for implementing lock free queue in multi-core environment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109032522A (en) * 2018-07-25 2018-12-18 浪潮电子信息产业股份有限公司 Data reading method of solid state disk and solid state disk
CN109032522B (en) * 2018-07-25 2021-06-29 浪潮电子信息产业股份有限公司 Data reading method of solid state disk and solid state disk
CN109542832A (en) * 2018-11-30 2019-03-29 青岛方寸微电子科技有限公司 Communication system and method between a kind of heterogeneous polynuclear CPU of no lock mechanism

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Application publication date: 20170801