CN103117225A - Production method preventing body effect in trench power MOS (metal oxide semiconductor) transistors - Google Patents
Production method preventing body effect in trench power MOS (metal oxide semiconductor) transistors Download PDFInfo
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- CN103117225A CN103117225A CN2013100339529A CN201310033952A CN103117225A CN 103117225 A CN103117225 A CN 103117225A CN 2013100339529 A CN2013100339529 A CN 2013100339529A CN 201310033952 A CN201310033952 A CN 201310033952A CN 103117225 A CN103117225 A CN 103117225A
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Abstract
The invention relates to a production method of semiconductor devices and particularly aims to provide a production method preventing body effect in trench power MOS (metal oxide semiconductor) transistors. A contact hole doping process is added mainly to guarantee same type of doping in certain range and body region below contact holes. When the contact holes fail to penetrate a source region due to process errors, an unpenetrated source region thin inversion layer below the contact holes is doped in the same type as the body region, so that the problem of failure caused by the body effect in the production of trench power MOS transistors is solved effectively.
Description
Technical field
The present invention relates to a kind of preparation method of semiconductor device, more precisely, the present invention aims to provide a kind of its preparation process that prevents groove-type power MOS transistor bulk effect.
Background technology
The advantages such as low and structure cell density is large based on state resistance, technique is more simplified, the groove-type power MOS transistor is comparatively popular in current power device.For example Chinese patent application 200510111168.0 discloses a kind of preparation method of grooved MOSFET, as shown in Figure 1A, be formed with groove in silicon substrate and be prepared with grid 3 in groove, thereafter when etching forms contact hole 5, after etch step proceeds to the silicon substrate surface, continue downward etch silicon matrix, make contact hole 5 penetrate source region 2 to being positioned at tagma 1, usually need the degree of depth of etch silicon matrix to be
Current, the method that illustrated this contact hole penetrates the source region is widely used by industry in the preparation process of groove-type power MOS transistor, under ideal state, the metal plug that is filled in contact hole can be realized ohmic contact with source region and tagma, can reach source region and tagma and keep equipotential target by metal plug, namely for N-type MOSFET, source region and tagma keep zero potential, for P type MOSFET, source region and tagma keep high potential.
Strengthen in the method for ohmic contact at some, industry tends to carry out the step that the contact hole Implantation forms contact injection region 6 after contact hole 5 is completed in preparation, as shown in Figure 1B, the foreign ion that injects is identical with tagma 1 in type, namely for the N-type power MOS transistor, contact hole doping ion is the P type, and for P type power MOS transistor, contact hole doping ion is N-type.The general Implantation Energy that forms when contacting injection region 6 is less, but dosage is larger, and its purpose is to form the ohmic contact between metal plug 7 and tagma 1.
The degree of depth for contact hole 5 downward etch silicon matrixes has two aspect requirements, and the one, requirement penetrates source region 2, to satisfy source region 2 and tagma 1 equipotential; The 2nd, requirement is can not etching too dark, to prevent that contact hole 5 over etchings are to the deep epitaxial region to the tagma 1, because the epitaxial region is connected with drain terminal, to avoid producing negative high-voltage breakdown (punch through).Therefore, the process window (process window) of the degree of depth of contact hole 5 in the preparation of groove-type power MOS transistor is smaller.
A kind of component failure mechanism of routine is exactly that contact hole 5 degree of depth are inadequate or source region 2 is blocked up, causes contact hole 5 not penetrate source region 2 and arrives tagma 1, for example shown in Fig. 1 C.At this moment tagma 1 and source region 2 be equipotential no longer, and MOS transistor has bulk effect (body effect), will cause the source of device leak between puncture voltage (Bvdss) reduce and the source leak between leakage current (Idss) increase.In addition, at this moment metal plug 7 is PNPN knot (N-type MOSFET) structure or NPNP knot (P type MOSFET) structure to the epitaxial region under tagma 1, and it forces down than the body drain PN junction breakdown potential of routine, also can cause the Bvdss of device to reduce, in serious situation, may cause component failure.
The application is just for a kind of common failure mechanism in the preparation of groove-type power MOS transistor technique, be that contact hole does not penetrate the source region and causes the Bvdss of device to reduce and the Idss increase, following various preferred implementation has been proposed, to solve this common failure mechanism, improve the handicraft product yield.
Summary of the invention
The invention provides a kind of its preparation process that prevents groove-type power MOS transistor bulk effect, mainly comprise the following steps: a, provide a Semiconductor substrate, an epitaxial loayer that comprises a base substrate and grow above it, and form the tagma at the top of epitaxial loayer, and form groove and form grid in tagma and epitaxial loayer in groove; B, form source area at the top in tagma and round groove; C, form a dielectric layer on Semiconductor substrate, this dielectric layer is covered described grid simultaneously; D, carry out etching in described dielectric layer, Semiconductor substrate, form and run through this dielectric layer and extend to contact hole in Semiconductor substrate; E, utilize contact hole to implement alloy to implant, form the contact zone with first degree of depth that is centered around the contact hole bottom; F, utilize contact hole to implement alloy to implant, form the contact with second degree of depth and promote the district; Wherein second degree of depth is promoted the district with the contact zone adjacency or overlaps greater than first degree of depth and contact; G, preferably cover a metal barrier on the bottom of contact hole and sidewall and dielectric layer, and fill in contact hole that metal material forms a metal plug and deposition one metal level on this metal plug and metal barrier.
Above-mentioned method, described epitaxial loayer, source area are the first conduction type, described tagma is the second conduction type with the first conductivity type opposite, and described contact zone, contact are promoted the district and be the second conduction type.
Above-mentioned method, described contact are promoted the doping content in district greater than the doping content of described source area.
Above-mentioned method is carried out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in source area, makes the bottom of described contact hole be positioned at source area.Its a kind of execution mode is, described contact zone is positioned at source area, and described contact promotes the district and be positioned between described source area and tagma, and its part is positioned at source area and maintenance connects or overlaps with described contact zone, and another part is positioned at the tagma.Its another kind of execution mode, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.
Above-mentioned method is carried out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in the tagma, makes the bottom of described contact hole correspondingly be positioned at the tagma.Its a kind of execution mode is, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.Its another kind of execution mode is, described contact zone is promoted the district and all is implanted in the tagma with described the contact.
Above-mentioned method is carried out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in the upper surface in tagma, and the bottom of described contact hole correspondingly is positioned on the upper surface in tagma.Its a kind of execution mode is, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.
Above-mentioned method, first execution in step e forms after the contact zone execution in step f again and forms contact and promote the district.
Above-mentioned method, first execution in step f formation contact enhancement is distinguished afterwards execution in step e again and is formed the contact zone.
Above-mentioned method, described the first conduction type is N-type, described the second conduction type is the P type, and the described contact alloy of promoting the district is one or more in B, BF, BF2, In.
Above-mentioned method, described the first conduction type is the P type, described the second conduction type is N-type, and the described contact alloy of promoting the district is one or more in P, As.
Above-mentioned method, described contact are promoted the degree of depth in district between 100～2000 dusts.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
Description of drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only is used for explanation and sets forth, and does not consist of limitation of the scope of the invention.
Figure 1A～1B is the method that the mentioned current techniques of background technology forms contact hole.
Fig. 1 C is that contact hole mentioned in background technology does not reach a kind of inefficacy mechanism that the tagma ends in source area.
Fig. 2 A～2E is that the present invention forms the contact hole that ends at source area and a kind of execution mode of successively implementing twice doping below contact hole.
Fig. 3 A～3B be form end at the contact hole of source area after, a kind of execution mode that twice implantation of contact hole below alloy sequentially put upside down.
Fig. 4 A～4C is that the present invention forms the contact hole that ends at the tagma and a kind of execution mode of successively implementing twice doping below contact hole.
Fig. 5 A～5C be form end at the contact hole in tagma after, a kind of execution mode that twice implantation of twice alloy in contact hole below sequentially put upside down.
Fig. 6 A～6C is the schematic diagram that forms several critical conditions of contact hole.
Embodiment
Referring to Fig. 2 A, be the vertical section figure of a grooved MOSFET, for the ease of explaining and understand, existing MOSFET device take the N raceway groove is narrated explanation to the present invention as example.The epitaxial loayer 101 of growth one deck N-type on the front of the heavily doped base substrate 100 of a N+ type, Semiconductor substrate 150 has comprised the base substrate 100 of epitaxial loayer 101 and this epitaxial loayer 101 of carrying.Groove 105 just is formed in Semiconductor substrate 150, particularly, implement etching and can form many grooves 105 in epitaxial loayer 101, and the means by for example Implantation are formed with the tagma 102 that doping type is the P-type at the top of epitaxial loayer 105, take this to offer in the epitaxial loayer 101 below tagma 102 and tagma 102 many grooves 105 of tool certain depth.Every groove 105 all runs through tagma 102 and extends downward in the epitaxial loayer 101 of 102 belows, tagma, and be filled with such as polycrystalline silicon material in each groove 105 and form grid 107, and the bottom of groove 105 and the equal liner of sidewall have relatively thin gate oxide 106, epitaxial loayer 101 or tagma 102 near insulate isolated gate 107 and groove 105.Adulterate round each groove 105 and by the means of for example implanted ions and form the source area 103 of N+ type in 102 the top in the tagma, same, and grid 107 is also by the isolation of insulating of gate oxide 106 and source area 103.In follow-up step, on Semiconductor substrate 150, form a dielectric layer 108 as insulating barrier, it comprises low temperature oxide layer and borated silica glass layer (BPSG) usually, and this dielectric layer 108 covers on grid 107 and source area 103 simultaneously.
As Fig. 2 B, utilize a mask with opening figure that does not illustrate to define contact hole 110, namely utilize the opening in mask to come etching dielectric layer 108 and Semiconductor substrate 150, run through dielectric layer 108 and extend downward the interior contact hole 110 of Semiconductor substrate 150 thereby form.Follow conventional step, after obtaining contact hole 110, need to be by contact hole 110 to the interior dopant implant thing of Semiconductor substrate 150 toward contact, be accompanied by the step of diffusion, form a contact zone with first degree of depth 125 that is centered around contact hole 110 bottoms, the degree of depth herein refers to the degree of depth that the upper surface of relative Semiconductor substrate 150 is downward.Source area 103 is thicker or degree of depth etching is inadequate if meet with, cause contact hole 110 can't penetrate source area 103, in this case, just etching dielectric layer 108 and source area 103 and there is no etching tagma 102, form the structure of Fig. 2 B, contact zone 125 is implanted in source area 103 (as Fig. 2 C).Again pass through contact hole 110 to the interior dopant implant thing of Semiconductor substrate 150 thereafter, and be accompanied by the step of diffusion, form a contact with second degree of depth and promote district 126, set second degree of depth greater than first degree of depth, this can realize by the Implantation Energy of adjusting alloy, make contact promote district 126 be positioned at contact zone 125 under, and contact to promote district 126 adjacent or overlap with contact zone 125, as shown in Fig. 2 D.Be readily appreciated that, district 126 and contact zone 125 are promoted in contact, and the two overlaps, this means in contact and promote in the formation step in district 126, a part is used to prepare contact promotes the alloy in district 126 and is infused in contact zone 125, so that the part that district 126 is promoted in contact can be formed in contact zone 125 (as Fig. 2 D); Perhaps, in the formation step of contact zone 125, a part of alloy for the preparation of contact zone 125 is infused in the contact enhancement and distinguishes in 126, so that the part of contact zone 125 can be formed on contact enhancement district 126 interior (as Fig. 3 B).Here must satisfy a condition: contact zone 125 is just round the bottom of contact hole 110, and contact is promoted at least a portion zone in district 126 and will be positioned at tagma 102, to play the effect that is connected contact zone 125 and tagma 102.For each doped region of more detailed observation, the ratio of specially having amplified each doped region during follow-up each is graphic, but its contour shape does not only consist of structural restriction as explaining used.In some embodiments, contact is promoted district 126 between source area 103 and tagma 102, a part of zone that district 126 is promoted in contact is positioned at source area 103, and this subregion keeps connecting with contact zone 125, and another part that 126 remainders are distinguished in the contact enhancement is positioned at tagma 102.The doping type that district 126 and contact zone 125 are promoted in contact is usually identical with tagma 102, in some optional modes, the former doping content is preferably greater than the latter's doping content, and the General Requirements contact is promoted the doping content in district 126 greater than the doping content of source area 103.In some embodiments, contact is promoted the degree of depth in district 126 between 100～2000 dusts.
As Fig. 2 E, preferably also need to cover a metal barrier 104 on the bottom of contact hole 110 and sidewall and dielectric layer 108 afterwards, generally include titanium/titanium nitride (Ti/TiN), and form metal plug (claiming again interconnection structure) 135 at the interior filling metal material of contact hole 110 (as tungsten), common means for example deposits tungsten are filled in contact hole 110 and cover on metal barrier 104 and implement CMP or eat-back to it, only keep the metal plug 135 that is positioned at contact hole 110.Deposit afterwards a metal level 109 on metal plug 135 and metal barrier 104, general aluminium copper or the Al-Si-Cu alloy of adopting of metal level 109.In other optional execution modes, if contact hole 110 is enough large, also can save for example metal plug technique of aforementioned tungsten, the substitute is, Direct precipitation metal level 109 makes its filling contact hole 110 also cover on metal barrier 104 or directly overlay on dielectric layer 108 when forming metal plug 135, and namely metal plug 135 is integrated formation with metal level 109, both materials are identical, are also finally overall structures.Those skilled in the art knows, the composite bed of metal level 109 and metal barrier 104 will be etched to two independently regional (not shown), these two independently are electrically connected grid 107 and metal plug 135 on the unshowned in the drawings direction of zone difference, come respectively as gate pad and source electrode weld pad, the back side of base substrate 100 deposits another metal layer (not shown) as drain electrode end, in view of these contents are known by those skilled in the art, so repeat no more.The meaning of metal plug 135 not only is to be electrically connected source area 103 and metal level 109, also be source area 103 and tagma 102 are implemented electrical short, extend in tagma 102 as aforementioned bottom with contact hole 110, metal plug 135 also comes short circuit tagma and source area by means of heavily doped contact enhancement district 126 and contact zone 125, to keep this both equipotential.
In some embodiments, 126 sequentially not requirement of priority implantation is distinguished with contacting to promote in contact zone 125, terminate in the interior situation of source area 103 as Fig. 3 A～3B for etching, can be by contact hole 110 to the interior dopant implant thing of Semiconductor substrate 150, first implant the contact with second degree of depth and promote district 126, thereafter just the dopant implant thing forms the contact zone 125 with first degree of depth, and district 126 is promoted in abutting connection with contact in contact zone 125.As hereinbefore, contact zone 125 still is positioned at source area 103 and is centered around the bottom of contact hole 110, and contact is promoted district 126 between source area 103 and tagma 102, a part of zone in contact enhancement district 126 is positioned at source area 103 and contacts this contact zone 125, and its remaining another part is positioned at tagma 102.
If after completing the etching of contact hole 110 at every turn, all go in advance to measure its degree of depth, then just determine whether it is to carry out primary ions to inject (normal process of current techniques) also at execution twice Implantation (method that the present invention mentions), have no the doubt meeting and cause manufacturing process to become numerous and diverse nor be easy to improve output, this runs in the opposite direction with target of pursuing high UPH.The Cost Problems and the time delays that bring in order to avoid additionally going to survey the degree of depth of contact hole 110 as far as possible, a kind of optional execution mode just is, need not to know that contact hole 110 terminates in source area 103 or terminates in tagma 102, as long as after forming contact hole 110, the method for carrying out twice Implantation of aforementioned priority gets final product.
For example in some embodiments, etching dielectric layer 108, source area 103 and tagma 102, have the etching depth that extends in tagma 102 to contact hole 110 successively, makes its bottom be positioned at tagma 102, as Fig. 4 A～4C.After obtaining contact hole 110, to the interior dopant implant thing of Semiconductor substrate 150, form a contact zone with first degree of depth 125 that is centered around contact hole 110 bottoms by contact hole 110, only this moment, contact zone 125 was positioned at tagma 102.Again pass through contact hole 110 to the interior dopant implant thing of Semiconductor substrate 150 thereafter, form a contact with second degree of depth and promote district 126, this moment contact promote district 126 be positioned at contact zone 125 under, and it is adjacent or overlap with contact zone 125 that district 126 is promoted in contact, as Fig. 4 C, contact this moment is promoted district 126 and also is positioned at tagma 102.Better selection will contact within the degree of depth of promoting district 126 is limited in tagma 102, and doping does not enter in the epitaxial loayer 101 of 102 belows, tagma.similar with Fig. 3 A～3B, 126 sequentially not requirement of priority implantation is distinguished with contacting to promote in contact zone 125, terminate in the interior situation in tagma 102 as Fig. 5 A～5B for etching, can be by contact hole 110 to the interior dopant implant thing of Semiconductor substrate 150, first implant the contact with second degree of depth and promote district 126, thereafter just the dopant implant thing forms the contact zone 125 with first degree of depth, district 126 is promoted in abutting connection with contact in contact zone 125, contact zone 125 is positioned at tagma 102 and is centered around the bottom of contact hole 110, and the below that district 126 is positioned at tagma 102 and is positioned at contact zone 125 is promoted in contact.District's 126 ohmic contact that still can strengthen between connector 135 and tagma 102 are promoted in heavily doped contact zone 125, contact at this moment, improve conductivity.
Fig. 2 A～2D is that hypothesis contact hole 110 is very shallow, its bottom is away from the border between source area 103 and tagma 102 comparatively speaking, and Fig. 4 A～4C is that hypothesis contact hole 110 is very dark, its bottom is also away from the border between source area 103 and tagma 102 comparatively speaking, under these limiting cases, precondition is all to have larger distance between the hypothesis bottom of contact hole 110 and aforementioned border.As a comparison, Fig. 6 A～6C is all degree of depth that contact hole 110 has critical condition.In Fig. 6 A, etching terminates in source area 103, and but the bottom of contact hole 110 is in source area 103 very near the border between source area 103 and tagma 102; In Fig. 6 B, etching terminates in tagma 102, still very near the border between source area 103 and tagma 102, this moment, the distance between the bottom of contact hole 110 and aforementioned border was very little under these critical conditions in tagma 102 in the bottom of contact hole 110.In Fig. 6 C, another kind of situation is, etching just terminates in the upper surface in tagma 102, and the bottom of contact hole 110 correspondingly is positioned on the upper surface in tagma 102, namely the bottom of contact hole 110 be close to and source area 103 and tagma 102 between the border coplanar.Under these conditions, contact zone 125 is implanted between source area 103 and tagma 102, its part is positioned at source area 103 and another part is positioned at tagma 102, and contact is promoted that district 126 is implanted in tagma 102 and connected with described another part maintenance that contact zone 125 is positioned at tagma 102.Heavily doped contact zone 125 still plays the effect of strengthening the ohmic contact between connector 135 and tagma 102.
Although above content is as demonstration with N-type MOSFET, but this invention spirit is equally applicable to P type MOSFET, for example adopt heavily doped P+ type base substrate 100, the epitaxial loayer 101 of relatively lightly doped P-type, and the source area 103 of the tagma 102 of N-type and P+ type.If set epitaxial loayer 101, source area 103 is the first conduction type, tagma 102 be the second conduction type with the first conductivity type opposite, and contact zone 125, contact are promoted and distinguished 126 and be the second conduction type.When the first conduction type is N-type, when the second conduction type was the P type, the alloy that district 126 is promoted in contact was mainly the element that contains III family, such as one or more in B, BF, BF2, In.When the first conduction type is the P type, the second conduction type is N-type, and the contact alloy of promoting district 126 is mainly the element that contains V family, as one or more in P, As, Sb.
The present invention is based on existing technology basis, increases the contact hole doping process one, to guarantee in the certain limit of contact hole below and the tagma homotype of adulterating.Namely when the generating process deviation causes contact hole not penetrate the source region, because the existence in district is promoted in for example contact, make source region thin layer transoid that contact hole below do not penetrate for and the doping type of tagma homotype, thereby effectively solve a kind of common failure mechanism in the preparation of groove-type power MOS transistor technique, be that contact hole does not penetrate the source region and causes the Bvdss reduction of device and the negative bulk effect that Idss increases, to improve the handicraft product yield.
Above, by explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention has proposed existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents, all should think still to belong in the intent of the present invention and scope in claims scope.
Claims (16)
1. an its preparation process that prevents groove-type power MOS transistor bulk effect, is characterized in that, comprises the following steps:
A, provide semi-conductive substrate, comprise a base substrate and an epitaxial loayer of growth thereon, and form the tagma at the top of epitaxial loayer, and form groove and form grid in tagma and epitaxial loayer in groove;
B, form source area at the top in tagma and round groove;
C, form a dielectric layer on Semiconductor substrate, this dielectric layer is covered described grid simultaneously;
D, carry out etching in described dielectric layer, Semiconductor substrate, form and run through this dielectric layer and extend to contact hole in Semiconductor substrate;
E, utilize contact hole to implement alloy to implant, form the contact zone with first degree of depth that is centered around the contact hole bottom;
F, utilize contact hole to implement alloy to implant, form the contact with second degree of depth and promote the district;
Wherein second degree of depth is promoted the district with the contact zone adjacency or overlaps greater than first degree of depth and contact;
G, cover a metal barrier on the bottom of contact hole and sidewall and dielectric layer, and fill metal material form a metal plug in contact hole.
2. the method for claim 1, is characterized in that, described epitaxial loayer, source area are the first conduction type, and described tagma is the second conduction type with the first conductivity type opposite, and described contact zone, contact are promoted the district and be the second conduction type.
3. the method for claim 1, is characterized in that, described contact is promoted the doping content in district greater than the doping content of described source area.
4. the method for claim 1, is characterized in that, carries out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in source area, makes the bottom of described contact hole be positioned at source area.
5. method as claimed in claim 4, it is characterized in that, described contact zone is positioned at source area, and described contact is promoted the district and is positioned between described source area and tagma, its part is positioned at source area and keeps connecting or overlapping with described contact zone, and another part is positioned at the tagma.
6. method as claimed in claim 4, it is characterized in that, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.
7. the method for claim 1, is characterized in that, carries out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in the tagma, makes the bottom of described contact hole correspondingly be positioned at the tagma.
8. method as claimed in claim 7, it is characterized in that, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.
9. method as claimed in claim 7, is characterized in that, described contact zone is promoted the district and all is implanted in the tagma with described the contact.
10. the method for claim 1, is characterized in that, carries out in described dielectric layer, Semiconductor substrate in the step of etching, and etching terminates in the upper surface in tagma, and the bottom of described contact hole correspondingly is positioned on the upper surface in tagma.
11. method as claimed in claim 10, it is characterized in that, described contact zone is between described source area and tagma, its part is positioned at source area and another part is positioned at the tagma, and described contact is promoted the district and is positioned at described tagma and connects or overlap with described another part maintenance that the contact zone is positioned at the tagma.
12. the method for claim 1 is characterized in that, first execution in step e forms after the contact zone execution in step f again and forms contact and promote the district.
13. the method for claim 1 is characterized in that, first execution in step f formation contact enhancement is distinguished afterwards execution in step e again and is formed the contact zone.
14. method as claimed in claim 2 is characterized in that, described the first conduction type is N-type, and described the second conduction type is the P type, and the described contact alloy of promoting the district is one or more in B, BF, BF2, In.
15. method as claimed in claim 2 is characterized in that, described the first conduction type is the P type, and described the second conduction type is N-type, and the described contact alloy of promoting the district is one or more in P, As, Sb.
16. the method for claim 1 is characterized in that, the degree of depth that the district is promoted in described contact exists
Between.
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| CN111192829A (en) * | 2019-05-31 | 2020-05-22 | 深圳方正微电子有限公司 | Groove type VDMOS device and manufacturing method thereof |
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| US20020115244A1 (en) * | 2000-08-11 | 2002-08-22 | Sung-Bae Park | SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same |
| CN102130007A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) transistor |
| CN102201409A (en) * | 2010-03-24 | 2011-09-28 | 万国半导体(开曼)股份有限公司 | Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with tungsten spacing layer and production method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020115244A1 (en) * | 2000-08-11 | 2002-08-22 | Sung-Bae Park | SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same |
| CN102130007A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) transistor |
| CN102201409A (en) * | 2010-03-24 | 2011-09-28 | 万国半导体(开曼)股份有限公司 | Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with tungsten spacing layer and production method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111192829A (en) * | 2019-05-31 | 2020-05-22 | 深圳方正微电子有限公司 | Groove type VDMOS device and manufacturing method thereof |
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