CN103117215B - The formation method of metal gate electrode layer - Google Patents
The formation method of metal gate electrode layer Download PDFInfo
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- CN103117215B CN103117215B CN201110366102.1A CN201110366102A CN103117215B CN 103117215 B CN103117215 B CN 103117215B CN 201110366102 A CN201110366102 A CN 201110366102A CN 103117215 B CN103117215 B CN 103117215B
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Abstract
A formation method for metal gate electrode layer, comprising: provide substrate, and described substrate surface has polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer covering described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer; Interlayer dielectric layer described in planarization and etching barrier layer are until expose described polysilicon dummy gate layer; Remove described polysilicon dummy gate layer, form opening, and form projection at the sidewall of described open top; Form protective layer at described interlayer dielectric layer and etching barrier layer surface, full described opening filled by described protective layer; The described protective layer of flattened section thickness, described interlayer dielectric layer, etching barrier layer and side wall, until remove protruding; Remove described protective layer.The metal gate electrode layer quality that the formation method of the metal gate electrode layer of the embodiment of the present invention is formed is high.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of formation method of metal gate electrode layer.
Background technology
Along with integrated, the microminiaturized development of semiconductor device, electrical leakage quantity increases and the problem such as gate electrode layer loss to adopt material to be the gate dielectric layer of silicon dioxide and material to be the MOS device of the gate electrode layer of polysilicon to occur; For solving the above problems, the dielectric layer of hafnium and gate electrode layer (being called for short high-K metal gate, the HKMG) technique of metal material become the focus of research now.
The formation process of high-K metal gate can be divided into " front grid " technique, " rear grid " technique two kinds.Rear grid technique, can the premium properties of retainer member due to metal gate electrode layer can be avoided through high annealing, and be the comparatively main method forming metal gate at present, the rear grid technique of the formation process of high-K metal gate is specially:
First, provide substrate, described substrate surface has polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides;
Secondly, the etching barrier layer covering described polysilicon dummy gate layer and side wall is formed at described substrate surface;
Afterwards, interlayer dielectric layer is formed on described etching barrier layer surface;
Adopt interlayer dielectric layer and etching barrier layer described in flatening process planarization until expose described polysilicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening;
Form high-K dielectric layer in described open bottom, form the metal gate electrode layer of filling described opening on described high-K dielectric layer surface.
It is the formation process that can also find more HKMG in the U.S. patent documents of US2010/0081262A1 at publication number.
But, according to the device that existing technique is obtained, formed in the processing step of the metal gate electrode layer of filling described opening on described high-K dielectric layer surface, easily in metal gate electrode layer, space is formed, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
Summary of the invention
The present invention is utilizing prior art to manufacture in the process of high-K metal gate to solve, interstitial problem in metal gate electrode layer.
For solving the problem, the embodiment of the present invention provides a kind of method removing space in metal gate electrode layer, comprising: provide substrate, and described substrate surface has polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer covering described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer; Interlayer dielectric layer described in planarization and etching barrier layer are until expose described polysilicon dummy gate layer; Remove described polysilicon dummy gate layer, form opening, and form projection at the sidewall of described open top; Form protective layer at described interlayer dielectric layer and etching barrier layer surface, full described opening filled by described protective layer; The described protective layer of flattened section thickness, described interlayer dielectric layer, etching barrier layer and side wall, until remove protruding; Remove described protective layer.
Optionally, described protective layer material is photoresist.
Optionally, when described protective layer material is photoresist, the formation process of described protective layer is: thickness is 400 dust ~ 1500 dusts, and the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 DEG C.
Optionally, protruding technique is removed in planarization is the second CMP (Chemical Mechanical Polishing) process.
Optionally, the parameter of CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is silica or cerium oxide is main component, wherein, the particle size of silica abrasive liquid is 1 ~ 100nm, the particle size of cerium oxide abrasive liquid is 10 ~ 20nm, and the planarization rate Selection radio of lapping liquid to silica and silicon nitride of described second chemico-mechanical polishing is 0.5 ~ 2.
Optionally, the technique of interlayer dielectric layer described in planarization and etching barrier layer is the first CMP (Chemical Mechanical Polishing) process.
Optionally, the parameter of the first CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is silica or cerium oxide is main component, wherein, the particle size of silica abrasive liquid is 1 ~ 100nm, the particle size of cerium oxide abrasive liquid is 10 ~ 20nm, and the planarization rate Selection radio of lapping liquid to silica and silicon nitride of described first chemico-mechanical polishing is greater than 1.
Optionally, the technique removing described protective layer is dry method ashing method or wet method ashing method.
Optionally, also comprise: form gate dielectric layer in the bottom of described opening and be positioned at gate dielectric layer surface and the metal level of the full described opening of filling.
Optionally, described gate dielectric layer material is silica or high K medium, and high K medium comprises zirconia, hafnium oxide etc.
Optionally, metal level is single coating or multilayer lamination structure.
Optionally, when described metal level is single coating, described metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
Optionally, when described metal level is multilayer lamination structure, described metal level comprises: the function metal level being positioned at described gate dielectric layer surface, is positioned at the aluminum metal layer of described function layer on surface of metal.
Optionally, described function metal layer material is titanium nitride, nitrogenize thallium or tantalum nitride.
Compared with prior art, the present invention has the following advantages:
Adopt second time surface with chemical polishing technology to remove the polysilicon being formed in described open top madial wall protruding, make follow-uply can not form space when forming described metal gate electrode layer in described opening; The present embodiment is also before removal polysilicon projection; protective layer is adopted to fill full described opening; avoid in this second time chemico-mechanical polishing to remove in the technique of oxidise polysilicon projection; the extra madial wall at opening forms other protruding or residues again, improves the quality of the described metal level gate electrode layer of follow-up filling.
Further, described protective layer material is photoresist, can while available protecting opening, removes easy and can not damage the interface of opening.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view that existing technique forms high-K metal gate;
Fig. 5 is the process flow diagram that one embodiment of the invention forms metal gate;
Fig. 6 to Figure 12 is the cross-sectional view of the formation procedure of one embodiment of the invention metal gate electrode layer.
Embodiment
Inventor finds, in the formation process of existing high-K metal gate, is formed in the processing step of the metal gate electrode layer of filling described opening on described high-K gate dielectric layer surface, easily in metal gate electrode layer, form space, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
Inventor finds after further research, and high-K metal gate technique comprises the steps:
Please refer to Fig. 1, provide substrate 100, described substrate 100 surface has polysilicon dummy gate layer 101 and is positioned at the side wall 102 of polysilicon dummy gate layer 101 both sides; Described substrate 100 surface is formed with the etching barrier layer 103 covering described polysilicon dummy gate layer 101 and side wall 102, and described etching barrier layer 103 is silicon nitride; Described etching barrier layer 103 surface is formed with interlayer dielectric layer 104, and described interlayer dielectric layer is silica;
Please refer to Fig. 2, described in the planarization of employing flatening process, interlayer dielectric layer 104 and etching barrier layer 103 are until expose described polysilicon dummy gate layer 101, and described flatening process is CMP (Chemical Mechanical Polishing) process;
Please refer to Fig. 3, remove described polysilicon dummy gate layer 101, form opening 105; Described removal technique is dry etching or wet etching, and the top due to described opening 105 is the handing-over interface of described polysilicon dummy gate layer 101, side wall 102 and etching barrier layer 103; When adopting dry etching or wet etching to remove described polysilicon dummy gate layer 101, easily forming polycrystalline at described interface location, can be formed through snperoxiaized polysilicon projection 106 at the sidewall at the top of described opening 105;
Please refer to Fig. 4, bottom described opening 105, form high-K dielectric layer 107, form the metal gate electrode layer 108 of filling described opening 105 on described high-K dielectric layer 106 surface; It should be noted that, when forming the metal gate electrode layer 108 of filling described opening 105, in described metal gate electrode layer 108, usually there will be space 109.
Inventor furthers investigate discovery, described in metal gate electrode layer interstitial reason be: existing technique is in removal described polysilicon dummy gate layer after forming opening, the madial wall at the top of described opening can form oxidise polysilicon projection 106; Thus make the top of opening become narrow, when follow-up employing metal deposition process forms the metal gate electrode layer of filling described opening, having, protruding position fill rate is very fast, make not fill completely in opening and there is protruding position closed, thus form space in metal gate electrode layer inside, cause performance of semiconductor device to reduce, power consumption increases, and reliability reduces.
For this reason, the present inventor provides a kind of formation method of metal gate electrode layer, please refer to Fig. 5, comprises the steps:
Step S101, provides substrate, and described substrate surface has polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer covering described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer;
Step S102, interlayer dielectric layer described in planarization and etching barrier layer are until expose described polysilicon dummy gate layer;
Step S103, removes described polysilicon dummy gate layer, forms opening, and forms projection at the madial wall of described open top;
Step S104, form protective layer at described interlayer dielectric layer and etching barrier layer surface, full described opening filled by described protective layer;
Step S105, the described protective layer of flattened section thickness, described interlayer dielectric layer, etching barrier layer and side wall, until remove protruding;
Step S106, removes described protective layer;
Step S107, forms gate dielectric layer and is positioned at gate dielectric layer surface and the metal gate electrode layer of the full described opening of filling in the bottom of described opening.
Embodiments of the invention adopt flatening process to remove the projection being formed in the sidewall of described open top; avoid being formed with space in the metal level of subsequent technique filling; further; the present invention first forms the protective layer of filling full described opening; described protective layer can be avoided removing in planarization additionally in crowing technique forming projection at the sidewall of opening; the semiconductor device metal layer inside adopting the embodiment of the present invention to be formed does not have space; the device performance formed improves; power consumption reduces, and reliability improves.
Specifically describe below in conjunction with the formation method of specific embodiment to the metal gate electrode layer of the embodiment of the present invention.
Please refer to Fig. 6, provide substrate 200, described substrate 200 surface has polysilicon dummy gate layer 201 and is positioned at the side wall 202 of polysilicon dummy gate layer 201 both sides; Described substrate 200 surface is formed with the etching barrier layer 203 covering described polysilicon dummy gate layer 201 and side wall 202; Described etching barrier layer 203 surface is formed with interlayer dielectric layer 204.
Described substrate 200 effect is for follow-up formation semiconductor device provides workbench, and described substrate 200 material is the III-V etc. such as silicon (SOI) substrate, silicon nitrate substrate and GaAs on N-shaped silicon substrate, p-type silicon substrate, insulating barrier.
The material of described etching barrier layer 203 is silicon nitride, described interlayer dielectric layer 204 be silicon oxide layer.
The concrete formation process of described substrate 200, polysilicon dummy gate layer 201, side wall 202, etching barrier layer 203, interlayer dielectric layer 204 please refer to prior art, here repeats no more.
Please refer to Fig. 7, interlayer dielectric layer 204 described in planarization and etching barrier layer 203 are until expose described polysilicon dummy gate layer 201.
The technique of described planarization is the first CMP (Chemical Mechanical Polishing) process, particularly, described first CMP (Chemical Mechanical Polishing) process parameter is: the lapping liquid that chemico-mechanical polishing adopts is with silica or cerium oxide for main component, and the planarization rate Selection radio of described lapping liquid to silica and silicon nitride is greater than 1.
It should be noted that, the particle size of described silica abrasive liquid is 1 ~ 100nm, and the advantage of employing silica abrasive liquid is: active, the rear cleaning process of abrasive grains good dispersion, chemical property is easy to advantage.
It should be noted that, the particle size of described cerium oxide abrasive liquid is 10 ~ 20nm, adopts the advantage of cerium oxide abrasive liquid to be: have that polishing speed is high, material remove rate is high, the advantage less to the damage on polished surface.
Also it should be noted that, in the present embodiment, the material of interlayer dielectric layer 204 is silica, etching barrier layer 203 is silicon nitride, selects the lapping liquid of the first chemico-mechanical polishing can ensure to be removed together with silica interlayer dielectric layer 204 higher than the silicon nitride etch barrier layer 203 of polysilicon dummy gate layer to the technological parameter that silica and the Selection radio of silicon nitride are greater than 1.
Please refer to Fig. 8, remove described polysilicon dummy gate layer 201, form opening 205, and form protruding 206 at the madial wall at described opening 205 top.
The described technique removing projection 206 is dry etching or wet etching.
In one embodiment, described dry etching method adopts reactive ion etching method, and the gas of employing can select the mixture of chlorine, helium, hydrogen bromide or helium and oxygen.The advantage of dry etching is adopted to be that anisotropy, selectivity are good and etching efficiency is high.
In another embodiment, described wet etching selects tetramethyl ammonium hydroxide solution, and mass percent concentration is 2 ~ 4%, and temperature is 50 DEG C ~ 90 DEG C, and etch rate is 100 ~ 3000 A/min of clocks, and the speed ratio of etch polysilicon and silica is greater than 100: 1; Adopt the advantage of wet etching be easy and simple to handle, low for equipment requirements, be easy to produce in enormous quantities.
Described protruding 206 materials are oxides of polysilicon, particularly, the reason of the described formation of protruding 206 is: described opening 205 top is the interface location of described polysilicon dummy gate layer 201, side wall 202 and etching barrier layer 203, when adopting dry etching or wet etching to remove described polysilicon dummy gate layer 101, easily form polycrystalline at described interface location, remaining polysilicon exposes in atmosphere or can be oxidized, forms oxidized polysilicon projection 206 at the madial wall at opening 205 top.
Please refer to Fig. 9, form protective layer 207 at described interlayer dielectric layer 204 and etching barrier layer 203 surface, full described opening 205 filled by described protective layer 207.
Described protective layer 204, for protective opening 205 madial wall in the processing step of subsequent planarization removal protruding 206, is avoided forming extra residual packing at the sidewall of opening 205, open top size is diminished.
The material photoresist of described protective layer 207; particularly; the concrete technology parameter of coating photoresist is: thickness is 400 dust ~ 1500 dusts, and the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 DEG C; photoresist has following advantage as protective layer: be easy to film forming; be easy to remove, easy to use, corrosion stability is good; adhesiveness is high, fully can fill described opening 205 plays a protective role, and can not cause the infringement at opening interface.
Please refer to Figure 10, the described protective layer 207 of flattened section thickness, described interlayer dielectric layer 204, etching barrier layer 203 and side wall 202, until remove protruding 206.
The technique that projection 206 is removed in described planarization is the second CMP (Chemical Mechanical Polishing) process, particularly, the technological parameter of described second chemico-mechanical polishing is: the lapping liquid that chemico-mechanical polishing adopts with silica or cerium oxide for main component, particularly, silica abrasive liquid particle size is 1 ~ 100nm, the particle size of cerium oxide abrasive liquid is 10 ~ 20nm, and the planarization rate Selection radio of lapping liquid to silica and silicon nitride of described second chemico-mechanical polishing is 0.5 ~ 2.Adopt the second above-mentioned CMP (Chemical Mechanical Polishing) process parameter, in conjunction with the protective layer of photoresist, effectively can remove projection and additionally can not form other residue at opening sidewalls.
In the present embodiment, adopt second time surface with chemical polishing technology to remove the polysilicon projection 206 being formed in described opening 205 inside top wall, form space to avoid the inside of metal gate dielectric layer 209 as shown in figure 12 of filling at subsequent technique.Further; in the present embodiment; the previous photoresist protective layer 207 forming the full described opening 205 of filling, can avoid in this second time chemico-mechanical polishing to remove in the technique of oxidise polysilicon projection 206, the extra madial wall at opening forms protruding 206 again.
Please refer to Figure 11, remove described protective layer 207;
The effect of described removal protective layer 207 technique is the opening 205 forming top width increase, and the filling of the metal gate electrode layer as shown in figure 12 209 after making can not form space 109 as shown in Figure 4.
In one embodiment, when the material of protective layer 207 is photoresists, described removal technique is dry method ashing method or wet method ashing method, particularly, the gas that described dry method ashing method adopts can be, one or more in inert gas, air, nitrogen, oxygen, fluorocarbon gases and hydrocarbon gas, the advantage that dry method is removed photoresist be simple to operate, efficiency of removing photoresist is high, surface clean is bright and clean; Particularly, the solvent that removes photoresist of described wet method ashing method can be the mixed liquor of sulfuric acid and hydrogen peroxide, and the advantage that wet method is removed photoresist is that cost is low, output is high.
In another embodiment, when protective layer 207 material is silicon dioxide, described removal technique is coagulation desiliconization method, comprises magnesia mixture desiliconization, the desiliconization of aluminium salt, molysite desiliconization and lime desiliconization.
Please refer to Figure 12, form gate dielectric layer 208 in the bottom of described opening 205 and be positioned at gate dielectric layer 208 surface and the metal gate electrode layer 209 of the full described opening 205 of filling.
Described gate dielectric layer 208 is the effect of high-K gate dielectric layer is the appearance preventing leaky.
The material of described high-K gate dielectric layer 208 is hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc, and the formation process of described high-K gate dielectric layer 208 can be chemical vapour deposition technique or physical vapour deposition (PVD).
Described metal gate electrode layer 209 can be single coating or multilayer lamination structure.
In one embodiment, when described metal gate electrode layer 209 is single coating, described metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
In another embodiment, when described metal gate electrode layer 209 is multilayer lamination structure, described metal level comprises: the function metal level being positioned at described gate dielectric layer 208 surface, be positioned at the aluminum metal layer of described function layer on surface of metal, particularly, the effect of described function metal level be prevent after aluminum metal layer forming process in gather in opening 205 sidewall surfaces and cause opening to narrow, the material of described function metal level is titanium nitride, nitrogenize thallium or tantalum nitride.
The formation process of described metal gate electrode layer 209 is chemical vapour deposition (CVD) or physical vapour deposition (PVD), particularly, the forming step of described metal level 209 is: form described high-K gate dielectric layer at opening 205 bottom deposit, form described function metal level on high-K gate dielectric layer surface and opening 205 madial wall, finally form aluminum metal layer at described function layer on surface of metal.
The advantage of embodiments of the invention adopts second time surface with chemical polishing technology to remove the polysilicon projection 206 being formed in described opening 205 inside top wall, makes the follow-up space 109 that can not be formed during the described metal gate electrode layer 209 of formation in described opening 205 as shown in Figure 4; The present embodiment is also before removal polysilicon projection 206; protective layer 207 is adopted to fill full described opening 205; avoid in this second time chemico-mechanical polishing to remove in the technique of oxidise polysilicon projection 206; the extra madial wall at opening forms other protruding or residues again, improves the quality of the described metal level gate electrode layer 209 of follow-up filling.
Further, described protective layer 207 material is photoresist, can while available protecting opening, removes easy and can not damage the interface of opening 205.
Though the embodiment of the present invention is described above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for metal gate electrode layer, is characterized in that, comprising:
There is provided substrate, described substrate surface has polysilicon dummy gate layer and is positioned at the side wall of polysilicon dummy gate layer both sides; Described substrate surface is formed with the etching barrier layer covering described polysilicon dummy gate layer and side wall; Described etching barrier layer surface is formed with interlayer dielectric layer;
Interlayer dielectric layer described in planarization and etching barrier layer are until expose described polysilicon dummy gate layer;
Remove described polysilicon dummy gate layer, form opening, and form projection at the sidewall of described open top, described raised material is the oxide of polysilicon;
Form protective layer at described interlayer dielectric layer and etching barrier layer surface, full described opening filled by described protective layer;
The described protective layer of flattened section thickness, described interlayer dielectric layer, etching barrier layer and side wall, until remove protruding;
Remove described protective layer.
2. the formation method of metal gate electrode layer as claimed in claim 1, it is characterized in that, described protective layer material is photoresist.
3. the formation method of metal gate electrode layer as claimed in claim 1; it is characterized in that, when described protective layer material is photoresist, the formation process of described protective layer is: thickness is 400 dust ~ 1500 dusts; the speed of spin coating is 300-4000 rev/min, and the temperature of spin coating is 15-100 DEG C.
4. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, it is the second CMP (Chemical Mechanical Polishing) process that protruding technique is removed in planarization.
5. the formation method of metal gate electrode layer as claimed in claim 4, it is characterized in that, the parameter of CMP (Chemical Mechanical Polishing) process is: the lapping liquid of employing is silica or cerium oxide is main component, wherein, the particle size of silica abrasive liquid is 1 ~ 100nm, the particle size of cerium oxide abrasive liquid is 10 ~ 20nm, and the planarization rate Selection radio of lapping liquid to silica and silicon nitride of described second chemico-mechanical polishing is 0.5 ~ 2.
6. the formation method of metal gate electrode layer as claimed in claim 1, it is characterized in that, the technique of interlayer dielectric layer described in planarization and etching barrier layer is the first CMP (Chemical Mechanical Polishing) process.
7. the formation method of metal gate electrode layer as claimed in claim 6, it is characterized in that, the technological parameter of the first chemico-mechanical polishing is: the lapping liquid that chemico-mechanical polishing adopts is for main component with silica or cerium oxide, wherein, the particle size of silica abrasive liquid is 1 ~ 100nm, the particle size of cerium oxide abrasive liquid is 10 ~ 20nm, and the planarization rate Selection radio of lapping liquid to silica and silicon nitride of described first chemico-mechanical polishing is greater than 1.
8. the formation method of metal gate electrode layer as claimed in claim 1, it is characterized in that, the technique removing described protective layer is dry method ashing method or wet method ashing method.
9. the formation method of metal gate electrode layer as claimed in claim 1, is characterized in that, also comprise: form gate dielectric layer in the bottom of described opening and be positioned at gate dielectric layer surface and the metal level of the full described opening of filling.
10. the formation method of metal gate electrode layer as claimed in claim 9, it is characterized in that, described gate dielectric layer material is silica or high K medium, and high K medium comprises zirconia or hafnium oxide.
The formation method of 11. metal gate electrode layers as claimed in claim 9, it is characterized in that, metal level is single coating or multilayer lamination structure.
The formation method of 12. metal gate electrode layers as claimed in claim 11, it is characterized in that, when described metal level is single coating, described metal layer material is aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, titanium tungsten, nickel platinum, titanium nitride, nitrogenize thallium or tantalum nitride.
The formation method of 13. metal gate electrode layers as claimed in claim 11, it is characterized in that, when described metal level is multilayer lamination structure, described metal level comprises: the function metal level being positioned at described gate dielectric layer surface, is positioned at the aluminum metal layer of described function layer on surface of metal.
The formation method of 14. metal gate electrode layers as claimed in claim 13, is characterized in that, described function metal layer material is titanium nitride, nitrogenize thallium or tantalum nitride.
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