CN103116511A - Double-booting method based on single FLASH storage chip - Google Patents
Double-booting method based on single FLASH storage chip Download PDFInfo
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Abstract
The invention discloses a double-booting method based on a single FLASH storage chip. The double-booting method based on the single FLASH storage chip includes the following steps: a master BOOT and a backup BOOT are respectively stored on different positions of the storage chip, and an address wire of a central processing unit (CPU) is connected with an address wire of the storage chip through a complex programmable logic device (CPLD) logic module; a successful booting marker register is arranged on the CPLD logic module, and a corresponding setting is carried out by the successful booting marker register according to whether booting of the master BOOT or the backup BOOT is successful; round robin of the master BOOT and the backup BOOT is carried out by the CPLD logic module according to the state of the successful booting marker register, if booting is carried out by the master BOOT, address information of the CPU is transferred to the storage chip, and system booting is guided from the master BOOT; if booting is carried out by the backup BOOT, the corresponding address wire is locked according to the position of a backup BOOT program in a storer, and the system booting is guided from the backup BOOT. According to the double-booting method based on the single FLASH storage chip, a double-booting function is achieved by adopting only one storage chip, and the problems that a double-FLASH is high in cost, large in size and high in system energy consumption are solved.
Description
Technical field
The present invention relates to embedded system, be specifically related to the double startup method based on single FLASH storage chip.
Background technology
In embedded system, the BOOT program of equipment leaves the caudal end of FLASH storage chip usually in, starts and guidance system when being used for powering on.In case the BOOT routine data is damaged, system can't start, and this result is unacceptable to highly-reliable system.
In order to realize that highly-reliable system is to the requirement of BOOT start-up routine, the way of industry is to use two sheet choosings to connect two FLASH storage chips at present, when the BOOT on a FLASH storage chip breaks down, automatically select the BOOT that switches to another one FLASH storage chip to start system by sheet, strengthen the reliability of system with this.
But such scheme need to use two sheet choosings and two FLASH storage chips, and each FLASH storage chip is deposited respectively a BOOT start-up routine.There is following defective:
(1) not only increase cost, and increased the volume of the pcb board of embedded device, especially for some, embedded device volume and cost have been had the product of strict demand.
(2) sheet is selected the few processor of resource, use two sheet choosings can cause processor piece to select resource nervous, restricted to systematic lectotype, this also can restrict application and scope that two sheets select scheme.
Summary of the invention
Technical matters to be solved by this invention is to solve the problem that the embedded system cost is high, volume is large and system resources consumption is many that adopts two FLASH storage chip BOOT to start.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is to provide a kind of double startup method based on single FLASH storage chip, comprises the following steps:
Store respectively primary BOOT and standby BOOT on the diverse location of FLASH storage chip, the address wire of CPU is connected with the address wire of FLASH storage chip by the CPLD logic module;
The CPLD logic module is provided with and starts successful flag register, and described startup success flag register starts whether successfully carry out corresponding set according to primary BOOT or standby BOOT;
The CPLD logic module carries out primary BOOT according to the state of the successful flag register of described startup and standby BOOT wheel turns, if start from primary BOOT, cpu address information is passed through the FLASH storage chip, and starts from primary BOOT guidance system; If start from standby BOOT, corresponding address wire is pinned in the position in the FLASH storer according to standby BOOT program, and starts from standby BOOT guidance system.
In said method, also be provided with startup BOOT tick lables register on the CPLD logic module, system carries out BOOT software upgrading backup according to the state of the tick lables register of described startup BOOT.
In said method, after system starts successfully, cpu address information is passed through the FLASH storage chip, system power on or reset after be defaulted as from primary BOOT and start.
In said method, utilize the logic dog to make regular check on startup and successfully indicate.
In said method, the CPLD logic module is carried out primary BOOT and standby BOOT wheel according to the state that starts successful flag register and is subcontracted and draw together following steps:
Step 101, system power on or reset;
Whether step 102, enable logic dog are used for monitoring CPU and start successfully;
Step 103, read the startup BOOT tick lables on CPLD;
Step 104, determine whether to start from primary BOOT, if it is turn step 105; Otherwise turn step 111;
Step 105, CPLD logic module pass through the FLASH storage chip with processor address;
Step 106, start from primary BOOT guidance system;
Whether step 107, monitoring CPU start successfully, if system starts successfully, turn step 113; Otherwise turn step 108;
Whether step 108, decision logic dog be overtime, if overtime turn step 110; Otherwise, turn step 109;
Step 109, judged whether hard reset request, if having turn step 102; Otherwise turn step 110;
Step 110, resetting system, primary BOOT and standby BOOT wheel turn, if transferring to from standby BOOT, wheel starts, starting the BOOT tick lables is set to start from standby BOOT, if transferring to from standby BOOT, wheel starts, start the BOOT tick lables and be set to standby usage BOOT startup, turn step 103;
Step 111, determine whether to start from standby BOOT, if it is turn step 112; Otherwise output alarm starts and finishes;
Step 112, CPLD logic module are pinned corresponding address wire in the position in the FLASH storer according to standby BOOT program, and start from standby BOOT guidance system; Turn step 107;
Step 113, determine whether that primary BOOT starts successfully; If so, startup is set successfully is masked as primary BOOT and starts successfully, turn step 113, successfully be masked as standby BOOT and start successfully otherwise startup is set, turn step 114;
Step 114, CPLD pass through the FLASH storage chip with the address of processor;
Step 115, judged whether hard reset request, according to whether having the hardware reset request to handle it, if having turn step 102, otherwise closed the logic dog, system starting process is normally completed.
In said method, BOOT program upgrade and backup comprise the following steps:
Corresponding startup BOOT tick lables after starting successfully, step 201, BOOT is set;
Step 202, determine whether that according to starting the BOOT tick lables primary BOOT starts, successfully turn step 203 if primary BOOT starts, successfully turn step 205 if standby BOOT starts, otherwise also end of output alarm;
Step 203, judge whether primary BOOT satisfies automatic local upgrade condition, if satisfy turn step 204, otherwise turn step 205;
Step 204, judge whether primary BOOT is consistent with program to be upgraded, if both consistent explanation does not need upgrading, turn step 210; Otherwise upgrade primary BOOT and resetting system;
Step 205, repair primary BOOT;
Step 206, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise turn step 207;
Step 207, start the operating system;
Step 208, judge whether the guiding from primary BOOT, if it is stop the logic dog, turn step 210, otherwise turn step 209;
Step 209, judge whether the guiding from standby BOOT, if it is turn step 210, otherwise report to the police, finish upgrading and backup flow process;
Step 210, repair primary BOOT, turn step 212;
Step 211, judge whether primary BOOT is consistent with standby BOOT, if unanimously finish upgrading and backup flow process, otherwise upgrade standby BOOT, finish upgrading and backup flow process, if upgrade standby rear active and standby inconsistently, output alarm, finish upgrading and backup flow process; If active and standby BOOT unanimously finishes upgrading and backup flow process;
Step 212, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise output alarm finishes upgrading and backup flow process.
The present invention only adopts a slice FLASH storage chip to realize the double startup function, has solved to use two FLASH to realize the problem that cost is high, volume is large and system resources consumption is many that the double startup scheme has; And on the basis that does not increase hardware cost, solved the problem of the poor reliability of single startup scheme commonly used.
Description of drawings
Fig. 1 is the double startup hardware configuration schematic diagram of single FLASH storage chip in the present invention;
Fig. 2 is method flow diagram provided by the invention;
Fig. 3 is BOOT program upgrade and backup process flow diagram in method provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is made detailed explanation.
As shown in Figure 1, in double startup implementation method based on single FLASH storage chip provided by the invention, store respectively primary BOOT and the general practice of standby BOOT(is the afterbody that is stored in the FLASH storage chip on the diverse location of FLASH storage chip), the address wire of CPU is connected with the address wire of FLASH storage chip by the CPLD logic module.The CPLD logic module realizes two kinds of functions, the one, cpu address information is passed through the FLASH storage chip, to realize starting (under default situations) from primary BOOT guidance system, the 2nd, corresponding address wire is pinned in the position according to standby BOOT program in the FLASH storer, to realize starting (when primary BOOT guides unsuccessfully, taking turns when being changed to standby BOOT) from standby BOOT guidance system.The CPLD logic module is provided with two flag registers: start and successfully indicate and start the BOOT tick lables, wherein, start and successfully indicate readable writing, be set to after BOOT successfully starts effectively, CPLD judges that according to this sign system starts whether success and whether needs start switching; It is read-only starting the BOOT tick lables, is used to refer to location, lock residence, and simultaneously, this sign also is used for BOOT software upgrading backup, and system carries out BOOT software upgrading backup according to the state of the tick lables register that starts BOOT.
As shown in Figure 2, above-mentioned double startup method based on single FLASH storage chip comprises the following steps:
Step 101, system power on or reset;
Whether step 102, enable logic dog are used for monitoring CPU and start successfully;
Step 103, read the startup BOOT tick lables on CPLD;
Step 104, determine whether to start from primary BOOT, if it is turn step 105; Otherwise turn step 111;
Step 105, CPLD logic module pass through the FLASH storage chip with processor address;
Step 106, start from primary BOOT guidance system;
Step 107, utilize the logic dog to make regular check on startup successfully to indicate, whether monitoring CPU starts successfully, if system starts successfully, turns step 113; Otherwise turn step 108;
Whether step 108, decision logic dog overtime (the overtime time limit of setting in present embodiment is 10 seconds, time limit value can arrange flexibly according to system's needs), if overtime turn step 110; Otherwise, turn step 109;
Step 109, judged whether hard reset request, if having turn step 102; Otherwise turn step 110;
Step 110, the CPLD output reset level whole system that resets, and turn according to the table tennis algorithm primary BOOT of startup and standby BOOT wheel, select a BOOT to start, the table tennis algorithm is algorithm commonly used in the CPLD programming in logic, can circulate by this algorithm and generate 0 and 1, according to 0 and 1 just can be corresponding the primary BOOT of selection and standby BOOT, if transferring to from standby BOOT, wheel starts, starting the BOOT tick lables is set to start from standby BOOT, start if wheel transfers to from standby BOOT, start the BOOT tick lables and be set to standby usage BOOT startup; Turn step 103;
Step 111, determine whether to start from standby BOOT, if it is turn step 112; Otherwise output alarm starts and finishes;
Step 112, CPLD logic module are pinned corresponding address wire (can lock as required one or more address wires) in the position in the FLASH storer according to standby BOOT program, and start from standby BOOT guidance system; Turn step 107;
Step 113, determine whether that primary BOOT starts successfully; If so, startup is set successfully is masked as primary BOOT and starts successfully, turn step 113, successfully be masked as standby BOOT and start successfully otherwise startup is set, turn step 114;
Step 114, CPLD pass through the FLASH storage chip with the address of processor;
Step 115, judged whether hard reset request, according to whether having the hardware reset request to handle it, if having turn step 102, otherwise closed the logic dog, system starting process is normally completed.
After system started successfully, CPLD must pass through processor address the FLASH storage chip, otherwise can cause operation chaotic.
As shown in Figure 3, in above-mentioned double startup method based on single FLASH storage chip, BOOT program upgrade and backup comprise the following steps:
Step 201, system power on or reset, and corresponding startup BOOT tick lables is set after BOOT starts successfully;
Step 202, be that primary BOOT starts successfully or standby BOOT starts successfully according to starting the judgement of BOOT tick lables, if starting, primary BOOT successfully turns step 203, if starting, standby BOOT successfully turns step 205, otherwise output alarm and end;
Step 203, judge whether primary BOOT satisfies automatic local upgrade condition, if satisfy turn step 204, otherwise turn step 207;
Step 204, judge whether primary BOOT is consistent with program to be upgraded, if both consistent explanation does not need upgrading, turn step 207; Otherwise upgrade primary BOOT and resetting system;
Step 205, repair primary BOOT;
Step 206, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise turn step 207;
Step 207, start the operating system;
Step 208, judge whether the guiding from primary BOOT, if it is stop the logic dog, turn step 212, otherwise turn step 209;
Step 209, judge whether the guiding from standby BOOT, if it is turn step 210, otherwise report to the police, finish upgrading and backup flow process;
Step 210, repair primary BOOT, turn step 211;
Step 211, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise report to the police, finish upgrading and backup flow process;
Step 212, judge whether primary BOOT is consistent with standby BOOT, if unanimously upgrading and Backup end, otherwise upgrade standby BOOT, upgrading and Backup end, if upgrade standby rear active and standby inconsistently, output alarm, finish upgrading and backup flow process.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, within all falling into protection scope of the present invention.
Claims (6)
1. based on the double startup method of single FLASH storage chip, it is characterized in that, comprise the following steps:
Store respectively primary BOOT and standby BOOT on the diverse location of FLASH storage chip, the address wire of CPU is connected with the address wire of FLASH storage chip by the CPLD logic module;
The CPLD logic module is provided with and starts successful flag register, and described startup success flag register starts whether successfully carry out corresponding set according to primary BOOT or standby BOOT;
The CPLD logic module carries out primary BOOT according to the state of the successful flag register of described startup and standby BOOT wheel turns, if need to start from primary BOOT, cpu address information is passed through the FLASH storage chip, and start from primary BOOT guidance system; If need to start from standby BOOT, corresponding address wire is pinned in the position in the FLASH storer according to standby BOOT program, and starts from standby BOOT guidance system.
2. the double startup method based on single FLASH storage chip as claimed in claim 1, it is characterized in that, also be provided with startup BOOT tick lables register on the CPLD logic module, system carries out BOOT software upgrading backup according to the state of the tick lables register of described startup BOOT.
3. the double startup method based on single FLASH storage chip as claimed in claim 1, is characterized in that, after system starts successfully, cpu address information passed through the FLASH storage chip, system power on or reset after be defaulted as from primary BOOT and start.
4. the double startup method based on single FLASH storage chip as claimed in claim 1, is characterized in that, utilizes the logic dog to make regular check on startup and successfully indicate.
5. the double startup method based on single FLASH storage chip as claimed in claim 1, is characterized in that, the CPLD logic module is carried out primary BOOT and standby BOOT wheel according to the state that starts successful flag register and subcontracted and draw together following steps:
Step 101, system power on or reset;
Whether step 102, enable logic dog are used for monitoring CPU and start successfully;
Step 103, read the startup BOOT tick lables on CPLD;
Step 104, determine whether to start from primary BOOT, if it is turn step 105; Otherwise turn step 111;
Step 105, CPLD logic module pass through the FLASH storage chip with processor address;
Step 106, start from primary BOOT guidance system;
Whether step 107, monitoring CPU start successfully, if system starts successfully, turn step 113; Otherwise turn step 108;
Whether step 108, decision logic dog be overtime, if overtime turn step 110; Otherwise, turn step 109;
Step 109, judged whether hard reset request, if having turn step 102; Otherwise turn step 110;
Step 110, resetting system, primary BOOT and standby BOOT wheel turn, if transferring to from standby BOOT, wheel starts, starting the BOOT tick lables is set to start from standby BOOT, if transferring to from standby BOOT, wheel starts, start the BOOT tick lables and be set to standby usage BOOT startup, turn step 103;
Step 111, determine whether to start from standby BOOT, if it is turn step 112; Otherwise output alarm starts and finishes;
Step 112, CPLD logic module are pinned corresponding address wire in the position in the FLASH storer according to standby BOOT program, and start from standby BOOT guidance system; Turn step 107;
Step 113, determine whether that primary BOOT starts successfully; If so, startup is set successfully is masked as primary BOOT and starts successfully, turn step 113, successfully be masked as standby BOOT and start successfully otherwise startup is set, turn step 114;
Step 114, CPLD pass through the FLASH storage chip with the address of processor;
Step 115, judged whether hard reset request, according to whether having the hardware reset request to handle it, if having turn step 102, otherwise closed the logic dog, system starting process is normally completed.
6. the double startup method based on single FLASH storage chip as claimed in claim 1, is characterized in that, BOOT program upgrade and backup comprise the following steps:
Step 201, system power on or reset, and corresponding startup BOOT tick lables is set after BOOT starts successfully;
Step 202, be that primary BOOT starts successfully or standby BOOT starts successfully according to starting the judgement of BOOT tick lables, if starting, primary BOOT successfully turns step 203, if starting, standby BOOT successfully turns step 205, otherwise output alarm and end;
Step 203, judge whether primary BOOT satisfies automatic local upgrade condition, if satisfy turn step 204, otherwise turn step 207;
Step 204, judge whether primary BOOT is consistent with program to be upgraded, if both consistent explanation does not need upgrading, turn step 207; Otherwise upgrade primary BOOT and resetting system;
Step 205, repair primary BOOT;
Step 206, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise turn step 207;
Step 207, start the operating system;
Step 208, judge whether the guiding from primary BOOT, if it is stop the logic dog, turn step 212, otherwise turn step 209;
Step 209, judge whether the guiding from standby BOOT, if it is turn step 210, otherwise report to the police, finish upgrading and backup flow process;
Step 210, repair primary BOOT, turn step 211;
Step 211, judge whether primary BOOT repairs successfully, if repair successfully, resetting system; Otherwise report to the police, finish upgrading and backup flow process;
Step 212, judge whether primary BOOT is consistent with standby BOOT, if unanimously upgrading and Backup end, otherwise upgrade standby BOOT, upgrading and Backup end, if upgrade standby rear active and standby inconsistently, output alarm, finish upgrading and backup flow process.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104035776A (en) * | 2014-06-23 | 2014-09-10 | 成都万维图新信息技术有限公司 | Operating system starting method |
| WO2015154538A1 (en) * | 2014-07-08 | 2015-10-15 | 中兴通讯股份有限公司 | Memory booting method and device |
| CN105677414A (en) * | 2016-01-06 | 2016-06-15 | 无锡中太服务器有限公司 | Method for achieving dual boot in Hostboot |
| CN105938445A (en) * | 2015-07-31 | 2016-09-14 | 杭州迪普科技有限公司 | Data backup method and device |
| CN106325940A (en) * | 2016-08-26 | 2017-01-11 | 天津市英贝特航天科技有限公司 | FLASH memory segmented intelligent starting module |
| WO2017143513A1 (en) * | 2016-02-23 | 2017-08-31 | 华为技术有限公司 | Method, cpu and single board for starting boot |
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| CN110597671A (en) * | 2019-08-23 | 2019-12-20 | 深圳震有科技股份有限公司 | FLASH chip with independent BOOT area, system and method |
| CN111338771A (en) * | 2020-02-13 | 2020-06-26 | 深圳震有科技股份有限公司 | Boot program switching processing method and device, computer equipment and medium |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1960434A (en) * | 2006-11-16 | 2007-05-09 | 深圳创维－Rgb电子有限公司 | Method, devices, and facility for implementing upgrading TV system |
| CN101131649A (en) * | 2006-08-23 | 2008-02-27 | 乐金电子（昆山）电脑有限公司 | Updating speed improving method for read-only memory of device with flash memory |
| CN101315605A (en) * | 2008-06-26 | 2008-12-03 | 四川长虹电器股份有限公司 | Automatic upgrading method of panel TV software based on USB port |
| CN101329632A (en) * | 2008-04-30 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for starting CPU by BOOT |
| CN101616018A (en) * | 2008-06-27 | 2009-12-30 | 中兴通讯股份有限公司 | The method of upgrading network management software and device |
| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| CN102137154A (en) * | 2011-02-23 | 2011-07-27 | 华为终端有限公司 | Method and device for upgrading customer premise equipment (CPE) |
| CN102662749A (en) * | 2012-03-23 | 2012-09-12 | 中兴通讯股份有限公司 | Method and device for realizing switching between dual Boots |
-
2013
- 2013-01-29 CN CN2013100344584A patent/CN103116511A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131649A (en) * | 2006-08-23 | 2008-02-27 | 乐金电子（昆山）电脑有限公司 | Updating speed improving method for read-only memory of device with flash memory |
| CN1960434A (en) * | 2006-11-16 | 2007-05-09 | 深圳创维－Rgb电子有限公司 | Method, devices, and facility for implementing upgrading TV system |
| CN101329632A (en) * | 2008-04-30 | 2008-12-24 | 中兴通讯股份有限公司 | Method and apparatus for starting CPU by BOOT |
| CN101315605A (en) * | 2008-06-26 | 2008-12-03 | 四川长虹电器股份有限公司 | Automatic upgrading method of panel TV software based on USB port |
| CN101616018A (en) * | 2008-06-27 | 2009-12-30 | 中兴通讯股份有限公司 | The method of upgrading network management software and device |
| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| CN102137154A (en) * | 2011-02-23 | 2011-07-27 | 华为终端有限公司 | Method and device for upgrading customer premise equipment (CPE) |
| CN102662749A (en) * | 2012-03-23 | 2012-09-12 | 中兴通讯股份有限公司 | Method and device for realizing switching between dual Boots |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035776B (en) * | 2014-06-23 | 2017-05-17 | 成都万维图新信息技术有限公司 | Operating system starting method |
| CN104035776A (en) * | 2014-06-23 | 2014-09-10 | 成都万维图新信息技术有限公司 | Operating system starting method |
| WO2015154538A1 (en) * | 2014-07-08 | 2015-10-15 | 中兴通讯股份有限公司 | Memory booting method and device |
| CN105320529A (en) * | 2014-07-08 | 2016-02-10 | 中兴通讯股份有限公司 | Boot method and device based on NAND-Flash double-boot guidance |
| CN105938445A (en) * | 2015-07-31 | 2016-09-14 | 杭州迪普科技有限公司 | Data backup method and device |
| CN105938445B (en) * | 2015-07-31 | 2019-09-06 | 杭州迪普科技股份有限公司 | Data back up method and device |
| CN105677414A (en) * | 2016-01-06 | 2016-06-15 | 无锡中太服务器有限公司 | Method for achieving dual boot in Hostboot |
| WO2017143513A1 (en) * | 2016-02-23 | 2017-08-31 | 华为技术有限公司 | Method, cpu and single board for starting boot |
| CN108701036A (en) * | 2016-02-23 | 2018-10-23 | 华为技术有限公司 | A kind of method, CPU and veneer starting Boot |
| CN106325940A (en) * | 2016-08-26 | 2017-01-11 | 天津市英贝特航天科技有限公司 | FLASH memory segmented intelligent starting module |
| CN107704258A (en) * | 2017-10-27 | 2018-02-16 | 深圳市恒扬数据股份有限公司 | Uboot upgrade methods, system and terminal device |
| CN109558176A (en) * | 2018-11-30 | 2019-04-02 | 郑州云海信息技术有限公司 | A kind of double Qi Fangfa based on Flash inside CPLD |
| CN110597671A (en) * | 2019-08-23 | 2019-12-20 | 深圳震有科技股份有限公司 | FLASH chip with independent BOOT area, system and method |
| CN111338771A (en) * | 2020-02-13 | 2020-06-26 | 深圳震有科技股份有限公司 | Boot program switching processing method and device, computer equipment and medium |
| CN113032026A (en) * | 2021-03-19 | 2021-06-25 | 山东英信计算机技术有限公司 | Firmware management method, device, equipment and medium for server mainboard |
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Application publication date: 20130522 |