WO2017143513A1

WO2017143513A1 - Method, cpu and single board for starting boot

Info

Publication number: WO2017143513A1
Application number: PCT/CN2016/074331
Authority: WO
Inventors: 徐炜
Original assignee: 华为技术有限公司
Priority date: 2016-02-23
Filing date: 2016-02-23
Publication date: 2017-08-31
Also published as: CN108701036A

Abstract

The present invention relates to the field of computers. Disclosed are a method, a CPU and a single board for starting Boot, which may improve the Boot start reliability. The specific solution is as follows: the CPU is installed on the single board, and the single board includes a memory, the memory containing at least two guide Boot backups. In the at least two Boot backups, an offset address of two adjacent backups has a preset value, wherein the offset address is the interval between the starting addresses of two adjacent Boot backups. The CPU determines the offset address and according to the offset address, starts the at least two Boot backups one by one and in a preset order until one Boot backup starts successfully. The present invention is applicable to the manufacturing of CPU and single boards.

Description

Method for starting boot, CPU and board

Technical field

The present invention relates to the field of computers, and in particular, to a method, a CPU, and a board for booting a boot.

Background technique

A board with certain calculation and processing functions is installed in many electronic devices, for example, base stations in the field of wireless communication and various signal control devices in other network elements and in the field of rail transit, and various customized functions are installed. The veneer. A board usually includes a central processing unit (Central Processing Unit, CPU for short) and a memory. The memory can be a non-volatile memory (for a non-volatile memory). The bootloader (full name: Boot) code, etc.

To ensure that the board starts normally, you can back up the Boot. When a boot backup fails, try to start another boot backup. In a prior art solution, the Boot includes two backups. As shown in Figure 1, the two backups are Level 1 BootRom (L1BootRom for short) and Level 2 BootRom (L2BootRom for short). L1BootRom and L2BootRom are two backups of the same version or different versions. For example, two are the latest version of Boot backup, or one of them is the latest version of Boot backup, and the other is the factory version backup. L1BootRom includes Bootstrap, which is located at the beginning of L1BootRom. After the CPU is powered on, it first loads Bootstrap to complete the simplest initialization and start jump judgment.

In conjunction with the execution flow shown by the solid arrow in Figure 1, after the CPU is powered on, it starts from the start address of L1BootRom. After the Bootstrap part is executed, it jumps to the start address of L2BootRom and starts to execute. Try to start the L2BootRom backup. If the L2BootRom backup fails, the board fails to start. The CPU resets and restarts from L1BootRom to the L2BootRom backup. Try to start the L2BootRom backup again.

In conjunction with the execution flow shown by the dotted arrow in FIG. 1, when the BootStrap is executed again, the BootStrap determines the number of failed L2BootRom backups, and if it reaches the predetermined number of times, it jumps to the L1BootRom backup. Therefore, if the L2BootRom backup fails to be started, the board can also start the L1BootRom backup to complete the board startup.

Further, BootRom can have more than two backups. At startup, try one of them first, and try another one when the failure condition is met. However, if there is an error in the code of the Bootstrap segment in the L1BootRom backup, the L1BootRom backup cannot complete the jump and the count. In this case, even if there are more Boot backups, the Boot will fail and the board will fail to start. . Therefore, the method for starting the Boot in the prior art is insufficient in reliability, which may cause the board to fail to start.

Summary of the invention

The present invention provides a method for starting a boot, a CPU, and a board, which can improve the reliability of boot startup.

To achieve the above objectives, the present application adopts the following technical solutions:

In a first aspect, a method for booting a boot is provided, which is applied to a CPU, and the CPU is installed on a single board.

The CPU includes on-chip boot logic, and the on-chip boot logic defines the number of boot backups, the offset address, and the order in which the boot backup is attempted. The number of Boot backups is greater than or equal to 2. The offset address is the interval between the start addresses of two adjacent Boot backups.

The board includes a memory, a board developer or a manufacturer, and stores a Boot backup in the memory according to the number of Boot backups supported by the CPU and the offset address.

The method for the CPU to execute the booting by using the on-chip booting logic specifically includes: determining the offset address; and starting the at least two boot backups according to an offset address one by one according to a preset sequence until there is a boot The backup was successfully started. That is to say, the CPU starts the boot backup one by one in the order defined by the on-chip boot logic. If a boot backup fails, an attempt is made to start another boot backup. The booting of each boot backup has no effect on each other, thus overcoming the problem that another boot backup cannot be started because one boot backup fails, so that at least two boot backups can be guaranteed as long as one backup can be started normally. Startup, which improves the reliability of boot startup.

With reference to the first aspect, in a possible implementation, the offset address is determined according to a pre-configured hardware indication signal, and the first address accessed by the CPU may be a zero address during the boot process. Or, the first address accessed by the CPU can be a non-zero address, when If the Boot backup of the non-zero address fails to start, try to start the Boot backup corresponding to the 0 address.

In combination with the first aspect, in a common startup boot scenario, you can directly try to start a Boot backup, or try to start the Boot backup after verifying.

In combination with the first aspect, in the application scenario of the secure booting boot, after a boot backup is digitally signed and verified, the boot backup is attempted.

In a second aspect, a CPU is provided, the CPU including on-chip boot logic. After the CPU is powered on, the method of booting the Boots provided by the first aspect is performed by the on-chip boot logic.

With reference to the second aspect, in a first possible implementation, the CPU includes: a determining unit and a boot startup control unit, wherein the determining unit is configured to determine the offset address, and the boot startup control unit is configured to follow a preset sequence The at least two boot backups are started according to the offset address one by one until a boot backup is successfully started.

In a third aspect, a board is provided, where the board includes a CPU and a memory, wherein the CPU is a CPU provided by the second aspect, and the memory stores at least two boot backups. The CPU starts the boot and further starts the operating system and application software of the board by executing the booting method provided by the first aspect.

DRAWINGS

1 is a schematic flowchart of starting a boot backup in the prior art;

2 is a schematic flowchart of a method for starting a boot according to an embodiment of the present invention;

3 is a schematic structural diagram of a CPU according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a single board according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

During the board startup process, you need to start the boot and the operating system. Boot may be tampered with or bit hopping in some cases, resulting in an error in the Boot code. For example, in a wireless communication system, a function board in a base station may be invaded and maliciously tampered with. Or, due to the voltage jump of the board, aging of the device, etc., some bits in the Boot may jump.

An error in the key position of the Boot code may cause the Boot to fail to start and further cause the board to fail to start. After the Boot is backed up, you can try to start another Boot backup to ensure that the board starts normally. However, as long as there is a Boot backup, it can be foolproof. In the prior art, when Boot is started, even if there is a bug in the Boot backup code, it can be started normally, and the boot startup may fail because it cannot be jumped to the backup. The object of the present invention is to provide a method for starting a boot, a CPU, and a board to overcome the problem that a Boot backup cannot be started due to a boot failure of a boot backup, so as to ensure that only one boot backup can be started normally. Boot is started to improve the reliability of boot startup.

Embodiment 1

A first embodiment of the present invention provides a method for booting a boot, which is applied to a CPU. The CPU includes on-chip boot logic. The on-chip boot logic may be an on-chip hardware circuit, or may be an on-chip boot code, or both. Combination of. After the CPU is powered on, the method for booting the boot is performed by using the on-chip boot logic. Referring to FIG. 2, the method for booting includes the following steps:

201. Determine an offset address.

The CPU is installed on a board. The board includes a memory, and the memory is a non-volatile memory, such as a flash memory (full name: flash memory). At least two boot backups are stored in the memory.

On-chip boot logic supports reading the backup code from two or more power-up locations. The power-on position is the starting address of the code that reads the Boot backup when the on-chip boot logic starts running. A power-on location corresponds to a Boot backup. Different Boot backup codes are read from different power-on locations to start different Boot backups.

The size of the address interval between two power-on positions adjacent to the on-chip boot logic is an offset address. In at least two boot backups stored in the memory, the interval between the start addresses of the adjacent two boot backups is also an offset address. That is to say, when a boot backup fails, the on-chip boot logic jumps to another boot backup and attempts to start another boot backup. A Boot Backup failed to start, including not executing the Boot Reserve. An exception occurred during the execution of the boot backup, and the boot backup did not start successfully. It can be understood that the offset address may be one or multiple, which may be determined by actual coefficient design requirements. For example, the interval between the first boot backup and the second boot backup is X, and the interval between the second boot backup and the third boot backup is X+1, ... the n-1th boot backup. The size of the interval between the nth boot backup and the nth boot backup is X+n-2, or other predetermined rules for the change of the interval size, and details are not described herein.

For example, the Boot backup is checked for correctness before the Boot backup is started. If the Boot backup is not started after the verification is not performed, the Boot backup fails. The correctness check is to verify whether the content of the boot backup is strictly correct, including hash value check or cyclic redundancy check. If the bit jumps, the Boot backup cannot pass the correctness check.

Or, after the correctness check is performed, the boot backup is started. If the boot backup does not start normally, the boot backup fails.

Or, if the backup is not properly verified, the Boot backup is started. The boot backup fails because the exception occurs during the execution.

After the CPU is powered on, the on-chip boot logic starts the Boot backup corresponding to the first power-on position. If the boot backup fails, the on-chip boot logic jumps from the first power-on position to the first time after the CPU resets. At the two power-on positions, try to start the Boot backup corresponding to the second power-on position. It should be specially noted that the Boot backup corresponding to the first power-on location (the first access boot backup) may have a starting address of 0 or 0, depending on the attempt defined by the on-chip boot logic. The order of startup.

Before the on-chip boot logic is used to jump, it is first necessary to determine the specific value of the offset address. In this embodiment, two specific methods for determining the offset address are provided as follows:

In the first mode, after the CPU is powered on, the on-chip boot logic reads the offset address from the flash. Or further, the on-chip boot logic can read the start address of each boot backup from flash so that the developer can customize the offset address or the start address.

In the second mode, after the CPU is powered on, the offset is determined according to the pre-configured hardware indication signal. address. In a specific application scenario, the number of power-on locations, the size of the offset address, and the order in which the boot backup is attempted are all defined by the on-chip boot logic.

For example, the on-chip boot logic defines at least two alternate offset addresses, the number of alternate offset addresses being the number of power-up locations. For example, in the case where the number of alternative offset addresses is 2, the values of the two alternative offset addresses are 2 megabytes and 4 megabytes, respectively. The CPU is provided with a pin for indicating an offset address, and is used for receiving a hardware indication signal input by the board, such as a pull-up corresponding to 2 megabytes and a pull-down corresponding to 4 megabytes. The board designer selects one of the 2 megabits or 4 megabytes as the offset address according to actual needs, stores 2 Boot backups in the memory according to the value of the selected offset address, and configures corresponding hardware instructions. signal. For example, if the size of the Boot backup is between 2 megabytes and 4 megabytes, the value of the offset address is 4 megabytes. When two Boot backups are written to the memory, the starting address of the first boot backup is 0. The second boot backup start address takes 1 x 4 megabytes. At the same time, the board will configure an input signal that will indicate the pin of the offset address. After the CPU is powered on, the board inputs a pre-configured hardware indication signal to the pin, and the on-chip startup logic reads the pre-configured hardware indication signal from the pin, and determines the offset address according to the hardware indication signal.

Of course, depending on the number of power-on positions, the number of pins used to indicate the offset address is also different. For example, if the number of power-on positions is 4, the number of candidate offset addresses is 4, and 2 pins are needed to indicate which of the 4 candidate offset addresses is the offset address.

In addition, when there are more than one pin for indicating the offset address, a binary code indicating the value of the offset address can be directly input to the pin. For example, if the number of pins is 10, the board directly inputs a 10-bit binary code to 10 pins to indicate the value of the offset address. For example, the 10 pin inputs are all 1, which means that the offset address takes the value of 2 to the power of 10, which is 1024 megabytes.

Alternatively, an erasable editable logic device (full name: Erasable Programmable Logic Device, EPLD) is set on the periphery of the CPU. The pre-configured hardware indication signal can be a fixed register value in the EPLD, and the on-chip boot logic is read in the EPLD. A fixed register value determines the offset address.

202. Start at least two boot backups according to the offset address one by one according to a preset sequence, until one boot backup succeeds.

After the CPU is powered on, the on-chip boot logic starts running. The on-chip boot logic determines the offset address through the CPU pre-configured hardware indication signal, and then starts the Boot backup in the memory one by one in a preset order until a Boot backup is successfully started. The number of power-on positions, the size of the offset address, and the order in which the boot backup is attempted are all defined by the on-chip boot logic. In the embodiment of the present invention, the preset order is defined by the on-chip boot logic. Boot backup attempts to start the order one by one. For example, the number of Boot backups is three, and the numbers 1, 2, and 3 respectively represent the respective start addresses of the three power-on positions, and the start address corresponding to the number 1 is the 0 address. The first power-on position after the CPU is powered on may be any one of the three power-on positions, and the preset sequence may be one of six types of three power-on positions, that is, 1-2. -3, any of 1-3-2, 2-1-3, 2-3-1, 3-1-2, 3-2-1.

The first boot backup and the second boot backup are taken as an example for description. The second boot backup is a backup backup that is located in the preset order and is adjacent to the first boot backup and is adjacent to the first boot backup. It should be noted that the adjacent here refers to the sequential order of execution, rather than the adjacent position of the storage location.

The starting address of the first boot backup is the first address, and the starting address of the second boot backup is the second address. The first address is taken as M times the offset address, and the second address is taken as N times the offset address. M and N are two preset values that are not equal, and both M and N are greater than or equal to zero.

For example, the value of the offset address is 4 megabytes, the number of boot backups is 3, and the starting addresses of the three boot backups are 0×4 megabytes, 1×4 megabytes, and 2×4 megabytes, respectively. The first address may be any one of three addresses, and the second address is any one of the three addresses except the first address.

The on-chip boot logic determines the first address based on the offset address and attempts to initiate the first boot backup. When the first boot backup fails, the second address is determined according to the offset address, and the second boot backup is started. And so on, until a boot backup is successfully started.

It can be understood that the offset address can be read from the flash after the CPU is powered on, and the boot backup is started one by one according to the offset address and the startup sequence. Or, in another In the possible case, the storage and acquisition of the offset address is not necessary. After the CPU is powered on, the start address of the first boot backup is directly read from the flash, and then the first boot backup is attempted. If the first boot backup fails, read the start address of the second boot backup directly from the flash, and then try to start the second boot backup. It can be understood that the two methods can still be combined with the correctness check solution mentioned in the embodiment of the present invention, and the start address of the Boot backup corresponding to the foregoing power-on position is non-zero. The combination of address schemes.

It should be noted that, in the embodiment of the present invention, the memory storing at least two Boot backups may be a single non-volatile memory chip, or may be more than one non-volatile memory chip. Taking the flash chip as an example, at least two boot backups are stored in at least one flash chip, and at least one flash chip stores at least one boot backup in one flash chip. A flash control logic circuit is disposed between the CPU and the at least one flash chip, and the CPU accesses the at least one flash chip through the flash control logic circuit.

The advantage of storing Boot backups through at least one flash chip is that flash chips continue to evolve toward larger capacity and cheaper prices, but their reliability is uneven. Therefore, different flash backups can be stored separately using flash chips with different reliability.

For example, the first boot backup is a new version of the boot backup, and the second boot backup is the factory version of the boot backup, and the board does not upgrade the second boot backup in the later use. If the first boot backup is correct, you can start a new version of Boot. If the boot of the first boot fails, the boot of the factory version is started, that is, the second boot backup. In this case, the amount of data of the second boot backup can be relatively small, and is stored in a flash chip with high price and high reliability, and the amount of data of the first boot backup can be relatively large, and the price is low. At the same time the reliability is also relatively low within the flash chip.

In the method for starting the boot provided by the embodiment of the present invention, the CPU includes on-chip boot logic. After the CPU is powered on, the on-chip boot logic is run, the on-chip boot logic determines the offset address, and the boot backup is started one by one according to the offset address. A boot backup has been successfully started. On-chip boot logic supports two or more power-on locations, different boot backups Each of them has no effect on each other. It does not cause another Boot backup to be started because a boot backup fails. Therefore, as long as one boot backup can be started normally, the Boot boot can be guaranteed, thereby improving the reliability of Boot boot.

Embodiment 2

With reference to the first embodiment, the second embodiment of the present invention provides another method for starting the boot, which is applied to the CPU, and is described in conjunction with the application scenario of the secure boot in this embodiment.

In an application scenario where security is required, the board needs to support secure startup. The program that the security boot requires the board to start from power-on should be verified by digital signature. Programs, including the Boot and the operating system, must be digitally signed and verified before starting. If the verification fails, the program cannot be started. The board stops this startup.

In combination with the execution process in the prior art shown in FIG. 1, the CPU needs to perform digital signature verification on the L1BootRom before starting. If the L1BootRom fails to pass the verification, since the jump from L1BootRom to other backups cannot be implemented, the Boot startup will definitely Failure, which in turn caused the board to fail to boot safely. The method for booting the boot provided in the second embodiment of the present invention is to overcome the problem that the boot backup cannot be verified due to the failure of a boot backup to be verified. Referring to FIG. 2, the method for booting the boot includes the following. step:

201. Determine an offset address.

The same as step 201 in the first embodiment, and details are not described herein again.

202. Safely start at least two boot backups according to the offset address one by one according to the preset sequence, until one boot backup is successfully started.

In the secure boot application scenario, the CPU on-chip boot logic includes an on-chip boot code, and the on-chip boot code includes a boot check code and a public key for the boot backup digital signature. After the CPU is powered on, run the verification code of the on-chip startup logic, read the digital signature of a certain boot backup, and perform digital signature verification on the boot backup using the public key. Boot backup is safely started. That is, the Boot backup is successfully started after being verified by digital signature.

On-chip boot logic supports reading the backup code from two or more power-up locations. A power-on position corresponds to a boot backup, passing from different upper potentials To read the code of different boot backups, the on-chip boot logic can perform digital signature verification on each of the at least two boot backups. That is to say, when a boot backup fails the digital signature verification, the on-chip boot logic jumps to another boot backup, and the other boot backup is digitally signed and verified.

For example, after the CPU is powered on, the on-chip startup logic performs digital signature verification on the Boot backup corresponding to the first power-on position. If the Boot backup fails the verification, the on-chip startup logic is based on the CPU after the CPU resets. Move the address to jump, and perform digital signature verification on the Boot backup corresponding to the second power-on location. Of course, in the application scenario of the secure startup, in addition to performing digital signature verification on the Boot backup, the correctness check can be performed on the Boot backup.

The first boot backup and the second boot backup are taken as an example for description. The starting address of the first boot backup is the first address, the starting address of the second boot backup is the second address, and the first address and the second address are respectively two different power-on positions, and the first address is The default power-up position when the on-chip boot logic starts running. The first address is taken as M times the offset address, and the second address is taken as N times the offset address. M and N are two preset values that are not equal, and both M and N are greater than or equal to zero.

After the CPU is powered on, the on-chip boot logic determines the first address, reads the digital signature from the first boot backup, and performs digital signature verification and correctness check on the first boot backup.

When the first boot backup passes the verification (the digital signature checksum correctness check passes), the first boot backup is started. When the first boot backup is the first boot backup that is verified after the CPU is powered on, it is better to use the first boot backup as the new version of the boot backup. If the verification is passed, the new version of the boot can be started.

When the first boot backup fails the verification (the digital signature checksum correctness check fails), the on-chip boot logic determines the second address, reads the digital signature from the second boot backup, and the second Boot backup is verified. When the second boot backup passes the verification, the second boot backup is started. Optionally, the second boot backup is a factory version, and the second boot backup start address is a zero address. When the new version of the first boot backup fails, the factory version of the second boot backup is started, and the second boot backup address is a non-zero address.

In addition to the first boot backup and the second boot backup, the third boot backup includes a third boot backup, and the third boot backup is a new version of the boot backup. If the second boot backup fails verification, the on-chip boot logic can verify the third boot backup.

Alternatively, the third boot backup can be started in another manner, that is, when the second boot backup can be started normally, the third boot backup is verified by the second boot backup, and if the third boot backup passes the verification, Indicates that the third boot backup is started. The advantage of this is that the second boot backup is the factory version, and its function is often not perfect compared to the new version of the boot backup. Therefore, the second boot backup verifies the third boot backup and the third boot backup passes the verification and starts. The third boot backup is started, so that a new version of the boot backup can be started.

It should be specially stated that the boot backup code includes a boot part and a non-boot part. When the on-chip boot logic verifies the third boot backup and passes, the on-chip boot logic jumps to the boot part of the third boot backup. , start the third boot backup. In the case that the second boot backup verifies and passes the third boot backup, indicating that the third boot backup is started, since the second boot backup has already completed the boot portion, the direct jump to the third boot backup is performed. Part of the execution continues.

In the method for starting the boot provided by the embodiment of the present invention, after the CPU is powered on, the on-chip boot logic is run, and the on-chip boot logic determines the offset address, and according to the offset address, at least two Boot backups are performed one by one until the check is performed. A Boot Backup security boot was successful. Alternatively, the on-chip boot logic performs verification on the boot backup one by one according to the start address of at least two boot backups until a boot backup is successfully started. Alternatively, the on-chip boot logic verifies the boot backup according to the start address (non-zero) of the boot backup corresponding to the power-on position, and if it fails, checks one by one other boot backup according to the offset address, at least two Boot backup is verified until a boot backup is successfully started. The on-chip boot logic supports two or more power-on locations. Each boot backup can be independently verified. It is not possible to check another boot backup because one boot backup fails. Therefore, A boot backup can be started normally by verifying and booting normally, thus improving the boot. Boot startup reliability.

Based on the embodiment corresponding to FIG. 2, an embodiment of the present invention further provides a CPU, where the CPU is used to be installed on a board, the board includes a memory, and the memory stores at least two boot disk backups. In the at least two boot backups, the offset addresses of the two adjacent boot backups are preset values, where the offset address is the interval between the start addresses of the two adjacent boot backups.

The CPU includes on-chip boot logic, and the on-chip boot logic may specifically be an on-chip hardware circuit, or may be an on-chip boot code, or a combination of the two.

The hardware circuit may be a specific integrated circuit integrated in the CPU (Application Specific Integrated Circuit, English abbreviation: ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

The on-chip boot code may be a firmware code stored in the CPU. After the CPU is powered on, the on-chip boot code is invoked to execute the steps performed by the CPU in the method of booting the boot provided by the embodiment of the present invention. Or the on-chip boot code cooperates with the on-chip hardware circuit to jointly complete the steps performed by the CPU in the method of booting the boot, which specifically includes the following two methods:

In the first way, the CPU determines the offset address and attempts to initiate a boot backup one by one according to the offset address. For example, the CPU on-chip boot logic defines the number of power-on locations, the size of the offset address, and the order in which the boot backups are attempted. After the CPU is powered on, the offset address is determined, and the Boot backup is started according to the offset address in a preset order, and the correctness check and digital signature verification of the Boot backup are performed until a Boot backup is successfully started.

In the second mode, after the CPU is powered on, the boot address of the Boot backup is read from the flash, and the boot backup corresponding to the start address is attempted. If a boot backup fails, read the start address of the next boot backup and try to start the next boot backup until a boot backup succeeds.

It can be understood that the two methods can be combined with the correctness check solution mentioned in the embodiment of the present invention, and the start address of the Boot backup corresponding to the power-on position mentioned above is a non-zero address. The combination of the programs.

As shown in FIG. 3, in a possible implementation manner, the CPU 30 includes:

The determining unit 301 is configured to determine an offset address.

The boot startup control unit 302 is configured to start at least two boot backups according to the offset address one by one according to a preset sequence, until one boot backup is successfully started.

Optionally, the determining unit 301 is specifically configured to determine an offset address according to the pre-configured hardware indication signal.

Optionally, the startup address corresponding to the first boot backup accessed by the Boot startup control unit 302 is not 0.

Optionally, at least two boot backups include a first boot backup and a second boot backup.

The Boot Start Control Unit 302 is configured to determine a first address according to the offset address, and check the first Boot backup. When the first boot backup passes the verification, the first boot backup is started. The first address is the starting address of the first boot backup, the first address is M times the offset address, M is an integer greater than or equal to 0, and M is a preset value.

The boot control unit 302 is further configured to: when the first boot backup fails the verification, determine the second address according to the offset address, and verify the second boot backup according to the second address, when the second boot backup passes the school At the time of verification, the second boot backup is started. The second address is the starting address of the second boot backup, the second address is N times the offset address, N is an integer greater than or equal to 0, and N is a preset value that is not equal to M.

The boot startup control unit 302 is configured to determine a first address according to the offset address, and start the first boot backup. The first address is the starting address of the first boot backup, the first address is M times the offset address, M is an integer greater than or equal to 0, and M is a preset value.

The boot startup control unit 302 also determines, when the first boot backup fails, determines the second address according to the offset address, and starts the second boot backup. The second address is the starting address of the second boot backup, and the second address is N times the offset address, where N is large. An integer equal to or equal to 0, and N is a preset value that is not equal to M.

Optionally, the EP30 303 is disposed on the periphery of the CPU 30.

The determining unit 301 is specifically configured to read the register value in the EPLD 303 and use the register value as the value of the offset address.

Optionally, the CPU 30 is provided with a pin for receiving a hardware indication signal.

The determining unit 301 is specifically configured to read a binary code input by the board to the pin, and determine an offset address according to the binary code.

Optionally, the CPU 30 further includes a storage unit 304, configured to store at least two candidate offset addresses.

The determining unit 301 is specifically configured to determine, according to the binary code, one of the at least two candidate offset addresses as an offset address.

Optionally, the determining unit 301 is specifically configured to use the value of the binary code as the value of the offset address.

The CPU provided by the embodiment of the present invention includes an on-chip boot logic. After the CPU is powered on, the on-chip boot logic is run, and the on-chip boot logic determines the offset address. According to the offset address, the boot backup is started one by one until there is a boot. The backup was successfully started. The on-chip boot logic supports two or more power-on locations. Different boot backups have no independent effects. They do not start another boot backup because one boot backup fails. Therefore, as long as one boot backup can be started normally. , it can ensure the boot of the boot, thereby improving the reliability of the boot boot.

Based on the embodiment corresponding to FIG. 3, an embodiment of the present invention further provides a single board. Referring to FIG. 4, the board 40 includes a CPU 401 and a memory 402.

The CPU 401 is the CPU 401 described in the embodiment corresponding to FIG. 4.

The memory 402 stores at least two boot backups. In at least two boot backups, the offset addresses of the two adjacent backups are preset values, and the offset address is between the start addresses of two adjacent boot backups. Interval.

Optionally, the at least two booting backups include a first boot backup, a second boot backup, and a third boot backup.

When the first boot backup fails, and the second boot backup is started, the second boot is started. It is used to verify the third boot backup. When the third boot backup passes the verification, the third boot backup is started.

Optionally, the first boot backup and the third boot backup are the new version of the boot backup, and the second boot backup is the factory version of the boot backup.

Optionally, the memory 402 includes at least one flash memory chip 403, and FIG. 4 shows a case where three flash memory chips 403 are included. At least two boot backups are stored in at least one flash chip 403. Among the at least one flash chip 403, at least one boot backup is stored in one flash chip 403.

The board 40 also includes flash control logic 404 through which the CPU 401 accesses at least one flash chip.

The board provided by the embodiment of the present invention includes a CPU and a memory. After the CPU is powered on, the offset address is determined. According to the offset address, the Boot backup stored in the memory is started one by one until a Boot backup is successfully started. The CPU supports two or more power-on locations. Different boot backups have no effect on each other. They do not start another boot backup because one boot backup fails. Therefore, as long as one boot backup can be started normally, you can Ensures boot startup, which improves the reliability of boot startup and further improves the reliability of board startup.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It is within the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A method for booting a boot, which is applied to a CPU of a central processing unit, wherein the CPU is mounted on a single board, the single board includes a memory, and at least two boot boot backups are stored in the memory, where the at least two In the two boot backups, the offset addresses of the two adjacent boot backups are preset values, where the offset address is the interval between the start addresses of two adjacent boot backups, and the CPU includes an on-chip boot. Logic, the CPU executes the method for booting a boot by using the on-chip booting logic, where the method for booting the boot includes:

Determining the offset address; starting the at least two boot backups according to the offset address one by one in a preset order until one boot backup is successfully started.
The method for starting a boot according to claim 1, wherein the determining the offset address comprises:

The offset address is determined based on a pre-configured hardware indication signal.
The method for starting the boot according to claim 1 or 2, wherein the starting address corresponding to the first boot backup accessed by the CPU is not 0 during the booting process.
The method for initiating a boot according to any one of claims 1 to 3, wherein the at least two boot backups comprise a first boot backup and a second boot backup, according to the offset address, according to The at least two boot backups are started one by one in a preset sequence, including:

Determining a first address according to the offset address, and verifying the first boot backup; wherein the first address is a start address of the first boot backup, and the first address is the M times the offset address, M is an integer greater than or equal to 0, and M is a preset value;

When the first boot backup passes the verification, the first boot backup is started;

When the first boot backup fails the verification, determining the second address according to the offset address, and verifying the second boot backup according to the second address, when the second boot backup passes During the verification, the second boot backup is started; wherein the second address is a starting address of the second boot backup, and the second address is the partial N times the address is shifted, N is an integer greater than or equal to 0, and N is a preset value that is not equal to M.
The method for initiating a boot according to any one of claims 1 to 3, wherein the at least two boot backups comprise a first boot backup and a second boot backup, according to the offset address, according to The at least two boot backups are started one by one in a preset sequence, including:

Determining a first address according to the offset address, and starting the first boot backup; wherein the first address is a start address of the first boot backup, and the first address is the offset address M times, M is an integer greater than or equal to 0, and M is a preset value;

Determining, according to the offset address, the second address, and starting the second boot backup, where the second address is the starting address of the second boot backup, The second address is N times the offset address, N is an integer greater than or equal to 0, and N is a preset value that is not equal to M.
The method for booting a boot according to any one of claims 2 to 5, wherein the CPU peripheral is provided with an erasable editable logic device EPLD;

Determining the offset address according to the pre-configured hardware indication signal, including:

The register value in the EPLD is read, and the register value is taken as the value of the offset address.
A method of booting a boot according to any one of claims 2 to 5, characterized in that

The CPU is provided with a pin for receiving the hardware indication signal;

Determining the offset address according to the pre-configured hardware indication signal, including:

Reading a binary code input by the board to the pin;

The offset address is determined based on the binary code.
The method for booting according to claim 7, wherein the on-chip boot logic of the CPU defines at least two candidate offset addresses;

The determining the offset address according to the binary code includes:

Determining one of the at least two candidate offset addresses according to the binary code Is the offset address.
The method for starting a boot according to claim 7 or 8, wherein the determining the offset address according to the binary code comprises:

The value of the binary code is taken as the value of the offset address.
A central processing unit CPU, the CPU is configured to be installed on a single board, the single board includes a memory, and the memory stores at least two booting backups, and the at least two boot backups are adjacent to the two The offset address of the Boot Backup is a preset value, where the offset address is an interval between the start addresses of two adjacent Boot Backups; the CPU includes:

a determining unit, configured to determine the offset address;

The boot startup control unit is configured to start the at least two boot backups according to the offset address one by one according to a preset sequence, until one boot backup is successfully started.
The CPU according to claim 10, characterized in that

The determining unit is specifically configured to determine the offset address according to a pre-configured hardware indication signal.
A CPU according to claim 10 or 11, wherein

The boot address corresponding to the first boot backup accessed by the boot startup control unit is not 0.
The CPU according to any one of claims 10 to 12, wherein the at least two boot backups comprise a first boot backup and a second boot backup;

The booting control unit is configured to determine a first address according to the offset address, and perform verification on the first boot backup; when the first boot backup passes verification, start the first The boot backup; wherein the first address is a start address of the first boot backup, the first address is M times the offset address, M is an integer greater than or equal to 0, and M is a pre- Set value

The booting control unit is further configured to: when the first boot backup fails the verification, determine the second address according to the offset address, and perform the second boot backup according to the second address. The second boot backup is started when the second boot backup passes the verification; wherein the second address is the start of the second boot backup An address, the second address is N times the offset address, N is an integer greater than or equal to 0, and N is a preset value that is not equal to M.
The CPU according to any one of claims 10 to 12, wherein the at least two boot backups comprise a first boot backup and a second boot backup;

The booting control unit is configured to determine a first address according to the offset address, and start the first boot backup, where the first address is a starting address of the first boot backup. The first address is M times the offset address, M is an integer greater than or equal to 0, and M is a preset value;

The booting control unit further determines, when the first boot backup fails, determines a second address according to the offset address, and starts the second boot backup; wherein the second address is the The starting address of the second boot backup, the second address is N times the offset address, N is an integer greater than or equal to 0, and N is a preset value that is not equal to M.
The CPU according to any one of claims 11 to 14, wherein the CPU peripheral is provided with an erasable editable logic device EPLD;

The determining unit is specifically configured to read a register value in the EPLD, and use the register value as a value of the offset address.
The CPU according to any one of claims 11 to 14, wherein the CPU is provided with a pin for receiving the hardware indication signal;

The determining unit is specifically configured to read a binary code input by the board to the pin, and determine the offset address according to the binary code.
The CPU according to claim 16, wherein the CPU further comprises a storage unit for storing at least two candidate offset addresses;

The determining unit is specifically configured to determine, according to the binary code, one of the at least two candidate offset addresses as the offset address.
A CPU according to claim 16 or 17, wherein:

The determining unit is specifically configured to use a value of the binary code as a value of the offset address.
A single board, wherein the single board includes a central processing unit CPU And memory;

Wherein the CPU is the CPU according to any one of claims 10-18;

At least two boot backups are stored in the memory. In the at least two boot backups, offset addresses of two adjacent boot backups are preset values, and the offset addresses are adjacent to two boot backups. The interval between the starting addresses.
The board of claim 19, wherein the at least two boot backups comprise a first boot backup, a second boot backup, and a third boot backup;

After the first boot backup fails, and the second boot backup is started, the second boot is used to check the third boot backup, and when the third boot backup passes the check, Instructing the third boot backup to start.
The veneer according to claim 20, wherein

The first boot backup and the third boot backup are new version Boot backups, and the second boot backup is a factory version boot backup.
A veneer according to any one of claims 19 to 21, wherein

The memory includes at least one flash memory chip, and the at least two boot backups are stored in the at least one flash memory chip; wherein, among the at least one flash memory chip, at least one boot backup is stored in one flash memory chip;

The board also includes flash control logic circuitry, the CPU accessing the at least one flash chip through the flash control logic.