CN109558176A - A kind of double Qi Fangfa based on Flash inside CPLD - Google Patents
A kind of double Qi Fangfa based on Flash inside CPLD Download PDFInfo
- Publication number
- CN109558176A CN109558176A CN201811449853.8A CN201811449853A CN109558176A CN 109558176 A CN109558176 A CN 109558176A CN 201811449853 A CN201811449853 A CN 201811449853A CN 109558176 A CN109558176 A CN 109558176A
- Authority
- CN
- China
- Prior art keywords
- cpld
- flash
- programming
- programming data
- memory blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
Abstract
The invention discloses a kind of double Qi Fangfa based on Flash inside CPLD, comprising the following steps: by the built-in Flash of CPLD, is divided into Flash-0 and two memory blocks of Flash-1；Two kinds of programming datas are distinguished into imprinting to two memory blocks；The programming data of one of memory block in two memory blocks is selected to move the RAM built-in to CPLD, to reach the bis- Qi Gongneng of CPLD.A kind of double Qi Fangfa based on Flash inside CPLD provided in an embodiment of the present invention, have the advantages that and reduce costs, be not required in addition increase a Flash to reach double startup function；Avoid CPLD can not starting problem, have mechanism inside entanglement due to unknown cause of CPLD programming data 0, CPLD and programming data 1 directly used to start；Different programming datas can be started according to different demands, two different programming datas can be used to go to test different circuit respectively to different research and development or measuring unit in the circuit development phase.
Description
Technical field
The present invention relates to a kind of double Qi Fangfa based on Flash inside CPLD.
Background technique
CPLD is widely used to the design of server, in order to avoid CPLD programming data because unknown cause entanglement then can not
Normal starting, so all starting to want to support double startup function using CPLD at present, but tradition CPLD is to reach double startup function
The storage that a Flash does another log-on data need to can be in addition hung, cost is very high.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide one kind based on Flash inside CPLD
Double Qi Fangfa, reduce costs, avoid CPLD can not starting problem, solve problem of the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of double Qi Fang based on Flash inside CPLD
Method, comprising the following steps:
By the built-in Flash of CPLD, it is divided into Flash-0 and two memory blocks of Flash-1；
Two kinds of programming datas are distinguished into imprinting to two memory blocks；
The programming data of one of memory block in two memory blocks is selected to move the RAM built-in to CPLD, to reach
To the bis- Qi Gongneng of CPLD.
Preferably, the programming data of one of memory block in two memory blocks of the selection is moved built-in to CPLD
RAM the step for specifically include: Flash-0 store programming data 0, Flash-1 store programming data 1, if 0 He of programming data
Entanglement due to unknown cause of 1 one of programming data, then move another normal programming data to RAM and realize that CPLD's is normal
Starting.
Preferably, the programming data of one of memory block in two memory blocks of the selection is moved built-in to CPLD
RAM the step for specifically include: when two programming datas in two memory blocks are normal, can according to different demands, lead to
Default Initiated Mechanism is crossed, the programming data of one of memory block is selected to move the RAM built-in to CPLD, to realize according to difference
Demand starts different programming datas.
Preferably, the RAM, storage by Flash move Lai programming data, and by the digital logic unit in CPLD,
It is compiled into the digital circuitry functions of user's design.
Preferably, two kinds of programming datas are distinguished to imprinting in a manner of JTAG In-System Programming to described
Two memory blocks.
As described above, a kind of double Qi Fangfa based on Flash inside CPLD provided in an embodiment of the present invention, have with following
Beneficial effect: reducing costs, and is not required in addition increase a Flash to reach double startup function；It avoids CPLD and can not start and ask
Topic, has mechanism inside entanglement due to unknown cause of CPLD programming data 0, CPLD and programming data 1 is directly used to start；It can
Start different programming datas according to different demands, two different programming datas can be used to go test different in the circuit development phase
Circuit respectively give different research and development or measuring unit.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets implementation of the invention
Example, and be used to explain the principle of the present invention together with specification.
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without any creative labor, is also possible to obtain other drawings based on these drawings.
Fig. 1 is flow chart of the invention；
Fig. 2 is that one kind provided by the invention specifically opens method flow diagram based on the double of Flash inside CPLD；
Fig. 3 is that another kind provided by the invention specifically opens method flow diagram based on the double of Flash inside CPLD；
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
As shown in Figure 1, the present invention provides a kind of double Qi Fangfa based on Flash inside CPLD, comprising the following steps:
S101, by the built-in Flash of CPLD, be divided into Flash-0 and two memory blocks of Flash-1；
Built-in Flash is divided into two storage regions by software program.
S102, two kinds of programming datas are distinguished into imprinting to two memory blocks；
As a preferred embodiment, two kinds of programming datas are in a manner of JTAG In-System Programming
Imprinting is distinguished to two memory blocks.
S103, the programming data of one of memory block in two memory blocks is selected to move the RAM built-in to CPLD,
To reach the bis- Qi Gongneng of CPLD.
The RAM, storage by Flash move Lai programming data be compiled into and by the digital logic unit in CPLD
The digital circuitry functions of user's design.
Referring to fig. 2, Fig. 2 is a kind of specific double flow charts for opening method provided by the embodiment of the present invention.
Referring to fig. 2, in embodiments of the present invention, it opens method based on the double of Flash inside CPLD and includes:
S201, by the built-in Flash of CPLD, be divided into Flash-0 and two memory blocks of Flash-1；This step with it is upper
It is essentially identical to state S101 in inventive embodiments, detailed content please refers to foregoing invention embodiment, is no longer repeated herein.
S202, two kinds of programming datas are distinguished into imprinting to two memory blocks；This step and foregoing invention are implemented
S102 is essentially identical in example, and detailed content please refers to foregoing invention embodiment, is no longer repeated herein.
S203, Flash-0 store programming data 0, and Flash-1 stores programming data 1, if programming data 0 and programming data 1
Another normal programming data, then is moved to RAM the normal starting for realizing CPLD by one entanglement due to unknown cause.
Referring to Fig. 3, Fig. 3 is the specific double flow charts for opening method of another kind provided by the embodiment of the present invention.
Referring to Fig. 3, in embodiments of the present invention, opens method based on the double of Flash inside CPLD and include:
S301, by the built-in Flash of CPLD, be divided into Flash-0 and two memory blocks of Flash-1；This step with it is upper
It states that S101 and S201 in inventive embodiments are essentially identical, and detailed content please refers to foregoing invention embodiment, no longer goes to live in the household of one's in-laws on getting married herein
It states.
S302, two kinds of programming datas are distinguished into imprinting to two memory blocks；This step and foregoing invention are implemented
S102 and S202 is essentially identical in example, and detailed content please refers to foregoing invention embodiment, is no longer repeated herein.
When S303, two programming datas in two memory blocks are normal, default starting can be passed through according to different demands
Mechanism selects the programming data of one of memory block to move the RAM built-in to CPLD, to realize according to different demands starting not
Same programming data.
Claims (5)
1. a kind of double Qi Fangfa based on Flash inside CPLD, which comprises the following steps:
By the built-in Flash of CPLD, it is divided into Flash-0 and two memory blocks of Flash-1；
Two kinds of programming datas are distinguished into imprinting to two memory blocks；
The programming data of one of memory block in two memory blocks is selected to move the RAM built-in to CPLD, to reach
The bis- Qi Gongneng of CPLD.
2. double Qi Fangfa according to claim 1, which is characterized in that one of them in two memory blocks of the selection is deposited
The programming data of storage area block is moved to the step for CPLD built-in RAM and specifically included: Flash-0 stores programming data 0,
Flash-1 stores programming data 1, will be another normal if entanglement due to unknown cause of programming data 0 and 1 one of programming data
Programming data move to RAM the normal starting for realizing CPLD.
3. double Qi Fangfa according to claim 1, which is characterized in that one of them in two memory blocks of the selection is deposited
The programming data of storage area block is moved to the step for CPLD built-in RAM and is specifically included: the two programming numbers in two memory blocks
According to it is normal when, by presetting Initiated Mechanism, the programming data of one of memory block can be selected to remove according to different demands
The built-in RAM of CPLD is moved to, starts different programming datas according to different demands to realize.
4. double Qi Fangfa according to claim 1, which is characterized in that the RAM, storage by Flash move Lai programming
Data, and by the digital logic unit in CPLD, it is compiled into the digital circuitry functions of user's design.
5. double Qi Fangfa according to claim 1, which is characterized in that by two kinds of programming datas with JTAG In-System
The mode of Programming distinguishes imprinting to two memory blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811449853.8A CN109558176A (en) | 2018-11-30 | 2018-11-30 | A kind of double Qi Fangfa based on Flash inside CPLD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811449853.8A CN109558176A (en) | 2018-11-30 | 2018-11-30 | A kind of double Qi Fangfa based on Flash inside CPLD |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109558176A true CN109558176A (en) | 2019-04-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201811449853.8A Pending CN109558176A (en) | 2018-11-30 | 2018-11-30 | A kind of double Qi Fangfa based on Flash inside CPLD |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200976140Y (en) * | 2005-04-29 | 2007-11-14 | 美国凹凸微系有限公司 | System for updating on-site programmable gate array bit files |
| CN101853172A (en) * | 2010-05-24 | 2010-10-06 | 中兴通讯股份有限公司 | Device and method for dynamically upgrading complex programmable logic device (CPLD) |
| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| CN103116511A (en) * | 2013-01-29 | 2013-05-22 | 烽火通信科技股份有限公司 | Double-booting method based on single FLASH storage chip |
-
2018
- 2018-11-30 CN CN201811449853.8A patent/CN109558176A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200976140Y (en) * | 2005-04-29 | 2007-11-14 | 美国凹凸微系有限公司 | System for updating on-site programmable gate array bit files |
| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| CN101853172A (en) * | 2010-05-24 | 2010-10-06 | 中兴通讯股份有限公司 | Device and method for dynamically upgrading complex programmable logic device (CPLD) |
| CN103116511A (en) * | 2013-01-29 | 2013-05-22 | 烽火通信科技股份有限公司 | Double-booting method based on single FLASH storage chip |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190402 |
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| RJ01 | Rejection of invention patent application after publication |