CN103108175A - Motion compensation structure in multimode video decoder - Google Patents
Motion compensation structure in multimode video decoder Download PDFInfo
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- CN103108175A CN103108175A CN2011103513157A CN201110351315A CN103108175A CN 103108175 A CN103108175 A CN 103108175A CN 2011103513157 A CN2011103513157 A CN 2011103513157A CN 201110351315 A CN201110351315 A CN 201110351315A CN 103108175 A CN103108175 A CN 103108175A
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Abstract
The invention relates to a modified novel interpolation method structure which is appropriate for multi-standard motion compensation. A motion compensation structure in a multimode video decoder is based on a Rounding Last (RL) strategy and a Diagonal Two Step (DTS) strategy which are provided by the invention. The novel interpolation method used by the motion compensation structure in the multimode video decoder has more regular data dependence relationship and a uniform two-step interpolation structure is applied, interpolation values of the luminance component and the chromaticity component in various standards are effectively compatible. Based on the novel method, a multi-standard motion compensation hardware circuit capable of being reconfigured is achieved. The multi-standard motion compensation hardware circuit capable of being reconfigured adopts the motion compensation structure based on the size of a variable-block. The motion compensation structure comprises five reconfigurable 8-grade finite impulse response (FIR) filters. Implementation results show that by means of the motion compensation structure in the multimode video decoder, bandwidth requirements are reduced by 27%-50%, the average burst length of accessing an external memory once is improved by 1.22 times-2.25 times, under the technology of 0.18 micrometer, the circuit only comprises 45.8K equivalent logic gates and 384-byte on-chip storage, under the worst condition, processing of a macro block needs about 520 periods, and under the operating frequency of 125MHZ, the motion compensation structure in the multimode video decoder can meet real-time decoding requirements of complete high definition 1080p (1920*1080) 30 frames per second.
Description
Technical field
The present invention is applicable to the multimedia video technique field, particularly aspect compatible multi-standard video decoding, satisfies the solution code requirement of HD video on the basis of low-power consumption.
Background technology
Motion compensation technique improves the efficient of Video coding by the temporal redundancy between the elimination consecutive frame.In up-to-date video encoding standard, many new coding techniquess have been introduced in motion compensation, comprise variable-block size, multi-reference frame, bi-directional predicted, unrestriced motion vector and 1/4th precision interpolation etc.All these new technologies all can improve the efficient of Video coding, but have also increased greatly computing demand and the bandwidth demand of motion compensation simultaneously.In main level H.264/AVC, motion compensation has taken 25% of total decode time, and has taken 50% of total bandwidth; Simultaneously, shared decode time and the bandwidth demand of motion compensation will increase respectively by 15% to 30% left and right in main.The situation of AVS and MPEG-4 ASP is also similar.Therefore, motion compensation is the bottleneck of many standard decoder designs.
In the past for H.264/AVC efficient movement compensating circuit, it has all adopted the motion compensation structure based on the 4x4 fixed block size, and complicated data huge profit has been proposed with strategy and scheduling strategy, to overcome the defective that motion compensation was brought based on the 4x4 block size, thereby cause the more on-chip memory of needs and complicated control logic to support these New Policies, luminance component and chromatic component have all adopted different hardware interpolation circuits simultaneously; H.264/AVC structure in the past can support the brightness interpolating structure with AVS simultaneously, but does not support chroma interpolation, does not also support other standards simultaneously; Some structures mainly concentrate on design and the realization of motion compensation subsystem (comprising motion-vector prediction etc.) in many standard decoders, but do not comprise the detailed description for the motion compensated interpolation structure; Some work has proposed to adopt a kind of 4 grades of new oriented FIR filters to replace H.264/AVC original 6 grades of filters in standard, with the irregular problem that solves original interpolation method and too high bandwidth demand problem, but it has introduced more serious image quality loss, also fails to propose to be applicable to simultaneously the solution of many standards.
Summary of the invention
The technical problem that (one) will solve
In field of video applications, the situation that many standards occurred and deposited is for adopting same set of circuit can realize that the solution code requirement of a plurality of various criterion code streams highlights day by day at present.In various up-to-date video encoding and decoding standards, variable-block size, multi-reference frame, the new technology such as bi-directional predicted all can improve the efficient of Video coding, but also increase greatly computing demand and the bandwidth demand of motion compensation simultaneously.The tradition implementation has adopted the motion compensation structure based on the 4x4 fixed block size.In this structure, motion compensation is carried out take the 4x4 fritter as unit, the data volume that need to carry out buffer memory on sheet this moment is reduced greatly, thereby can reduce hardware consumption, but also brought a large amount of redundant external memory access and redundant operation simultaneously, caused the increase of circuit bandwidth demand and the reduction of throughput.
(2) technical scheme
For effectively solving the multi-standard compatibility problem of motion compensation, this paper proposed a kind of improved be applicable to the compensation of many standard movements (comprise MPEG-2, H.263, MPEG-4 SP/ASP, H.264/AVC and AVS) new interpolation method structure, and design has realized a kind of reconfigurable many standard movements compensation hardware circuits.New interpolation method proposed by the invention is based on RL strategy proposed by the invention and DTS strategy, new method has more regular data dependence relation, its adopt a kind of two step interpolation structures of unification effectively compatible the interpolation of luminance component and chromatic component in each standard.Based on new method, this paper designs and has realized a kind of reconfigurable many standard movement compensation hardware circuits, and this structure adopts the motion compensation structure based on the variable-block size, has effectively reduced external memory access and redundant operation.
(1) in the RL strategy, ask nonlinear round up operation and saturation limiting operation in Interpolation Process in ignoring.
(2) DTS (Diagonal Two Step) strategy represent respectively in two steps on vertical direction and horizontal direction on 1/4 precision filtering interpolation.
(3) in corresponding Design of Hardware Architecture, the present invention adopts the motion compensation based on the variable-block size, the motion compensated interpolation process will be carried out in strict accordance with corresponding block size, with the bandwidth demand of minimizing external memory, and the burst length of increase single reference external memory reduces the access power consumption of external memory storage.
(4) hardware configuration that adopts simultaneously the looking ahead of reference pixel, Horizontal interpolation filtering and vertical filtering interpolation to carry out simultaneously.
(5) for interpolating unit, filtering operation of the present invention is converted into the vector zoom operations, and for filtering hardware, design pre-calculation unit Precomputer and reconfigurable addition shift unit SAU consist of.
(3) beneficial effect
The present invention has following beneficial effect:
1. the present invention proposes RL strategy and the DTS strategy of optimization, based on these two kinds of strategies, this paper proposed a kind of improved be applicable to the compensation of many standard movements (comprise MPEG-2, H.263, MPEG-4 SP/ASP, H.264/AVC and AVS) new interpolation method structure, and by detailed experiment show the feasibility of new interpolation method structure.Compare with traditional implementation, this paper algorithm structure has more regular data dependence relation and unified interpolation structure, and need still less on-chip memory and register resources with the irregular data of buffer memory.
2. the present invention is based on the new method structural design and realized a kind of reconfigurable many standard movement compensation hardware circuits, 5 reconfigurable FIR filters based on sharing adder structure have been used in this design, and circuit can satisfy the real-time decoding demand of full HD 1080p (1920x1080) 30 frames/s under the 125MHz operating frequency.For overcoming deficiency and the defective based on 4x4 fixed block size motion compensation structure, the present invention has adopted the motion compensation structure based on the variable-block size, this structure can not introduced the external memory access of any redundancy and the calculating of redundancy, has improved greatly the access efficiency of external memory storage and the throughput of circuit.
Description of drawings
Fig. 1 is the irregular data dependence in the 1/4 pixel precision motion compensation analyzed of the present invention.
Fig. 2 is many standard movement compensation hardware circuit figure that the present invention proposes.
Fig. 3 is the read and write access pattern of the transpose memory that proposes of the present invention.
Fig. 4 is the restructural FIR filter hardware structure chart that the present invention proposes.
Embodiment
For making purpose of the present invention, technical scheme and advantage are clearer, and below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The efficient motion compensation new construction of the many standards of this compatibility provided by the invention, based on RL (Rounding Last) strategy and DTS (the Diagonal Two Step) strategy that propose, a kind of new unified interpolation method structure that is applicable to many standard movement compensation has been proposed, and on the basis of this algorithm, designed restructural motion compensation hardware configuration.
1. proposed RL strategy and the DTS strategy of simplification in the present invention, will ignore nonlinear round up operation and saturation limiting operation in 1/4th pixel intermediate interpolated processes in the RL strategy; In the DTS strategy, diagonal 1/4th pixels are completed by two step Interpolation Process, first carry out interpolation on horizontal direction according to horizontal level, then carry out interpolation on vertical direction according to the interpolation result on upright position and horizontal direction.With reference to Fig. 1, in the RL strategy, 1/4 pixel a, and c, d, the interpolation result of n} will directly be produced by the integer pixel point interpolation; 1/4 pixel i, and k, f, the interpolation result of q} will directly be produced by horizontal half-pix point or vertical half-pix point interpolation.
2. the present invention is based on above improved RL strategy and the DTS strategy that proposes, in each standard, the motion compensated interpolation process all can adopt the two consistent steps of statement to improve interpolation method.The method makes the Interpolation Process of all fraction pixel points of luminance component and chromatic component in various criterion all can complete with a kind of two step Interpolation Process of unification.At first carry out interpolation on horizontal direction according to horizontal level, then carry out interpolation on vertical direction according to the interpolation result on upright position and horizontal direction.
3. the present invention is based on the above method that proposes and proposed reconfigurable hardware configuration.In order to reduce the on-chip memory of buffer memory reference pixel, the difference process in two steps:
(1) carry out at first in the horizontal direction, and intermediate object program is temporary in transpose memory on sheet.
(2) then vertical filter is taken out intermediate object program from transpose memory, carries out the interpolation operation on vertical direction.
Interpolation result on horizontal direction interpolation result and vertical direction all is limited in 8bit, with the area of buffer memory and the bit wide of interpolation filter on the minimizing sheet.
4. in the present invention the hardware configuration of motion compensation is as shown in Figure 2.This main circuit will be comprised of reference pixel pre-fetch unit and interpolating unit.Pre-fetch unit comprises 6 grades of dark FIFO 204 as the buffer memory of looking ahead of reference pixel, the delegation reference pixel of each FIFO word in can the buffer memory reference pixel block.Interpolating unit comprises the transpose memory 203 of 402 and one 24 of 201, two vertical interpolation filters of three Horizontal interpolation filters (H0, H1, H2) (V0, V1), and transpose memory is divided into two bank.Three Horizontal interpolation filters can be carried out the interpolation of three row fractional samples simultaneously, and each filter is responsible for delegation.The intermediate object program that the Horizontal interpolation filter produces will be stored in transpose memory in the mode of intersecting by row, and even column is stored in bank0, and odd column is stored in bank1.By this storage mode, two vertical filter can be processed the interpolation of two row fractional samples simultaneously, so can be so that interpolating unit reaches the throughput that per cycle produces two pixels.
5. the present invention adopts transpose memory access module flexibly, as shown in Figure 3.A main feature of many standard movements compensation hardware structures proposed by the invention is that the looking ahead of reference pixel, Horizontal interpolation filtering can be carried out simultaneously with vertical filtering interpolation.At first take out three row reference pixels in reference block by pre-fetch unit, after being ready to, carried out simultaneously the Horizontal interpolation process of three row samples by the Horizontal interpolation filter, pre-fetch unit following three row reference pixels of can looking ahead in advance simultaneously, by access mode and the memory module of careful arrangement external memory storage, can guarantee that the Horizontal interpolation process carries out continuously and do not introduce any streamline bubble.After the Horizontal interpolation process of a piece is completed, can start vertical interpolation operation, can carry out the Horizontal interpolation process of next piece in macro block simultaneously.For guaranteeing that horizontal filter can not cover wherein not yet the intermediate data of a upper piece of being processed by vertical filter to the write operation of transpose memory, the write operation direction of adjacent two pieces should be mutually orthogonal.
6. the present invention adopts reconfigurable FIR hardware configuration based on sharing adder.At first filtering operation is converted into the vector zoom operations, this moment, filter coefficient was represented as a series of addition and the displacement combinations with alpha operand of less bit wide that pre-define.In each standard, the maximum bit wide of filter coefficient is 6, and therefore, this paper is made as 3 with alpha operand bit wide.This moment, filter coefficient all can be expressed as the linear combination of two alpha operands arbitrarily, and the set of alpha operand is defined as { 1x, 3x, 5x, 7x}.Reconfigurable FIR hardware configuration as shown in Figure 4.This structure mainly is made of pre-calculation unit Precomputer 401 and addition shift unit SAU 403.Pre-calculation unit is completed the calculating of intermediate object program (i.e. input and the product of alpha operand), and intermediate object program is shared by 8 SAU, and the SAU unit carries out for intermediate object program the calculating that final interpolation result is completed in addition and shifting function.The SAU unit can carry out dynamic reconstruct 402 according to filter coefficient.Because the progression of interpolation filter between various criterion is different, interpolation filter for shorter progression, for avoiding introducing additional long delay, the design is by introducing the data selector of 8: 1 404, and it takes out interpolation result according to filter order timely at suitable pipelining-stage.
Above-described specific embodiment; to purpose of the present invention; technical scheme and beneficial effect further describe, and institute it should be understood that the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, as to make any modifications are equal to replacement; improve etc., within all should being included in protection scope of the present invention.
Claims (8)
1. the motion compensation structure of the many standards of compatibility, it is characterized in that this structure adopts a kind of improved new interpolation method that is applicable to many standard movement compensation, realize a kind of reconfigurable many standard movement compensation hardware configurations, it mainly comprises reference pixel pre-fetch unit and restructural interpolating unit.
2. motion compensation structure according to claim 1, it is characterized in that: be applicable to the new interpolation method of many standard movements compensation for the motion compensated interpolation process of each video encoding standard, adopt improved RL (Rounding Last) interpolation strategies and DTS (Diagonal Two Step) interpolation strategies, and formed two unified step interpolation structures.
3. motion compensation structure according to claim 2 is characterized in that: described RL interpolation strategies has been to ignore round up operation and saturation limiting of nonlinear in 1/4th pixel intermediate interpolated processes and has operated; Described DTS interpolation strategies is to adopt two unified step interpolation methods to replace traditional irregular multilevel interpolation process for diagonal 1/4th pixels.
4. motion compensation structure according to claim 2, it is characterized in that: described two the step interpolation structures in Interpolation Process in two steps, first horizontal direction is calculated, intermediate object program is temporary in transpose memory on sheet, then on the basis of memory, carry out the interpolation calculation on vertical direction.
5. motion compensation structure according to claim 1, it is characterized in that: described reference pixel pre-fetch unit comprises a multistage FIFO, but the delegation's reference pixel in the capable buffer memory reference pixel block of each FIFO, simultaneously, the prefetching process of reference pixel can be carried out simultaneously with the Interpolation Process of pixel.
6. motion compensation structure according to claim 1 is characterized in that: described restructural interpolating unit comprises transpose memory on a plurality of reconfigurable Horizontal interpolation filters and vertical interpolation filter and sheet; The Horizontal interpolation process of pixel has adopted block-based parallel pipelining process scheduling process with vertical Interpolation Process simultaneously, after the Horizontal interpolation process of a piece is completed, can start vertical interpolation operation, can carry out the Horizontal interpolation process of next piece in macro block simultaneously.
7. motion compensation structure according to claim 6, it is characterized in that: the write operation direction of described upper adjacent two pieces of transpose memory should be mutually orthogonal, can not cover wherein not yet the intermediate data of a upper piece of being processed by vertical filter to the write operation of transpose memory to guarantee horizontal filter.
8. motion compensation structure according to claim 6, it is characterized in that: the filtering operation of described restructural interpolation filter is converted into the vector zoom operations, the filter construction that has adopted arithmetic element to share mainly is made of pre-calculation unit Precomputer and addition shift unit SAU.Pre-calculation unit is completed the calculating of intermediate object program (i.e. the product of input and alpha operand), intermediate object program is shared by 8 SAU, the SAU unit carries out for intermediate object program the calculating that final interpolation result is completed in addition and shifting function, and SAU carries out dynamic reconstruct for different video encoding standards in the unit.
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| CN108322758A (en) * | 2018-01-12 | 2018-07-24 | 深圳市德赛微电子技术有限公司 | Motion compensation structure in multimode Video Decoder |
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Application publication date: 20130515 |