CN104754363B - Loop circuit filtering method and device, encoder and decoder for HEVC - Google Patents

Loop circuit filtering method and device, encoder and decoder for HEVC Download PDF

Info

Publication number
CN104754363B
CN104754363B CN201310754390.7A CN201310754390A CN104754363B CN 104754363 B CN104754363 B CN 104754363B CN 201310754390 A CN201310754390 A CN 201310754390A CN 104754363 B CN104754363 B CN 104754363B
Authority
CN
China
Prior art keywords
filtering
module
data
memory module
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310754390.7A
Other languages
Chinese (zh)
Other versions
CN104754363A (en
Inventor
王森
林福辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spreadtrum Communications Shanghai Co Ltd
Original Assignee
Spreadtrum Communications Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spreadtrum Communications Shanghai Co Ltd filed Critical Spreadtrum Communications Shanghai Co Ltd
Priority to CN201310754390.7A priority Critical patent/CN104754363B/en
Publication of CN104754363A publication Critical patent/CN104754363A/en
Application granted granted Critical
Publication of CN104754363B publication Critical patent/CN104754363B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

A kind of loop circuit filtering method and device, encoder and decoder for HEVC, described device includes:First memory module, the data suitable for storing the horizontal filtering of lastrow above current CTU;Second memory module, suitable for the storage column data of current CTU lefts rightmost 4;3rd memory module, suitable for storing the data without block-eliminating effect filtering;Module for reading and writing, suitable for reading data formation deblocking effect elementary cell from first, second, third memory module and storing to the first registration module;The data of the filtered deblocking effect elementary cell stored in first registration module are write into corresponding memory module;First registration module, suitable for the deblocking effect elementary cell before and after storage filtering;First filtering operation module, suitable for being filtered to the deblocking effect elementary cell in the first registration module, and is exported to the first registration module;First control module, suitable for dispatching and controlling module for reading and writing and the first filtering operation module.The scheme can reduce hardware spending.

Description

Loop circuit filtering method and device, encoder and decoder for HEVC
Technical field
It is used for high efficiency Video coding the present invention relates to technical field of video coding, more particularly to one kind(High Efficiency Video Coding, HEVC)Loop circuit filtering method and device, encoder and decoder.
Background technology
HEVC is by International Telecommunication Union(International Telecommunication Union, ITU)And motion Motion picture expert group version(Moving Picture Experts Group, MPEG)The International video of future generation coding mark that joint is formulated It is accurate.With existing international standard H.264/AVC compared with, HEVC ensure picture quality on the premise of, can be by the code check of video Reduction by 50%, that is to say, that H.264 twice of code efficiency can be reached.
HEVC is as video compression standard of new generation, because its superior compression performance, is widely used in ultra high-definition In video.HEVC is while compression ratio is improved, and its computational complexity also accordingly increases.Also, because ultra high-definition video image Resolution ratio with 4Kx2K pixels, is 1080P 4 times of pixels, and it needs data volume to be processed very big, and so high computing is answered Miscellaneous degree and data volume propose high requirement to the performance of each modules of HEVC.
HEVC is a kind of video coding and decoding system predicted based on block with transition coding, can be occurred on the border of block discontinuous Phenomenon, this phenomenon is called blocking effect.In order to reduce blocking effect, block elimination effect filter has been used in HEVC.It is existing to go In block effect filtering device framework, in order to reach resolution ratio, the 30fps frame rate of 4Kx2K pixels, multiple deblocking effects are employed Filtering operation unit parallel processing, and improve using polylith dual port RAM reading and writing data speed.
Such scheme is due to needing the parallel block-eliminating effect filtering arithmetic element of many sets and the storage of polylith dual port random access Device(Random Access Memory, RAM), therefore hardware spending is larger.
The content of the invention
The problem of embodiment of the present invention is solved is how in the case where ensureing identical frame rate, to reduce hardware spending.
To solve the above problems, the embodiments of the invention provide a kind of loop filter for HEVC, described device Including:
First memory module, the data suitable for storage present encoding tree unit CTU top lastrows horizontal filtering;
Second memory module, suitable for the storage column data of current CTU lefts rightmost 4;
3rd memory module, suitable for storing the data handled without block-eliminating effect filtering;
Module for reading and writing, suitable for read-write data, the read-write data include:Read from first, second, third memory module Access is according to formation deblocking effect elementary cell and stores to the first registration module;The filter that will be stored in first registration module The data of deblocking effect elementary cell after ripple write corresponding memory module;Wherein:The deblocking effect elementary cell includes 3 The first row data that row 2 is arranged in the data block of 6 4x4, the current deblocking effect elementary cell totally come from the first memory module, Second, third row data in the deblocking effect elementary cell come from the 3rd memory module, and are current CTU when reading data During first row, the first column data of second, third row comes from second memory module in the deblocking effect elementary cell;
First registration module, with filtered deblocking effect elementary cell before being filtered suitable for storage;
First filtering operation module, suitable for the deblocking effect elementary cell in first registration module according to first to hang down Block-eliminating effect filtering is carried out to the order of horizontal boundary after straight boundary, and exported to first registration module;
First control module, suitable for dispatching and controlling the module for reading and writing read-write data and the first filtering operation module to be entered Row block-eliminating effect filtering computing.
Optionally, first registration module includes:First register and the second register, are respectively adapted to before storage filtering With filtered deblocking effect elementary cell;First control module is further adapted for control first register and the second deposit Data exchange between device.
Optionally, described device also includes:First configuration module, the ginseng suitable for configuring the first filtering operation module Number.
Optionally, described device also includes:4th memory module, the deblocking suitable for storing the first module for reading and writing output The filtered data of effect.
Optionally, first, second, third, fourth memory module is SRAM.
Optionally, described device also includes:
5th memory module, the row data of inverse the 5th suitable for storing the current upper CTU row of CTU;
6th memory module, suitable for storing the right row of number the 5th to 12 of current CTU left sides CTU totally 8 column data;
Read module, suitable for reading data from the four, the five, the 6th memory module, forms a pixel adaptive Filter row;
Second registration module, suitable for 4 continuous pixel adaptive-filtering rows of storage;
3rd control module, the displacement storage suitable for controlling the pixel adaptive-filtering row in second registration module;
Second filtering operation module, for carrying out pixel adaptive-filtering, including at least two parallel processings pixel from Adaptive filtering unit;
Second control module, suitable for dispatching and controlling the read module to read data, dispatches and controls the 3rd control Molding block is to the pixel adaptive-filtering traveling every trade displacement storage operation in second register, and scheduling and control institute State the second filtering operation module and carry out pixel adaptive-filtering.
Optionally, the pixel adaptive-filtering row includes 10 pixels, the read module, suitable for the pixel from When adaptation pixel column is 0 row, read from the 5th memory module;When being non-zero row, read columns is judged, if It is the 0th row, is read from the 6th memory module, if the 1st row, preceding 5 pixels is from the 6th memory module, latter 5 Pixel is read from the 4th memory module;Otherwise, read from the 4th memory module.
Optionally, the second filtering operation module includes the pixel adaptive-filtering unit of 4 parallel processings.
Optionally, described device also includes:Second configuration module, the filtering suitable for configuring the second filtering operation module Parameter.
Optionally, described device also includes:7th memory module, suitable for storing the second filtering operation module output Filtering data.
To solve the above problems, the embodiment of the present invention additionally provides a kind of video encoder, including above-mentioned it is used for HEVC Loop filter.
To solve the above problems, the embodiment of the present invention additionally provides a kind of Video Decoder, including above-mentioned it is used for HEVC Loop filter.
To solve the above problems, the embodiment of the present invention additionally provides a kind of loop circuit filtering method for HEVC, the side Method includes:
Respectively data formation deblocking effect elementary cell, the deblocking effect are read from first, second, third memory module Elementary cell includes the data block that 3 rows 2 arrange totally 6 4x4, and the read-write data include:Read from first memory module Data are used as the first row in the block-eliminating effect filtering unit;When it is current CTU first rows to read data, from described second Data are read in memory module as the first column data of second, third row in the deblocking effect elementary cell;When reading number During according to first row non-for current CTU, data are read as in the deblocking effect elementary cell from the 3rd memory module Second, third row data;Wherein:First memory module is stored with the data of the horizontal filtering of lastrow above current CTU, Second memory module is stored with the column data of current CTU lefts rightmost 4, and the 3rd memory module was stored with without the past The data of block effect filtering processing;
The deblocking effect elementary cell for reading data formation from first, second, third memory module respectively is stored into the One registration module;
From first registration module read deblocking effect elementary cell, and according to first to after vertical boundary to horizontal boundary Order carry out block-eliminating effect filtering, and export to first registration module;
The data in deblocking effect elementary cell after the filtering process that will be stored in first registration module are write out To corresponding memory module.
Optionally, first registration module includes the first register and the second register, and the loop circuit filtering method is also Including:By the unfiltered deblocking effect elementary cell stored in first register and the filter stored in the second register The deblocking effect elementary cell of ripple carries out data exchange.
Optionally, in the deblocking effect elementary cell after the filtering process that will be stored in first registration module Data be writen to corresponding memory module, including:
Second, third row output in the filtered deblocking effect elementary cell that first registration module is stored To the 4th memory module;
By the third line data storage in the filtered deblocking effect elementary cell of first registration module storage extremely First memory module;
By second in second and third row in the filtered deblocking effect elementary cell of first registration module storage Column data is stored to second memory module.
Optionally, methods described also includes:
Respectively from the 4th memory module, and the five, the 6th memory modules read data, form a pixel adaptive Answer filter row;
The pixel adaptive-filtering row read is carried out to be stored into the second registration module, 4 continuous pixels are formed certainly Adaptive filtering row;
Carried out using the second filtering operation module in pixel adaptive-filtering, the second filtering operation module comprising at least The pixel adaptive-filtering unit of two parallel processings.
Optionally, it is described to read data from the 4th memory module, and the five, the 6th memory modules respectively, formed One pixel adaptive-filtering row, including:
When the adaptive pixel column of the pixel is 0 row, read from the 5th memory module;When being non-zero row, institute is judged The columns of reading, if the 0th row, read from the 6th memory module, if the 1st row, preceding 5 pixels store mould from the 6th Block, rear 5 pixels are read from the 4th memory module;Otherwise, read from the 4th memory module.
Optionally, the progress pixel adaptive-filtering, including:Using 4 parallel pixel adaptive-filtering units pair The data of input carry out pixel adaptive-filtering and exported.
Compared with prior art, the technical scheme of the embodiment of the present invention has advantages below:
Deposited by reading data formation deblocking effect elementary cell from first, second, third memory module respectively in advance Enter the first registration module, and using deblocking effect elementary cell as basic filtering unit, to the deblocking effect elementary cell according to First to carrying out block-eliminating effect filtering after vertical boundary to the order of horizontal boundary, and by filtered data transfer to described first Data block in registration module, the filtered deblocking effect elementary cell for afterwards storing first registration module is write out To corresponding memory module, due to carrying out the read-write of data by being multiplexed first, second memory module and the first registration module Operation, whole filtering only need to be using a block-eliminating effect filtering computing module(That is the first filtering operation module), Yi Jiyi Cover single port memory module(Including first, second, third memory module), in the filtering operation module using same clock frequency Under the premise of, you can identical frame rate is realized, therefore hardware spending can be saved, hardware cost is reduced.
Further, with filtered deblocking effect base before being filtered by using the first register and the storage of the second register This unit, by directly carrying out data friendship to the deblocking effect elementary cell stored in first register and the second register Operation is changed, by increasing a register, micro hardware spending is increase only, data read time can be saved, is being used On the premise of the filtering operation module of same clock frequency, double frame rate.
By reading data from the 4th memory module, and the five, the 6th memory modules, form a pixel and adaptively filter Ripple row is stored in the second registration module, and passes through the cyclic shift of pixel adaptive-filtering row so that the reading speed of read module It is consistent with the filtering speed of the second filtering operation module, in the feelings of the pixel adaptive-filtering arithmetic element using same frequency Under condition, it is only necessary to which a small amount of pixel adaptive-filtering unit carries out parallel processing, you can reaches identical frame rate, therefore can subtract Few hardware spending.
When carrying out parallel processing using 4 adaptive-filtering arithmetic units in the second filtering operation module, it can make Reading speed and filtering operation speed Complete Synchronization, in the case of using the pixel adaptive-filtering arithmetic unit of same frequency, With less hardware costs, frame rate can be doubled.
Brief description of the drawings
Fig. 1 is the structural representation for the loop filter for being used for HEVC in the embodiment of the present invention;
Fig. 2 is the schematic diagram of block-eliminating effect filtering data in the embodiment of the present invention;
Fig. 3 is the flow chart for the loop circuit filtering method for being used for HEVC in the embodiment of the present invention;
Fig. 4 is the structural representation for the loop filter for being used for HEVC in the embodiment of the present invention;
Fig. 5 is the schematic diagram of pixel adaptive-filtering order in the embodiment of the present invention;
Fig. 6 is the flow chart for the loop circuit filtering method for being used for HEVC in the embodiment of the present invention.
Embodiment
HEVC is a kind of video coding and decoding system predicted based on block with transition coding, can be occurred on the border of block discontinuous Phenomenon, this phenomenon is called blocking effect.It has been investigated that, blocking effect Producing reason has two, and one is when quantifying at piecemeal Quantization relative coarseness during reason, makes decoder carry error in the conversion coefficient of inverse quantization recovery process, and another is fortune The error of data when different piecemeals enter row interpolation using the reference block data of diverse location during dynamic compensation, this can all cause image to exist Piecemeal is easily visual discontinuous, and in order to reduce this blocking effect, corresponding wave filter has been used in HEVC.It is existing In block elimination effect filter framework, for the image of the resolution ratio of 4Kx2K pixels, in order to reach the frame rate of 30 frames/second, use Multiple block-eliminating effect filtering arithmetic element parallel processings, and reading and writing data speed is improved using polylith dual port RAM, hardware is opened Pin is larger.
To solve the above problems, in the embodiment of the present invention, by advance respectively from first, second, third memory module Data formation deblocking effect elementary cell is read, the first registration module is stored in, and using deblocking effect elementary cell as basic filtering Unit, to the deblocking effect elementary cell according to first to carrying out deblocking effect filter to the order of horizontal boundary after vertical boundary Ripple, and by filtered data transfer to first registration module, the filtering for afterwards storing first registration module The data block in deblocking effect elementary cell afterwards is writen to corresponding memory module.In whole process, pass through multiplexing first, the Two memory modules and the read-write operation that data are carried out using the first registration module, whole filtering only need to be using a deblocking Effect filtering operation module(That is the first filtering operation module), and a set of single port memory module(Including first, second, third Memory module), on the premise of using the filtering operation module of same clock frequency, you can realize identical frame rate, therefore Hardware spending can be saved, hardware cost is reduced.
It is understandable to enable the above-mentioned purpose of the embodiment of the present invention, feature and advantage to become apparent, it is right below in conjunction with the accompanying drawings The specific embodiment of the present invention is described in detail.
The structural representation of the loop filter for HEVC shown in reference picture 1, the loop filter includes First memory module 11, the second memory module 12, the 3rd memory module 13, module for reading and writing 14, the filter of the first registration module 15, first The control module 17 of ripple computing module 16 and first, wherein:
First memory module 11, suitable for storage present encoding tree unit(Coding Tree Unit, CTU)Top lastrow Data of horizontal filtering;
Second memory module 12, suitable for the storage column data of current CTU lefts rightmost 4;
3rd memory module 13, suitable for storing the data handled without block-eliminating effect filtering;
Module for reading and writing 14, suitable for read-write data, the read-write data include:From first, second, third memory module 11st, 12,13 data formation deblocking effect elementary cell is read, and by the CTU data storages read to the first registration module 11; Data block write-in in the filtered deblocking effect elementary cell that will be stored in first registration module 15 is deposited accordingly Store up module;
First registration module 15, with filtered deblocking effect elementary cell before being filtered suitable for storage;
First filtering operation module 16, suitable for the deblocking effect elementary cell in the first registration module 15 according to first to hang down Block-eliminating effect filtering is carried out to the order of horizontal boundary after straight boundary, and exported to the first registration module 15;
First control module 17, suitable for dispatching and controlling the read-write data of module for reading and writing 14 and the first filtering operation module 16 Carry out block-eliminating effect filtering computing.
Wherein, CTU is the basic coding unit in HEVC, and CTU maximums support 64x64 block(Coding Unit, CU), each CU is 4x4 block.The schematic diagram of block-eliminating effect filtering data shown in reference picture 2, wherein, CTU21,22, 23 numbers comprising CU are followed successively by 32x32,16x16,16x16.To carry out block-eliminating effect filtering to the CTU, of the invention real Apply in example, using a deblocking effect elementary cell as a basic filter unit, as shown in Fig. 2 deblocking effect is basic Unit 24 can include the data block that 3 rows 2 arrange totally 6 4x4:Block 0 is to block 5.
Block-eliminating effect filtering unit 24 is described in detail below in conjunction with Fig. 1 and Fig. 2:Current deblocking effect elementary cell The first row data in 24, i.e. block 0 and block 1, can come from the first memory module 11, current deblocking effect elementary cell 24 Second, third row data, i.e. block 2 can come from the 3rd memory module 13, or be simultaneously from the second memory module 12 to block 5 With the 3rd memory module 13.In embodiments of the present invention, when it is current CTU first rows to read data, deblocking effect is substantially single First column data of second, third row, i.e. block 2 and block 4 in member 24;The of second, third row in deblocking effect elementary cell 24 Two column datas, i.e. block 3 and block 5, from the 3rd memory module 13.
The flow chart of the loop circuit filtering method for HEVC shown in reference picture 3, illustrates above-mentioned below by way of idiographic flow Operation principle for HEVC loop filter:
S31, reads data formation deblocking effect elementary cell from first, second, third memory module 11,12,13 respectively 24。
Reference picture 2, block-eliminating effect filtering elementary cell 24 includes the data block that 3 rows 2 arrange totally 6 4x4, i.e. block 0 to block 5. Specific read method is as follows in the present embodiment:Data are read from the first memory module 11 and are used as the block-eliminating effect filtering unit The first row in 24, i.e., as block 0 and block 1.When it is current CTU first rows to read data, read from the second memory module 12 Access is according to the first column data as second, third row in deblocking effect elementary cell 24, i.e. block 2 and block 4, from the 3rd storage mould Data are read in block 13 as the second column data of second, third row in deblocking effect elementary cell 24, i.e. block 3 and block 5;Work as reading When access is according to first row non-for current CTU, data are read as in deblocking effect elementary cell 24 from the 3rd memory module 23 Second, third row data, i.e. block 2, block 3, block 4 and block 5.
In specific implementation, first, second, third memory module 11,12,13 can be delayed using SRAM as on piece Deposit.
Wherein, the first memory module 11 is stored with the data of the horizontal filtering of lastrow above current CTU, the second storage mould Block 12 is stored with the column data of current CTU lefts rightmost 4, and the 3rd memory module 13 is stored with to be handled without block-eliminating effect filtering Data.In 3rd memory module 13 undressed data may be from upper level hardware module handled without the past The reconstruction data of block effect filtering or the reconstruction data without block-eliminating effect filtering read in outside piece.
S32, will read the deblocking effect base of data formation from first, second, third memory module 11,12,13 respectively This unit 24 is stored into the first registration module 15.
S33, the deblocking effect elementary cell 24 of non-filtered processing is read from the first registration module 15, according to first to vertical Block-eliminating effect filtering is carried out to the order of horizontal boundary behind border, and exported to first registration module.
Reference picture 2, vertical overstriking solid line 28 therein represents the vertical boundary for needing to carry out horizontal filtering, and horizontal overstriking is empty Line 29 represents the horizontal boundary for needing to carry out vertical filtering.In the embodiment of the present invention, i.e., a deblocking effect first to being read The vertical boundary represented by vertical overstriking solid line 28 in elementary cell 24, after to the water in the deblocking effect elementary cell 24 The order of horizontal boundary represented by flat overstriking dotted line 29, carries out block-eliminating effect filtering.
The data in deblocking effect elementary cell 24 after S34, the filtering process that will be stored in the first registration module 15 It is writen to corresponding memory module.
In specific implementation, the data after the filtering process that will can be stored in the first registration module 15 are directly exported, It can also keep in, the data are further processed for rear class hardware module, for example, further making to the data Adaptive-filtering processing.
In embodiments of the present invention, the filtered deblocking effect elementary cell that the first registration module 15 can be stored Data, i.e. block 0 are exported to the 4th memory module 18, the filtered deblocking effect that the first registration module 15 is stored to block 5 The third line data in elementary cell 24, i.e. block 4 and block 5 are stored to the first memory module 11, and the first registration module 15 is stored The second column data in filtered deblocking effect elementary cell 24 in second and third row, i.e. block 3 and block 5, store to second and deposit Store up module 12.
From above-described embodiment as can be seen that due to reading number from first, second, third memory module 11,12,13 respectively The first registration module 15 is stored according to deblocking effect elementary cell 24 is formed, and it is single for basic filtering with deblocking effect elementary cell 24 Position, to the deblocking effect elementary cell 24 according to first to carrying out deblocking effect filter to the order of horizontal boundary after vertical boundary Ripple, and by filtered data transfer to first registration module 15, afterwards store first registration module 15 Data block in filtered deblocking effect elementary cell is writen in corresponding memory module, whole process, passes through multiplexing the First, the second memory module 11,12,13 and the first registration module 15 carry out the read-write operation of data, and whole filtering is only needed Using a filtering operation module(That is the first filtering operation module 16), and a set of single port memory module(Including first, 2nd, the 3rd memory module 11,12,13), under conditions of the filtering operation module using same clock frequency, it is possible to achieve phase Same frame rate.
For example, it is existing it is usual use two or four clock frequency for 200MHz or so block-eliminating effect filtering unit simultaneously Row is performed.In embodiments of the present invention, only with the block-eliminating effect filtering computing module that a clock frequency is 200MHz, for One deblocking effect elementary cell, reading needs 16 cycles(cycle), computing need 16 cycle, 32 are needed altogether cycle.And for a size is 32x32 CTU, a total of 24 deblocking effect elementary cells need processing, that is, need Will:24x32=768 cycle, if the resolution ratio of 4Kx2K pixels, 30fps frame rate are reached, to each 32x32 CTU When requirement be 200M/(30x(4Kx2K)/(32x32))=856 cycle, more than 768 cycle of actual consumption, therefore Resolution ratio, the frame rate of 30 frames/second of 4Kx2K pixels can be realized, therefore hardware spending can be saved, hardware cost is reduced.
In specific implementation, the first registration module 15 in the embodiment of the present invention can also may be used only with a register With using two registers, as shown in figure 1, the first registration module 15 can include the first register 151 and the second register 152, it is respectively adapted to before storage filtering and filtered deblocking effect elementary cell 24., can be directly by institute in specific implementation State the unfiltered deblocking effect elementary cell stored in the first register and the deblocking filtered stored in the second register Effect elementary cell carries out data exchange.Correspondingly, the first control module 17 is further adapted for control first register 151 and the Data exchange between two registers 152, to accelerate read or write speed, improves the filtration efficiency of the loop filter, passes through The setting of the above-mentioned register 152 of first register 151 and second, increase only a register, can be with less hardware generation Valency, the frame rate of the loop filter is doubled.For the filter that preceding clock frequency is 200MHz, you can Reach resolution ratio, the 60fps frame rate of 4Kx2K pixels.
Above-described embodiment is related generally to pair using the filtering method of the loop filter for HEVC of two registers The read-write operation of data, and specific block-eliminating effect filtering process:
Read-write operation:If the data in the first register 151 are the data after block-eliminating effect filtering, by block 0 to block 5 It is written in the 4th memory module 18, while block 4 and block 5 are written in the first memory cell 11;If described first, second, The data of reading also in need in three memory modules 11,12,13, then read data from the 3rd memory cell 13 and be used as block 3 and block 5 To the first register 151, reading data are used as block 2 and block 4 to the first from the second memory module 12 or the 3rd memory module 13 Register 151, reads data from the first memory module and is used as block 0 and the register of block 1 to the first 151.
When having valid data in the first register 151, that is, during the deblocking effect elementary cell that is stored with, Ke Yihe Second register 152 carry out data exchange, unfiltered data is transmitted to the second register 152, by filtering data transmit to First register 151.
Filtering operation:If during the deblocking effect elementary cell that is stored with the second register 152, the first filtering operation Unit can carry out block-eliminating effect filtering to the deblocking effect elementary cell.
After a deblocking effect elementary cell has been handled, then next deblocking effect elementary cell is handled, Complete and export until all deblocking effect elementary cells are filtered.Wherein, the process of block-eliminating effect filtering and above-mentioned reading Concurrent process execution is write, therefore processing speed can be improved.
As shown in figure 1, in specific implementation, the loop filter can also include the first configuration module 19, be suitable to Configure the parameter of the first filtering operation module, such as boundary filtering strength(Boundary filtering Strength, BS), quantization parameter(Quantization Parameter, Qp)Deng block-eliminating effect filtering parameter, so as to according to actual feelings Condition, carries out corresponding configuration to above-mentioned parameter, realizes more preferable filtering performance, repeat no more here.
It has been investigated that, because HEVC employs bigger transform size(Maximum supports 32x32)Inserted with more interframe It is worth tap number, wherein brightness uses 8 taps(8-tap), colourity uses 4-tap, can introduce more ringing effects(Ringing Artifacts), to reduce this effect, picture quality is further improved, pixel further can also be carried out to it and adaptively filtered Ripple.
A kind of pixel sef-adapting filter framework using 8x8 as elementary cell is employed in the prior art, and it is used largely Register store the pixel on 8x8 borders, and using 64 pixel adaptive-filtering arithmetic element parallel computations, hardware spending It is very big.
To solve the above problems, the embodiment of the present invention provides a kind of loop filter for HEVC, using based on capable Pixel sef-adapting filter framework, in the case where using seldom pixel adaptive-filtering arithmetic element parallel, in filtering dress In the case of putting with same clock frequency, you can realize same frame rate.
The structural representation of loop filter shown in reference picture 4, for clarity, only shows the loop in Fig. 4 The structural representation for newly increasing part of filter, the loop filter may include:
4th memory module 41, the input data suitable for storing pixel adaptive-filtering;
5th memory module 42, the row data of inverse the 5th suitable for storing the current upper CTU row of CTU;
6th memory module 43, suitable for storing the right row of number the 5th to 12 of current CTU left sides CTU totally 8 column data;
Reading unit 44, suitable for reading data from the four, the five, the 6th memory module 41,42,43, forms one Pixel adaptive-filtering row;
Second registration module 45, suitable for 4 continuous pixel adaptive-filtering rows of storage;
3rd control module 46, suitable for controlling the pixel adaptive-filtering traveling every trade in second registration module 45 to move Position storage operation;
Second filtering operation module 47, for carrying out pixel adaptive-filtering;
Second control module 48, for dispatching and controlling the read module 44 to read data and the second filtering fortune Calculate module and carry out pixel adaptive-filtering.
The second filtering operation module 47 includes the pixel adaptive-filtering unit of at least two parallel processing.
In specific implementation, what is stored in the 4th memory module 41 treats that pixel adaptive-filtering data can come from deblocking effect The output of wave filter is answered, such as can be that module for reading and writing 14 writes out data in embodiment illustrated in fig. 1, in other words, shown in Fig. 4 The 4th memory module 18 in 4th memory module 41 and Fig. 1 is same memory module.
In specific implementation, read module 44 can be first according to CTU size, the columns of processing needed for calculating, with And pending line number in each column, it is possible to the ranks number selection according to being read is read to be filtered from corresponding memory module OK, each pixel adaptive-filtering row has 10 pixels in the present embodiment, can specifically be performed according to following rule:If the 0 row, reads from the 5th memory module 42;If non-zero row, judge read columns, if the 0th row, all data from 6th memory module 43 is read, if the 1st row, preceding 5 pixels are deposited from the 6th memory module 43, rear 5 pixels from the 4th Storage module 41 is read;Otherwise, all pixels are read from the 4th memory module 41.
Second registration module 45 can use a 4 row registers, and often row can deposit 10 pixels, read module 44 1 One pixel column of secondary reading, and store into the second registration module 45, when the pixel column stored in the second registration module 45 has 3 rows When, the second filtering operation module 47 can read data from the second registration module 45, carry out pixel adaptive-filtering, specifically , at least 1 row data stored in second registration module 45 can be located line by line in accordance with the order from top to bottom Reason, has handled a row and has carried out the filter sequence progress pixel adaptive-filtering of next column again and export.
In specific implementation, pixel column circulation in this 4 row register can be controlled to move using the 3rd control module 46 Position storage operation, make it that the filtering operation of the second filtering operation module 47 is operated and the read operation of the read module 44 can With parallel processing, data-handling efficiency is improved.
In embodiments of the present invention, to reduce hardware spending, as far as possible few pixel adaptive-filtering unit can be used Number.Second filtering operation module 47 can carry out parallel processing using 2 pixel adaptive-filtering units, it would however also be possible to employ 4 Individual pixel adaptive-filtering unit carries out parallel processing.
Specifically, when carrying out parallel processing using 2 pixel adaptive-filtering units, due to real in each pixel column Border has 8 pixels to be the data for needing to filter, and each pixel adaptive-filtering unit once can be only in a pixel, for Each pixel column is, it is necessary to which 2 clock cycle could handle need 8 pixels to be processed, and correspondingly, read module 44 can be with every Two clock cycle read a pixel column.
And if carrying out parallel processing using 4 pixel adaptive-filtering units, then only need to a clock cycle Having handled a pixel column needs 8 pixels to be processed, correspondingly, and read module 44 can read one with each clock cycle Pixel column, so as to when whole HEVC loop filters pixel adaptive-filtering efficiency double, it is hard in a small amount of increases In the case of part expense, systematic function greatly improved.
For example, 200MHz filter is similarly for clock frequency, if using 2 pixel adaptive-filtering units Parallel processing, for the image of 4Kx2K pixel resolutions, can reach 30fps frame rate, if adaptive using 4 pixels Filter unit parallel processing is answered, for the image of the resolution ratio of 4Kx2K pixels, 60fps frame rate can be reached.
In specific implementation, the loop filter in the embodiment of the present invention for HEVC may also include:Second configuration mould Block 49, the filtering parameter suitable for configuring the second filtering operation module 47, configuration parameter includes pixel sef-adapting filter Type(SAO type), the skew of pixel adaptive-filtering(SAO offset)Deng.If if edge offset filtering, also having Edge type(EO class), if if band bending filtering, also frequency band original position(band position).
In specific implementation, the loop filter in the embodiment of the present invention for HEVC may also include:7th storage mould Block 50, the filtering data suitable for storage the second filtering operation module 47 output.
In specific implementation, the four, the five, the six, the 7th memory module can be using SRAM etc. as on piece Caching.
The flow chart of loop circuit filtering method shown in reference picture 6, the embodiment of the present invention is described in detail below in conjunction with flow chart Filtering method:
S61, reads data from the four, the five, the 6th memory modules 41,42,43 respectively, forms a pixel and adaptively filters Ripple row;
, can be according to CTU size in specific implementation, the columns of processing needed for calculating, and in each column it is pending Line number, then reads corresponding pixel column from the four, the five, the 6th memory modules 41,42,43 respectively.In specific implementation, Each pixel column can have 10 pixels, wherein having 8 to need the pixel of adaptive-filtering.Specifically can be according to following rule Read:
1)If the 0th row, read from the 5th memory module 42;
2)Otherwise,
I) if the 0th row, all data are read from the 6th memory module 43;
Ii) if the 1st row, preceding 5 data read from the 6th memory module 43, rear 5 data are from the 4th memory module 41 read.
Otherwise, all data are read from the 4th memory module 41.
S62, the second registration module 45 is stored into by the pixel adaptive-filtering row read, forms 4 continuous pixels Adaptive-filtering row;
In specific implementation, to improve filtering speed, it is to avoid data read operation occupancy excessive time or memory space, The 4 row registers that second registration module is used can be stored using such a way:
Assuming that i is the current line number being filtered, and according to the regulation of HEVC standard, the picture for image border part Plain sef-adapting filter includes edge offset(Edge Offset, EO)And bandwidth offset(Band Offset, BO)Two parts, EO Substantially it is the wave filter of a 3x3 template, it is necessary to which two in 8 pixels of surrounding carry out carrying out computing, it is therefore desirable to I-1 rows and i+1 rows, it is also desirable to which j-1 is arranged and j+1 row.
S63, pixel adaptive-filtering is carried out using the second filtering operation module, and the second filtering operation module is included extremely Two pixel adaptive-filtering units of few parallel processing.
Second filtering operation module can in accordance with the order from top to bottom, to the pixel stored in second registration module Adaptive-filtering row data are handled line by line, handled one row carry out again next column filter sequence carry out pixel adaptively filter Ripple is simultaneously exported.
In specific implementation, can using the parallel data processing to be filtered of 2 pixel adaptive-filtering units to input, Pixel adaptive-filtering can also be carried out to the data of input using 4 parallel pixel adaptive-filtering units and exported.
As shown in figure 5, wherein, the columns filtered during 0,1,2,3 expression pixel adaptive-filtering.Arrow table in figure Show and handled line by line using order from top to bottom by the way of carrying out line by line from top to bottom in each column, handled a row again Carry out the order of next column filtering.So, often toward next line, only with data line is updated, so as to improve filtering effect Rate.
The 3rd control module 46 shown in Fig. 4 the line number of the actual pixels row read and 0x3 can be carried out with that is, It can obtain position of the pixel column in the 4 row register in the row register of actual storage.Particularly:Assuming that i-th- The data of 1 row are stored in(i-1)In &0x3 row registers, the data of the i-th row are stored in i&0x3 row registers, i+1 line number According to being stored in(i+1)In &0x3 row registers, this 3 row register is used for carrying out pixel adaptive-filtering, now, the(i+2)& 0x3 rows register is used for carrying out the reading of data, and the data of reading come from the i-th+2 row.
According to above-mentioned shift control rule, the number in the four, the five, the 6th memory modules 41,42,43 can be successively read According to(i+2)&0x3 row registers.Meanwhile, if there are effective data in other 3 row register, carry out pixel and adaptively filter Ripple computing, and export filtered data.If current still have the row for not completing filtering, i is set to i+1, repeated State step.If when all rows in prostatitis have completed pixel adaptive-filtering computing, and also unfiltered row, then i put For 0, the filtering for the beginning next column that repeats the above steps;Otherwise, end pixel adaptive-filtering.
In specific implementation, the loop filter of the HEVC in above-described embodiment is that can be used in video encoder, It can be used in decoder.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can To instruct the hardware of correlation to complete by program, the program can be stored in a computer-readable recording medium, storage Medium can include:ROM, RAM, disk or CD etc..
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (18)

1. a kind of loop filter for HEVC, it is characterised in that including:
First memory module, the data suitable for storage present encoding tree unit CTU top lastrows horizontal filtering;
Second memory module, suitable for the storage column data of current CTU lefts rightmost 4;
3rd memory module, suitable for storing the data handled without block-eliminating effect filtering;
Module for reading and writing, suitable for read-write data, the read-write data include:Number is read from first, second, third memory module Deblocking effect elementary cell and stored according to being formed to the first registration module;After the filtering that will be stored in first registration module The data of deblocking effect elementary cell write corresponding memory module;Wherein:The deblocking effect elementary cell includes 3 rows 2 The first row data arranged in the data block of totally 6 4x4, the current deblocking effect elementary cell come from the first memory module, institute State second, third row data in deblocking effect elementary cell and come from the 3rd memory module, and be current CTU the when reading data During one row, the first column data of second, third row comes from second memory module in the deblocking effect elementary cell;
First registration module, with filtered deblocking effect elementary cell before being filtered suitable for storage;
First filtering operation module, suitable for the deblocking effect elementary cell in first registration module according to first to vertical edges Block-eliminating effect filtering is carried out to the order of horizontal boundary behind boundary, and exported to first registration module;
First control module, suitable for dispatching and controlling the module for reading and writing read-write data and the first filtering operation module to be gone Block effect filtering computing.
2. it is used for HEVC loop filter as claimed in claim 1, it is characterised in that the first registration module bag Include:First register and the second register, are respectively adapted to before storage filtering and filtered deblocking effect elementary cell;
First control module is further adapted for controlling the data exchange between first register and the second register.
3. it is used for HEVC loop filter as claimed in claim 1, it is characterised in that also include:First configuration module, Parameter suitable for configuring the first filtering operation module.
4. the loop filter for HEVC as described in any one of claims 1 to 3, it is characterised in that also include:4th Memory module, the data after block-eliminating effect filtering suitable for storing the module for reading and writing output.
5. it is used for HEVC loop filter as claimed in claim 4, it is characterised in that described first, second, third, 4th memory module is SRAM.
6. it is used for HEVC loop filter as claimed in claim 4, it is characterised in that also include:
5th memory module, the row data of inverse the 5th suitable for storing the current upper CTU row of CTU;
6th memory module, suitable for storing the right row of number the 5th to 12 of current CTU left sides CTU totally 8 column data;
Read module, suitable for reading data from the four, the five, the 6th memory module, forms a pixel adaptive-filtering OK;
Second registration module, suitable for more than 4 continuous pixel adaptive-filtering rows of storage;
3rd control module, the displacement storage suitable for controlling the pixel adaptive-filtering row in second registration module;
Second filtering operation module, is adapted for pixel adaptive-filtering, including the pixel of at least two parallel processings is adaptive Filter unit;
Second control module, suitable for dispatching and controlling the read module to read data, dispatches and controls the 3rd control mould Block is to the pixel adaptive-filtering traveling every trade displacement storage operation in second register, and scheduling and controls described the Two filtering operation modules carry out pixel adaptive-filtering.
7. it is used for HEVC loop filter as claimed in claim 6, it is characterised in that the pixel adaptive-filtering row Including 10 pixels, the read module is suitable to when the adaptive pixel column of the pixel is 0 row, is read from the 5th memory module Take;When being non-zero row, read columns is judged,
If the 0th row, read from the 6th memory module, if the 1st row, preceding 5 pixels are from the 6th memory module, latter 5 Pixel is read from the 4th memory module;Otherwise, read from the 4th memory module.
8. it is used for HEVC loop filter as claimed in claim 6, it is characterised in that the second filtering operation module Include the pixel adaptive-filtering unit of 4 parallel processings.
9. it is used for HEVC loop filter as claimed in claim 6, it is characterised in that also include:Second configuration module, Filtering parameter suitable for configuring the second filtering operation module.
10. it is used for HEVC loop filter as claimed in claim 6, it is characterised in that also include:7th storage mould Block, the filtering data suitable for storing the second filtering operation module output.
11. a kind of video encoder, it is characterised in that including the ring for HEVC as described in any one of claim 1 to 10 Road filter.
12. a kind of Video Decoder, it is characterised in that including the ring for HEVC as described in any one of claim 1 to 10 Road filter.
13. a kind of loop circuit filtering method for HEVC, it is characterised in that including:
Data formation deblocking effect elementary cell is read from first, second, third memory module respectively, the deblocking effect is basic Unit includes the data block that 3 rows 2 arrange totally 6 4x4, and the read data packet is included:Data are read from first memory module It is used as the first row in the block-eliminating effect filtering unit;When it is current CTU first rows to read data, from the described second storage Data are read in module as the first column data of second, third row in the deblocking effect elementary cell;It is when reading data During the non-first row of current CTU, from the 3rd memory module read data as second in the deblocking effect elementary cell, The third line data;Wherein:First memory module is stored with the data of the horizontal filtering of lastrow above current CTU, described Second memory module is stored with the column data of current CTU lefts rightmost 4, and the 3rd memory module is stored with imitates without deblocking Answer the data of filtering process;
The deblocking effect elementary cell for reading data formation from first, second, third memory module respectively is stored into first to post Storing module;
From first registration module read deblocking effect elementary cell, and according to first to after vertical boundary to the suitable of horizontal boundary Sequence carries out block-eliminating effect filtering, and exports to first registration module;
The data in deblocking effect elementary cell after the filtering process that will be stored in first registration module are writen to phase The memory module answered.
14. it is used for HEVC loop circuit filtering method as claimed in claim 13, it is characterised in that the first registration module bag The first register and the second register are included, the loop circuit filtering method also includes:Do not filtered what is stored in first register The deblocking effect elementary cell filtered stored in the deblocking effect elementary cell and the second register of ripple carries out data exchange.
15. it is used for HEVC loop circuit filtering method as claimed in claim 13, it is characterised in that described to be deposited described first The data in deblocking effect elementary cell after the filtering process stored in module are writen to corresponding memory module, including:
Second, third row in the filtered deblocking effect elementary cell that first registration module is stored is exported to the Four memory modules;
The third line data storage is to described in the filtered deblocking effect elementary cell that first registration module is stored First memory module;
The second columns in the filtered deblocking effect elementary cell that first registration module is stored in second and third row According to storing to second memory module.
16. it is used for HEVC loop circuit filtering method as claimed in claim 15, it is characterised in that also include:
Respectively from the 4th memory module, and the five, the 6th memory modules read data, form a pixel and adaptively filter Ripple row;
The pixel adaptive-filtering row read is carried out to be stored into the second registration module, the continuous pixel of at least four is formed certainly Adaptive filtering row;
Carry out including at least two in pixel adaptive-filtering, the second filtering operation module using the second filtering operation module The pixel adaptive-filtering unit of parallel processing.
17. it is used for HEVC loop circuit filtering method as claimed in claim 16, it is characterised in that described respectively from the described 4th Memory module, and the five, the 6th memory modules read data, form a pixel adaptive-filtering row, including:
When the adaptive pixel column of the pixel is 0 row, read from the 5th memory module;When being non-zero row, institute is judged The columns of reading, if the 0th row, read from the 6th memory module,
If the 1st row, preceding 5 pixels are read from the 6th memory module, rear 5 pixels from the 4th memory module Take;Otherwise, read from the 4th memory module.
18. it is used for HEVC loop circuit filtering method as claimed in claim 16, it is characterised in that the carry out pixel is adaptive Filtering, including:
Pixel adaptive-filtering is carried out to the data of input using 4 parallel pixel adaptive-filtering units and exported.
CN201310754390.7A 2013-12-31 2013-12-31 Loop circuit filtering method and device, encoder and decoder for HEVC Active CN104754363B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310754390.7A CN104754363B (en) 2013-12-31 2013-12-31 Loop circuit filtering method and device, encoder and decoder for HEVC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310754390.7A CN104754363B (en) 2013-12-31 2013-12-31 Loop circuit filtering method and device, encoder and decoder for HEVC

Publications (2)

Publication Number Publication Date
CN104754363A CN104754363A (en) 2015-07-01
CN104754363B true CN104754363B (en) 2017-08-08

Family

ID=53593369

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310754390.7A Active CN104754363B (en) 2013-12-31 2013-12-31 Loop circuit filtering method and device, encoder and decoder for HEVC

Country Status (1)

Country Link
CN (1) CN104754363B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110213579A (en) * 2019-06-11 2019-09-06 上海富瀚微电子股份有限公司 The method of double-core computing unit realization loop filtering

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107124608A (en) * 2016-02-24 2017-09-01 北京数码视讯科技股份有限公司 A kind of coding method and device
CN110121069B (en) * 2019-06-27 2021-06-11 上海富瀚微电子股份有限公司 HEVC loop filtering method based on cross word boundary

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921625A (en) * 2006-09-15 2007-02-28 清华大学 Filtering method and system of deblocking effect filter
CN102724512A (en) * 2012-06-29 2012-10-10 豪威科技(上海)有限公司 Loop filter and loop filtering method
CN103220529A (en) * 2013-04-15 2013-07-24 北京大学 Method for achieving video coding and decoding loop filtering
CN103442239A (en) * 2013-08-29 2013-12-11 复旦大学 Deblocking filter hardware on-chip storage method applicable to HEVC standard

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9094658B2 (en) * 2010-05-10 2015-07-28 Mediatek Inc. Method and apparatus of adaptive loop filtering

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921625A (en) * 2006-09-15 2007-02-28 清华大学 Filtering method and system of deblocking effect filter
CN102724512A (en) * 2012-06-29 2012-10-10 豪威科技(上海)有限公司 Loop filter and loop filtering method
CN103220529A (en) * 2013-04-15 2013-07-24 北京大学 Method for achieving video coding and decoding loop filtering
CN103442239A (en) * 2013-08-29 2013-12-11 复旦大学 Deblocking filter hardware on-chip storage method applicable to HEVC standard

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110213579A (en) * 2019-06-11 2019-09-06 上海富瀚微电子股份有限公司 The method of double-core computing unit realization loop filtering

Also Published As

Publication number Publication date
CN104754363A (en) 2015-07-01

Similar Documents

Publication Publication Date Title
CN101127906B (en) Deblocking filter, image encoder, and image decoder
US8494062B2 (en) Deblocking filtering apparatus and method for video compression using a double filter with application to macroblock adaptive frame field coding
KR20060060919A (en) Deblocking filter and method of deblock-filtering for eliminating blocking effect in h.264/mpeg-4
CN104253998B (en) Hardware on-chip storage method of deblocking effect filter applying to HEVC (High Efficiency Video Coding) standard
CN104754363B (en) Loop circuit filtering method and device, encoder and decoder for HEVC
CN101409833B (en) De-block effect filtering device and method
CN100588251C (en) Video data filtering method, device and system
CN101888554B (en) VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter
CN102857758B (en) Reusable pixel processing method and reusable video processing chip
CN101778280B (en) Circuit and method based on AVS motion compensation interpolation
CN102665080B (en) Electronic device for motion compensation and motion compensation method
CN103916612A (en) Random proportion zoom system and method
CN101459839A (en) Deblocking effect filtering method and apparatus for implementing the method
CN102023944A (en) Memory multimode access control method and SRAM memory control system on chip
CN105160622B (en) The implementation method of image super-resolution based on FPGA
JP2007180723A (en) Image processor and image processing method
Fang et al. A hardware-efficient deblocking filter design for HEVC
CN105530519B (en) A kind of intra-loop filtering method and device
EP1725984A1 (en) Electronic device and a method in an electronic device for processing image data
CN103702132B (en) filtering method, device and equipment
CN104754331A (en) Adaptive pixel type filter and filtering method, coder and decoder
CN107135398B (en) Deblocking filtering method, device and system
CN201345710Y (en) Loop filter applicable to video decoding
CN106488163A (en) The method and apparatus of adjustment data array
CN102215404B (en) Decoding method and system of videos inside embedded system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20190314

Address after: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing

Patentee after: Xin Xin finance leasing (Beijing) Co.,Ltd.

Address before: 201203 Shanghai Pudong New Area Pudong Zhangjiang hi tech park, 2288 Chong Nong Road, exhibition center, 1 building.

Patentee before: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd.

TR01 Transfer of patent right
EE01 Entry into force of recordation of patent licensing contract

Application publication date: 20150701

Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd.

Assignor: Xin Xin finance leasing (Beijing) Co.,Ltd.

Contract record no.: X2021110000008

Denomination of invention: Loop filtering method and device, encoder and decoder for hevc

Granted publication date: 20170808

License type: Exclusive License

Record date: 20210317

EE01 Entry into force of recordation of patent licensing contract
TR01 Transfer of patent right

Effective date of registration: 20221017

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech park, Spreadtrum Center Building 1, Lane 2288

Patentee after: SPREADTRUM COMMUNICATIONS (SHANGHAI) Co.,Ltd.

Address before: 101399 Building 8-07, Ronghui Garden 6, Shunyi Airport Economic Core Area, Beijing

Patentee before: Xin Xin finance leasing (Beijing) Co.,Ltd.

TR01 Transfer of patent right