CN103094283B - 8-bit semiconductor memory cell, manufacture method and memory cell array thereof - Google Patents
8-bit semiconductor memory cell, manufacture method and memory cell array thereof Download PDFInfo
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- CN103094283B CN103094283B CN201110332297.8A CN201110332297A CN103094283B CN 103094283 B CN103094283 B CN 103094283B CN 201110332297 A CN201110332297 A CN 201110332297A CN 103094283 B CN103094283 B CN 103094283B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 176
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title description 7
- 238000003860 storage Methods 0.000 claims abstract description 57
- 239000002131 composite material Substances 0.000 claims abstract description 38
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 44
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000007667 floating Methods 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000005452 bending Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
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Abstract
The invention provides a kind of 8-bit semiconductor memory cell and formation method, memory cell array.8-bit semiconductor memory cell comprises a source area, four drain regions, four gate regions, four strip-shaped semiconductor fins and eight charge storage composite beds; Wherein, four drain electrodes are symmetrical arranged outside source electrode, and are provided with the strip-shaped semiconductor fin with channel region between each drain electrode and source electrode; Each of four grids is arranged between every two adjacent strip-shaped semiconductor fins, and grid is by having the channel region contacts between the charge storage composite bed of electric charge capture layer and this grid both sides semiconductor fin.Therefore, utilize the structure that this is brand-new, the 8-bit achieving memory cell cleverly stores, and improves the storage density of memory cell further.
Description
Technical field
The present invention relates to semiconductor memory field, particularly relate to a kind of 8-bit semiconductor memory cell, manufacture method and memory cell array thereof.
Background technology
As the one of semiconductor memory, multi-crystal silicon floating bar memory cell structure (FloatingGate) is widely used.General, 1-bit multi-crystal silicon floating bar memory cell structure 1 comprises active area Semiconductor substrate 2, Semiconductor substrate being formed and comprises source electrode 3 and drain electrode 4, form barrier oxide layer 5, floating boom 6, tunnel oxide 7 and control gate 8 successively on the active area, barrier oxide layer 5, floating boom 6, tunnel oxide 7 form charge storage composite bed 9, as shown in Figure 1.When programming, drain electrode 4 and control gate 8 all add higher program voltage, source electrode 3 ground connection.So a large amount of electronics flows to drain electrode 4 from source electrode 3, form sizable electric current, produce a large amount of hot electron, and from substrate 2 trapped electron, because the density of electronics is large, some electronics just reach between substrate 2 and floating boom 6, at this moment because control gate 8 is added with high voltage, under electric field action, these electronics arrive floating boom 6 by tunnel oxide 7, and form electron cloud on floating boom 6.Information even if the electron cloud on floating boom 6 is when power down, still can remain on floating boom 6, so can be preserved for a long time.
Along with miniaturization, the microminiaturization of semiconductor storage unit, due to multi-crystal silicon floating bar storage organization because laminated thickness is excessive, require too high to tunnel oxide insulating properties and be difficult to adapt to the demand for development of future memory.Based on SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) nonvolatile semiconductor memory member (Non-volatilememory) of the silicon nitride of excellent insulation performance, with its charge storage stronger relative to conventional multi-crystalline silicon floating-gate memory, be easy to realize the characteristics such as miniaturized and technique is simple and again come into one's own.
Shown in structural reference Fig. 2 of conventional 1-bitSONOS memory cell, the gate stack 11 that SONOS memory cell comprises P type semiconductor substrate 10 and is arranged in the presumptive area of this P type semiconductor substrate 10.Source region 12 and drain region 14 are formed in the side place of gate stack 11 in P type semiconductor substrate 10, inject N-type conductive impurity to it.Source region 12 and drain region 14 extend below gate stack 11.Below gate stack 11, channel region 16 is formed between source region 12 and drain electrode 14.The grid conductive layer 26 that gate stack 11 comprises the charge storage composite bed 24 in the presumptive area being formed in the channel region 16 comprising P type semiconductor substrate 10 and is formed on this charge storage composite bed 24, i.e. control gate.The barrier oxidation nitride layer 22 that this memory node 24 comprises tunnel oxide 18 in the presumptive area being formed in the channel region 16 comprising P type semiconductor substrate 10, is formed in the nitride layer 20 in tunnel oxide 18 and is formed on this nitride layer 20.This nitride layer 20 enters electronics in tunnel oxide 18 for capturing tunnelling, and has trap sites within it, forms the electronics 28 be trapped in nitride layer 20.The electronics 28 that barrier oxide layer 22 is used in the nitride layer 20 that prevents from capturing moves to grid conductive layer 26.
Although the memory cell of floating boom and SONOS structure has excellent memory property, but the 1-bit memory cell of routine can not meet in memory capacity, and people are miniaturized to memory, the requirement of large storage capacity, in order to better adapt to practical application, around the improvement of semiconductor memory memory property, especially improve its storage density always by researcher is paid close attention to.
LEEYK, etal.Twin-BitSilicon-Oxide-Nitride-Oxide-Silicon (SONOS) MemorybyInvertedSidewallPatterning (TSM-ISP) IEEETNanotechnology, 2003, 2 (4): 246-252, and LEEYK, etal.TwinSONOSMemorywith30nmStorageNodesunderaMergedGate FabricatedwithInvertedSidewallandDamasceneProcess, IEEEElectrDeviceL, 2004, 25 (5): 317-319 all disclose a kind of 2-bitSONOS memory cell, it utilizes reversing abutment wall shaping (InvertedSide-wallPatterning, ISP), door grid are formed by abutment wall, stop the lateral displacement of both sides electric charge, prevent the electric charge write from influencing each other, achieve the storage of 2-bit.Meanwhile, also having by developing many level (multilevel) technology, by accurately controlling voltage on control gate, realizing a unit in floating gate structure and storing multiple data.
Due to FinFET (FinField-effecttransistor, fin field-effect transistor) invention of structure, cause exploration FinFET being applied in field of storage, as CN1751392A discloses a kind of fin formula field effect transistor memory cell, the method of fin formula field effect transistor memory cell arrangements and manufacture fin formula field effect transistor memory cell, the charge storage layer of the memory cell based on fin formula field effect transistor is configured between the word line regions on area of grid and this area of grid by it, the mode utilizing source side or drain side to inject carries out programming to charge storage layer.
Moreover, SunyeongLee, etal.NonvolatileMemoryCellWithT-GateandI-shapedFinFETStr ucture, IEEETRANSACTIONSONELECTRONDEVICES, VOL.57, NO.8, AUGUST2010, also disclose a kind of 4-bit memory cell utilizing FinFET structure to be formed, it, by structure I type active area and T-shaped grid, achieves the memory cell of 4-bit.
Summary of the invention
The invention provides a kind of 8-bit semiconductor memory cell and formation method, memory cell array, store with the 8-bit realizing memory cell, and improve the storage density of memory cell further.
The technological means that the present invention adopts is as follows: a kind of 8-bit semiconductor memory cell, comprise setting source area on a semiconductor substrate and drain region, semiconductor fin, gate regions, and between described active area and gate regions, the charge storage composite bed with electric charge capture layer, it is characterized in that, described semiconductor memory cell comprises a source area, four drain regions, four gate regions, four strip-shaped semiconductor fins and eight charge storage composite beds;
Wherein, described four drain electrodes are symmetrical arranged outside described source electrode, and are provided with the strip-shaped semiconductor fin with channel region between each described drain electrode and described source electrode;
Each of described four grids is arranged between every two adjacent described strip-shaped semiconductor fins, and described grid pass through described in there is channel region contacts between the charge storage composite bed of electric charge capture layer and this grid both sides semiconductor fin.
Further, described gate regions bending-like at a right angle, and the two ends of described right-angle bending shape grid are by the channel region contacts between described charge storage composite bed and this grid both sides semiconductor fin.
Further, described charge storage composite bed comprises the tunnel oxide, nitride layer and the barrier oxidation nitride layer that set gradually to gate regions from side, described semiconductor fin channel region.
Further, described charge storage composite bed comprises from source area to tunnel oxide, floating gate layer and the barrier oxidation nitride layer that grid sets gradually.
Further, described substrate is P type semiconductor substrate, and described nitride layer is by Si
3n
4form.
Further, described substrate is P type semiconductor substrate, and described floating gate layer is made up of polysilicon.
Further, described memory cell also comprises setting field oxide on a semiconductor substrate, described source area and drain region, semiconductor fin, gate regions, and charge storage composite bed is arranged on described field oxide.
Further, described drain region, semiconductor fin, gate regions and charge storage composite bed arranged outside have oxide layer.
Present invention also offers a kind of formation method of 8-bit semiconductor memory cell, comprising:
Semiconductor substrate is provided, and etches formation four semiconductor fins on the semiconductor substrate; Wherein, described four semiconductor fins have a common port region, and described four semiconductor fins become band, and symmetrical centered by described common port region;
Be oxidized described semiconductor fin, described semiconductor fin forms the first oxide layer;
Deposit spathic silicon between described wantonly two neighbouring strip semiconductor fins, and etching forms gate regions;
Be oxidized described gate regions, described gate regions is formed the second oxide layer;
Deposit between described gate regions and its both sides neighbouring strip semiconductor fin and form electric charge capture layer;
Be entrained in described public petiolarea to described strip-shaped semiconductor fin to form source area, differ from the formation drain region, one end of public petiolarea at described strip-shaped semiconductor fin, and form channel region between described source area and drain region.
Further, the step of described formation four semiconductor fins comprises:
Form the hard mask of patterning over the substrate, the hard mask of described patterning is cross, and symmetrical is provided with four ribbon districts;
With described hard mask, described substrate is etched, formed and there is public petiolarea and four strip-shaped semiconductor fins symmetrical centered by described common port region;
Remove described hard mask, substrate is formed the field oxide surrounding described four strip-shaped semiconductor fins.
Further, described field oxide thickness is less than described semiconductor fin thickness.
Further, the step of described formation grid comprises:
Deposit spathic silicon on field oxide and between described wantonly two neighbouring strip semiconductor fins;
Described polysilicon is formed patterned photo glue, and with patterned photo glue for polysilicon described in mask etching, form right-angle bending shape gate regions, and the two ends concavity of described gate regions bending, described female end comprises jut and hollow bulb, and is contacted with both sides, described gate regions strip-shaped semiconductor fin by the jut of spill grid.
Further, described oxidation grid comprises the step of the jut complete oxidation of described spill grid.
Further, the step of described formation electric charge capture layer is included in described gate regions female end hollow bulb charge trapping layer material.
Further, described electric charge capture layer material is polysilicon or nitride.
Further, described substrate is P type semiconductor substrate, and described nitride is Si
3n
4.
Further, form source area respectively by the region between the described public petiolarea of strip-shaped semiconductor fin described in ion implantation doping, the one end differing from public petiolarea and above-mentioned two ends, form drain region and form channel region
Further, after formation source electrode and drain electrode, also comprise the step of obtained semicon-ductor structure surface being carried out to chemico-mechanical polishing, and generate the step of oxide layer at burnishing surface after chemico-mechanical polishing.
Present invention also offers a kind of 8-bit semiconductor memory cell array, comprise the 8-bit semiconductor memory cell of multiple one-tenth transverse and longitudinal array arrangement, multiple bit line and multiple wordline, it is characterized in that, semiconductor memory cell comprises a source electrode, four drain electrodes, four grids, four strip-shaped semiconductor fins and eight charge storage composite beds;
Wherein, described four drain electrodes are symmetrical arranged outside described source electrode, and are provided with the strip-shaped semiconductor fin with channel region between each described drain electrode and described source electrode;
Each of described four grids is arranged between every two adjacent described strip-shaped semiconductor fins, and described grid pass through described in there is channel region contacts between the charge storage composite bed of electric charge capture layer and this grid both sides semiconductor fin;
Described semiconductor memory cell, the first drain electrode and the 3rd drains and is oppositely arranged, and the second drain electrode and the 4th drains and is oppositely arranged, and first grid and the 3rd grid are oppositely arranged, and second grid and the 4th grid are oppositely arranged;
Second drain electrode and second of this line memory cell of every line memory cell drain formation bit line, and the 4th of the 4th drain electrode and this line memory cell drains formation bit line;
First drain electrode and first of this columns of memory cells of every columns of memory cells drain formation bit line, and the 3rd of the 3rd drain electrode and this columns of memory cells drains formation bit line;
In every columns of memory cells first and the 3rd grid form a wordline, and in every columns of memory cells second and the 4th grid form a wordline.
The present invention, by structural change, make in a semiconductor memory cell, achieve 8-bit and store, and its manufacture method can adapt with existing technique, and the basis not increasing too much process costs achieves high-density city.
Accompanying drawing explanation
Fig. 1 is existing multi-crystal silicon floating bar memory cell structure schematic diagram;
Fig. 2 is existing 1-bitSONOS memory cell structure schematic diagram;
Fig. 3 is 8-bit semiconductor storage unit structure vertical view of the present invention;
Fig. 4 is that 8-bit semiconductor memory cell of the present invention forms method flow diagram;
Fig. 5 a ~ Fig. 5 g is 8-bit semiconductor memory cell formation method schematic diagram of the present invention;
Fig. 6 is 8-bit semiconductor memory cell array schematic diagram of the present invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
In order to clear description structure of the present invention and method, be defined as follows vocabulary implication at this:
" relatively " refers to that both are with symmetric points Central Symmetry, and " adjacent " then refers to that both close on mutually.
The invention provides a kind of 8-bit memory cell, comprise setting source area on a semiconductor substrate and drain region, semiconductor fin, gate regions, and between described active area and grid, the charge storage composite bed with electric charge capture layer.
Fig. 3 is the vertical view of semiconductor memory cell of the present invention, semiconductor memory cell as shown in Figure 3, comprises a source area S, four drain region D1 ~ D4, four gate regions G1 ~ G4, four strip-shaped semiconductor fin AA1 ~ AA4 and eight charge storage composite bed B1 ~ B8.
Wherein, strip-shaped semiconductor fin AA1 ~ AA4 shares a source area S, four drain region D1 ~ D4 are arranged on one end that strip-shaped semiconductor fin AA1 ~ AA4 differs from source area S, and be symmetrical arranged, be formed with channel region (not shown) between each drain region D1 ~ D4 and source area S;
Four gate regions G1 ~ G4 are all arranged between every two adjacent strip-shaped semiconductor fin AA1 ~ AA4, and are respectively arranged with the charge storage composite bed B1 ~ B8 with electric charge capture layer between gate regions G1 ~ G4 and its both sides semiconductor fin AA1 ~ AA4.
Gate regions G1 ~ G4 bending-like all at a right angle, the two ends of its bending and the semiconductor fin AA1 ~ AA4 of G1 ~ G4 both sides, gate regions are by the channel region contacts of the charge storage composite bed B1 ~ B8 and semiconductor fin AA1 ~ AA4 with electric charge capture layer.
Semiconductor storage unit structure of the present invention is further illustrated for gate regions G1.The active area that one end G1a of gate regions G1 is formed by electric charge capture composite bed B1 and drain region D2 and source area S and semiconductor fin AA2 contacts, and the channel region place being arranged on this active area that G1a is corresponding, the active area that the other end G1b of gate regions G1 is formed by charge storage composite bed B8 and drain region D1 and source area S and semiconductor fin AA1 contacts, and the channel region place being arranged on this active area that G1b is corresponding.
Based on above-mentioned structure, the active area of gate regions G1, charge storage composite bed B1 and its correspondence constitutes a complete 1-bit semiconductor storage unit structure, and being equal to fell the 1-bit semiconductor storage unit structure of stacked setting on a semiconductor substrate is in the past flat in Semiconductor substrate.In like manner, the active area of gate regions G1, charge storage composite bed B8 and its correspondence also constitutes a complete 1-bit semiconductor storage unit structure.
Further, gate regions G2 ~ G4 is also corresponding respectively constitutes two 1-bit semiconductor storage unit structures.
So, this semiconductor storage structure provided by the invention, related to and layout by structure cleverly, utilize a source area S, namely four drain region D1 ~ D4, four gate regions G1 ~ G4, four strip-shaped semiconductor fin AA1 ~ AA4 and eight charge storage composite bed B1 ~ B8 just constitute 8-bit organization of semiconductor memory.
As preferably, charge storage composite bed B1 ~ B8 can comprise the tunnel oxide, nitride layer (preferred Si3N4) and the barrier oxidation nitride layer that set gradually to gate regions G1 ~ G4 from side, semiconductor fin AA1 ~ AA4 channel region, and then the memory of the ONO structure formed; Can also comprise from source area to tunnel oxide, floating gate layer (preferred polysilicon) and the barrier oxidation nitride layer that grid sets gradually, and then the memory of the floating gate structure formed.
The invention provides the manufacture method of above-mentioned 8-bit semiconductor memory cell, its flow process as shown in Figure 4, comprises step:
Semiconductor substrate is provided, and etches formation four semiconductor fins on a semiconductor substrate; Wherein, four semiconductor fins have a common port region, and four semiconductor fins become band, and symmetrical centered by common port region;
Oxide-semiconductor fin, semiconductor fin is formed the first oxide layer;
Deposit spathic silicon between two neighbouring strip semiconductor fins in office, and etching forms gate regions;
Oxidation gate regions, gate regions is formed the second oxide layer;
Deposit between gate regions and its both sides neighbouring strip semiconductor fin and form electric charge capture layer;
Be entrained in public petiolarea to strip-shaped semiconductor fin to form source area, differ from the formation drain region, one end of public petiolarea at strip-shaped semiconductor fin, and form channel region between source area and drain region.
With reference to Fig. 5 a ~ Fig. 5 g, below describe the manufacture method flow process of 8-bit semiconductor memory cell of the present invention in detail.
There is provided Semiconductor substrate, form the hard mask of patterning on semiconductor substrate 1, the hard mask of patterning is cross, is symmetrically arranged with four ribbon districts;
With hard mask, substrate is etched, formed and there is public petiolarea and four strip-shaped semiconductor fin a ~ d symmetrical centered by common port region, as shown in Figure 5 a;
Remove described hard mask, substrate is formed the field oxide 31 surrounding described four strip-shaped semiconductor fins, and the thickness of field oxide 31 is less than semiconductor fin thickness, as shown in Figure 5 b, Fig. 5 b is formed after field oxide 31, along the sectional view in A-A direction for structure shown in Fig. 5 a;
As shown in Figure 5 c, oxide-semiconductor fin a ~ d, forms the first oxide layer (not shown); Deposit spathic silicon 32 between wantonly two neighbouring strip semiconductor fins on field oxide 31;
As fig 5d, polysilicon 32 is formed patterned photo glue (not shown), and with patterned photo glue for mask etching polysilicon 32, form four right-angle bending shape gate regions G1 ~ G4, wherein, the two ends concavity of gate regions bending, for gate regions G1, its concrete shape is described, Fig. 5 e is the partial enlarged drawing of gate regions G1 in Fig. 5 d, two female end (33a of G1 bending, 33b) comprise jut (34a, 34b) with hollow bulb (35a, 35b), jut (the 34a of G1, 34b) contact with G1 both sides, gate regions strip-shaped semiconductor fin a with b.
Oxidation gate regions G1 ~ G4 forms the second oxide layer 36b, and the jut of complete oxidation spill grid, as shown in figure 5f;
At gate regions G1 ~ G4 female end hollow bulb deposited charge trapping material, for clear description, still be described for the gate regions G1 of partial enlargement, as shown in fig. 5g: at G1 female end hollow bulb deposited charge trapping material 36c, so, the the first oxide layer 36a formed during oxide-semiconductor fin, the charge storage composite bed that the second oxide layer 36b that the charge trapping material 36c of deposition and oxidation gate regions are formed just has been stacked into, wherein, with the first oxide layer 36a for tunnel oxide, second oxide layer 36b is barrier oxide layer, charge trapping material 36c is by selecting polysilicon or nitride (as Si
3n
4), and then form floating gate structure or SONOS structure.
Form source area S respectively by the region between the public petiolarea of strip-shaped semiconductor fin described in ion implantation doping, the one end differing from public petiolarea and above-mentioned two ends, form drain region D1 ~ D4 and form raceway groove respectively between the D1 ~ D4 of drain region after the S of source area;
Finally chemico-mechanical polishing is carried out to obtained semicon-ductor structure surface, and generate oxide layer at burnishing surface after chemico-mechanical polishing, just obtain 8-bit semiconductor storage unit structure of the present invention as shown in Figure 3.
Known for those skilled in the art, the oxide layer generated after oxide layer on cushion oxide layer, semiconductor fin, gate regions oxide layer and cmp is except a part for the oxide layer on semiconductor fin and gate regions oxide layer is as except tunnel oxide and barrier oxide layer, the effect of other oxide layer portion its surface oxide layer on 8-bit semiconductor storage unit structure of the present invention, for improving the surface breakdown voltage of memory cell.
Further, as a kind of specific embodiment of method in the present invention, and only core process flow process is recorded, completely this case is not recorded in the technical process that must perform well known to those skilled in the art; Moreover wherein the description of each technique is only limited to qualitative elaboration, does not limit technique numerical value, those skilled in the art can select according to actual conditions and experience, and this also should belong to the scope of the inventive method protection.
Present invention also offers a kind of 8-bit semiconductor memory cell array, comprise the 8-bit semiconductor memory cell of multiple one-tenth transverse and longitudinal array arrangement, multiple bit line and multiple wordline; Semiconductor memory cell comprises a source electrode, four drain electrodes, four grids, four strip-shaped semiconductor fins and eight charge storage composite beds;
Wherein, four drain electrodes are symmetrical arranged outside source electrode, and are provided with the strip-shaped semiconductor fin with channel region between each drain electrode and source electrode;
Each of four grids is arranged between every two adjacent strip-shaped semiconductor fins, and grid is by having the channel region contacts between the charge storage composite bed of electric charge capture layer and this grid both sides semiconductor fin;
Semiconductor memory cell, the first drain electrode and the 3rd drains and is oppositely arranged, and the second drain electrode and the 4th drains and is oppositely arranged, and first grid and the 3rd grid are oppositely arranged, and second grid and the 4th grid are oppositely arranged;
Second drain electrode and second of this line memory cell of every line memory cell drain formation bit line, and the 4th of the 4th drain electrode and this line memory cell drains formation bit line;
First drain electrode and first of this columns of memory cells of every columns of memory cells drain formation bit line, and the 3rd of the 3rd drain electrode and this columns of memory cells drains formation bit line;
In every columns of memory cells first and the 3rd grid form a wordline, and in every columns of memory cells second and the 4th grid form a wordline.
2 × 2 arrays as shown in Figure 6, are described in detail 8-bit semiconductor memory cell array:
Memory cell becomes transverse and longitudinal array arrangement with memory cell;
Each memory cell in array, the grid in the definition upper left corner is first grid, and define successively clockwise second, third, the 4th grid, the drain electrode on the definition left side is the first drain electrode, and define successively clockwise second, third, the 4th drain electrode;
Have four wordline wi1 ~ wi4,8 bit line bi1 ~ bi8, wherein:
Wordline wi1 is formed by connecting by the first grid of the first columns of memory cells and the 3rd grid (with first grid Central Symmetry), and in like manner, wordline wi3 is formed by connecting by the first grid of the second columns of memory cells and the 3rd grid;
Wordline wi2 is formed by connecting by the second grid of the first columns of memory cells and the 4th grid, in like manner wordline wi4;
Bit line bi1 is formed by connecting by the first drain electrode of the first columns of memory cells, bit line bi2 is formed by connecting by the 3rd drain electrode of the first columns of memory cells, in like manner, bit line bi3 and bi4 be by first of the second columns of memory cells and the 3rd drain electrode be formed by connecting;
Bit line bi5 is formed by connecting by the second drain electrode of the first line memory cell, and bit line bi6 is formed by connecting by the 4th drain electrode of the first line memory cell, and in like manner, bit line bi7 and bi8 be similar setting also.
The You Liangge memory location, two active areas that each grid in each memory cell is adjacent respectively, for the second row secondary series first grid, when selecting bit line bi7 and wordline wi3, programme in memory location between the active area that can be formed its second drain electrode and source electrode and first grid, when selecting bit line bi3 and wordline wi3, programme in memory location between the active area that can be formed its first drain electrode and source electrode and first grid, in like manner, the bit line of setting like this and word line circuit structure can be programmed to each 8-bit memory cell stored in array, realize storing and erasing.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (19)
1. a 8-bit semiconductor memory cell, comprise setting source area on a semiconductor substrate and drain region, semiconductor fin, gate regions, and between described source area and gate regions, the charge storage composite bed with electric charge capture layer, it is characterized in that, described semiconductor memory cell comprises a source area, four drain regions, four gate regions, four strip-shaped semiconductor fins and eight charge storage composite beds;
Wherein, described four drain regions are symmetrical arranged outside described source area, and are provided with the strip-shaped semiconductor fin with channel region between each described drain region and described source area;
Each of described four gate regions is arranged between every two adjacent described strip-shaped semiconductor fins, and described gate regions pass through described in there is channel region contacts between the charge storage composite bed of electric charge capture layer and this both sides, gate regions semiconductor fin.
2. memory cell according to claim 1, is characterized in that, described gate regions bending-like at a right angle, and the two ends of described right-angle bending shape gate regions are by the channel region contacts between described charge storage composite bed and this grid both sides semiconductor fin.
3. memory cell according to claim 1 and 2, is characterized in that, described charge storage composite bed comprises the tunnel oxide, nitride layer and the barrier oxidation nitride layer that set gradually to gate regions from side, described semiconductor fin channel region.
4. memory cell according to claim 1 and 2, is characterized in that, described charge storage composite bed comprises from source area to tunnel oxide, floating gate layer and the barrier oxidation nitride layer that grid sets gradually.
5. memory cell according to claim 3, is characterized in that, described substrate is P type semiconductor substrate, and described nitride layer is by Si
3n
4form.
6. memory cell according to claim 4, is characterized in that, described substrate is P type semiconductor substrate, and described floating gate layer is made up of polysilicon.
7. memory cell according to claim 1 and 2, it is characterized in that, described memory cell also comprises setting field oxide on a semiconductor substrate, described source area and drain region, semiconductor fin, gate regions, and charge storage composite bed is arranged on described field oxide.
8. memory cell according to claim 1 and 2, is characterized in that, described drain region, semiconductor fin, gate regions and charge storage composite bed arranged outside have oxide layer.
9. a formation method for 8-bit semiconductor memory cell, comprising:
Semiconductor substrate is provided, and etches formation four semiconductor fins on the semiconductor substrate; Wherein, described four semiconductor fins have a common port region, and described four semiconductor fins become band, and symmetrical centered by described common port region;
Be oxidized described semiconductor fin, described semiconductor fin forms the first oxide layer;
Deposit spathic silicon between described wantonly two neighbouring strip semiconductor fins, and etching forms gate regions;
Be oxidized described gate regions, described gate regions is formed the second oxide layer;
Deposit between described gate regions and its both sides neighbouring strip semiconductor fin and form electric charge capture layer;
Be entrained in described public petiolarea to described strip-shaped semiconductor fin to form source area, differ from the formation drain region, one end of public petiolarea at described strip-shaped semiconductor fin, and form channel region between described source area and drain region.
10. method according to claim 9, is characterized in that, the step of described formation four semiconductor fins comprises:
Form the hard mask of patterning over the substrate, the hard mask of described patterning is cross, and symmetrical is provided with four ribbon districts;
With described hard mask, described substrate is etched, formed and there is public petiolarea and four strip-shaped semiconductor fins symmetrical centered by described common port region;
Remove described hard mask, substrate is formed the field oxide surrounding described four strip-shaped semiconductor fins.
11. methods according to claim 10, is characterized in that, described field oxide thickness is less than described semiconductor fin thickness.
12. methods according to claim 10 or 11, it is characterized in that, the step of described formation grid comprises:
Deposit spathic silicon on field oxide and between described wantonly two neighbouring strip semiconductor fins;
Described polysilicon is formed patterned photo glue, and with patterned photo glue for polysilicon described in mask etching, form right-angle bending shape gate regions, and the two ends concavity of described gate regions bending, described female end comprises jut and hollow bulb, and is contacted with both sides, described gate regions strip-shaped semiconductor fin by the jut of spill grid.
13. methods according to claim 12, is characterized in that, described oxidation grid comprises the step of the jut complete oxidation of described spill grid.
14. methods according to claim 12, is characterized in that, the step of described formation electric charge capture layer is included in described gate regions female end hollow bulb charge trapping layer material.
15. methods according to claim 14, is characterized in that, described electric charge capture layer material is polysilicon or nitride.
16. methods according to claim 15, is characterized in that, described substrate is P type semiconductor substrate, and described nitride is Si
3n
4.
17. methods according to claim 9, it is characterized in that, form source area respectively by the region between the described public petiolarea of strip-shaped semiconductor fin described in ion implantation doping, the one end differing from public petiolarea and above-mentioned two ends, form drain region and form channel region.
18. methods according to claim 9, is characterized in that, after formation source electrode and drain electrode, also comprise the step of obtained semicon-ductor structure surface being carried out to chemico-mechanical polishing, and generate the step of oxide layer at burnishing surface after chemico-mechanical polishing.
19. 1 kinds of 8-bit semiconductor memory cell arrays, comprise the 8-bit semiconductor memory cell of multiple one-tenth transverse and longitudinal array arrangement, multiple bit line and multiple wordline, it is characterized in that, semiconductor memory cell comprises a source electrode, four drain electrodes, four grids, four strip-shaped semiconductor fins and eight charge storage composite beds;
Wherein, described four drain electrodes are symmetrical arranged outside described source electrode, and are provided with the strip-shaped semiconductor fin with channel region between each described drain electrode and described source electrode;
Each of described four grids is arranged between every two adjacent described strip-shaped semiconductor fins, and described grid pass through described in there is channel region contacts between the charge storage composite bed of electric charge capture layer and this grid both sides semiconductor fin;
Described semiconductor memory cell, the first drain electrode and the 3rd drains and is oppositely arranged, and the second drain electrode and the 4th drains and is oppositely arranged, and first grid and the 3rd grid are oppositely arranged, and second grid and the 4th grid are oppositely arranged;
Second drain electrode and second of this line memory cell of every line memory cell drain formation bit line, and the 4th of the 4th drain electrode and this line memory cell drains formation bit line;
First drain electrode and first of this columns of memory cells of every columns of memory cells drain formation bit line, and the 3rd of the 3rd drain electrode and this columns of memory cells drains formation bit line;
In every columns of memory cells first and the 3rd grid form a wordline, and in every columns of memory cells second and the 4th grid form a wordline.
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| KR102637644B1 (en) * | 2016-07-14 | 2024-02-19 | 삼성전자주식회사 | Memory device |
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