CN103094247B - A kind of self aligned extension contact hole structure and preparation method - Google Patents
A kind of self aligned extension contact hole structure and preparation method Download PDFInfo
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- CN103094247B CN103094247B CN201210580108.3A CN201210580108A CN103094247B CN 103094247 B CN103094247 B CN 103094247B CN 201210580108 A CN201210580108 A CN 201210580108A CN 103094247 B CN103094247 B CN 103094247B
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Abstract
The present invention relates to a kind of self aligned extension contact hole structure and preparation method, including：Etching stop layer is formed on substrate；Exposed and etching, defines epitaxial growth zone map on etching stop layer, and epitaxial growth region is formed in source electrode and drain surface；Using selective epitaxial growth process, vertical ordering growth is carried out in epitaxial growth region surface, form extension contact hole；Layer of metal front medium layer is deposited on substrate, air-gap is formed between source electrode, drain and gate；Using photoetching technique, the substrate surface beyond extension contact hole top is covered, only expose extension contact hole top；Externally receiving contact hole carries out heavy doping technique；Contact hole top is received outside forms one layer of silicide.The present invention realizes contact hole self-aligned vertical epitaxial growth, and the extension contact hole resistance rate for preparing is low, and is obtained in that good Ohmic contact on its surface, using the air-gap for being formed, such that it is able to largely reduce RC retardation ratio.
Description
Technical field
The present invention relates to ic manufacturing technology field, more particularly to a kind of self aligned extension contact hole structure and system
Preparation Method.
Background technology
Super large-scale integration manufacturing industry follows Moore's Law always, realizes that integration density is doubled for every 1.5 years.For
Ensure the constantly improve of integration density, integrated circuit critical size constantly reduces, many technical problems are brought therewith.Wherein,
The crosstalk or electromagnetic action caused by the approach effect of various circuit sources device cannot be ignored, and influence RC retardation ratio indirectly.
As technology node enters 65nm and following, the RC retardation ratio of metal interconnection turned into whole chip RC retardation ratio major part it
One.
On the one hand, the maximum RC retardation ratio of metal interconnection appears in the electrical contact of silicon face and metal surface, and industry is generally adopted
With silicide contact resistance is reduced as transition zone.That be used as silicide earliest is WSi2, it is followed by continuing to use to 250nm technologies
The TiSi in generation2With the CoSi for continuing to use 130nm technology generations2, arrived 90nm technologies generation and begun to use NiSi below2, progressively by transition
The resistivity of layer is down near 10 uohmcm.
On the other hand, in order to reduce the RC retardation ratio between copper interconnection layer, industry is generally replaced using lower dielectric constant medium
Traditional SiO2（k~4.2）Medium.In 90nm to 65nm technology generations, industry generally uses SiOCH of the dielectric constant 2.6 ~ 3.0
The CORAL of the BD1 and Novellus of medium, such as AMAT.Into 45nm technology generations, industry typically enters one using porous type SiOCH
Step drop low k-value, such as BD2 of AMAT, dielectric constant is up to 2.0 ~ 2.5；Also have using C, H organic media, such as Dow Chemical
SILK, dielectric constant is 2.2 ~ 2.6.Although be down to k values near 2.0 by the ultralow dielectric medium of prior art,
Cannot still meet metal line width further reduce requirement, industry start consider dielectric constant be 1 air as connected medium,
That is air-gap.
Source drain contact hole technique will unavoidably consider factors described above as a kind of interconnection process, typically
Using tungsten contact hole technology as source drain contact hole technique, preparation process is：After all preceding road techniques are completed, first deposit
Layer of metal front medium layer, chemically mechanical polishing（CMP）Planarization material front medium layer, makes source electrode and drain contact porose area by lithography
Domain, dry etching goes out source electrode and drain contact hole, and low concentration injection is repaired the etching injury of contact hole, deposits barrier layer Ti/
TiN, CVD deposition via metal tungsten, finally chemically mechanical polishing is ground tungsten contact hole.As integrated circuit critical size continues
Reduce, the filling capacity of tungsten CVD techniques encounters severe challenge；Contact hole etching technique is to very thin source/drain silicide table
The physical damnification in face causes the increase of contact resistance, and then increases RC retardation ratio.Accordingly, it would be desirable to be carried out to existing contact hole and technique
Improve, so as to reduce contact resistance and RC retardation ratio.
The content of the invention
To overcome above mentioned problem, it is an object of the invention to provide a kind of self aligned extension contact hole structure and preparation side
Method.
The present invention provides a kind of self aligned extension contact hole structure, and the substrate of use includes grid, source electrode and drain electrode, its
It is characterised by, including：
Etching stop layer on the substrate；
Extension contact hole on the source electrode and the drain electrode；
Before-metal medium layer on the extension contact hole；
Silicide at the top of the extension contact hole；
Air-gap is formed between the source electrode, the drain electrode and the grid；And in the before-metal medium layer and
Air-gap is formed between the etching stop layer.
Preferably, the material of the extension contact hole is germanium silicon.
Preferably, in the germanium silicon, the content of germanium is 20%-60%.
Preferably, the extension contact hole is the extension contact hole of heavy doping.
Preferably, the doping concentration of the heavy doping is 1016-1017。
Preferably, the substrate includes PMOS or NMOS.
The present invention also provides a kind of method for preparing above-mentioned self aligned extension contact hole structure, it is characterised in that including：
Step S01：One layer of etching stop layer is formed on substrate；
Step S02：Exposed and etching, defines epitaxial growth zone map, in the source on the etching stop layer
Pole and the drain surface form epitaxial growth region；
Step S03：Using selective epitaxial growth process, vertical ordering life is carried out in the epitaxial growth region surface
It is long, form extension contact hole；
Step S04：By depositing layer of metal front medium layer over the substrate, in the source electrode, the drain electrode and institute
State and form air-gap between grid；
Step S05：Using photoetching technique, the substrate surface beyond extension contact hole top is covered, only exposed
Go out the extension contact hole top；
Step S06：Heavy doping technique is carried out to the extension contact hole；
Step S07：One layer of silicide is formed at the top of the extension contact hole.
Preferably, in step S04, also including planarizing the gold using low stress or stressless chemically mechanical polishing
Category front medium layer.
Preferably, in step S06, after the heavy doping technique, the source electrode, the drain electrode and the extension are contacted
Line activating annealing is entered in hole simultaneously.
Preferably, the activation annealing temperature is 950 DEG C -1050 DEG C.
Preferably, in step S02, the etching technics for using is first to carry out dry etching, then carries out wet etching.
Preferably, the heavy dopant concentration in the heavy doping technique is 1016-1017。
Preferably, the material of the extension contact hole is germanium silicon.
Preferably, in the germanium silicon, the content of germanium is 20%-60%.
Preferably, the substrate includes PMOS or NMOS.
Compared with prior art, a kind of self aligned extension contact hole structure of the invention and preparation method, by using
Selective epitaxial growth process, realizes contact hole self-aligned vertical epitaxial growth, by the way that externally receiving contact hole carries out heavy doping
Made annealing treatment with activation so that the resistivity of the extension contact hole of heavy doping is close with the resistivity of tungsten contact hole, by swashing
Annealing living so that good Ohmic contact is reached between source electrode, drain electrode and extension contact hole, RC retardation ratio is reduced, utilizes
Preceding metallic dielectric layer forms air-gap between source electrode, drain electrode and extension contact hole, such that it is able to further reduce RC retardation ratio.
Brief description of the drawings
Fig. 1 is an a kind of system for preferred embodiment of the preparation method of self aligned extension contact hole structure of the invention
Standby schematic flow sheet；
Fig. 2-6 is each of the preparation method of the self aligned extension contact hole structure of above-mentioned preferred embodiment of the invention
Preparation process schematic diagram；
Fig. 7 is the structural representation of the self aligned extension contact hole structure of above-mentioned preferred embodiment of the invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the present invention provide a kind of self aligned extension contact hole structure and its
Preparation method is described in further detail.According to following explanation and claims, advantages and features of the invention will become apparent from.
It should be noted that, accompanying drawing in the form of simplifying very much and uses non-accurately ratio, is only used to conveniently, lucidly aid in
Illustrate the purpose of the embodiment of the present invention.
Below in conjunction with accompanying drawing 1-7, a kind of self aligned extension contact hole structure of the invention and preparation method thereof is made into
One step is described in detail.It should be noted that, accompanying drawing in the form of simplifying very much and uses non-accurately ratio, only to side
Just the purpose of the embodiment of the present invention, is lucidly aided in illustrating.
Fig. 1 is an a kind of system for preferred embodiment of the preparation method of self aligned extension contact hole structure of the invention
Standby schematic flow sheet.Fig. 2-7 is the preparation method of the self aligned extension contact hole structure of the above-mentioned preferred embodiment of this law
Each preparation process schematic diagram.
Fig. 1 is referred to, a kind of preparation method of self aligned extension contact hole structure of the invention comprises the following steps：
Step S01：Fig. 2 is referred to, one layer of etching stop layer is formed on substrate.Specifically, in the present invention, substrate is included
PMOS or NMOS, PMOS can be, but not limited to be germanium silicon, and for the ease of explaining, in the present embodiment, PMOS is germanium silicon, with PMOS
As a example by be described, but this is not used in limitation the scope of the present invention.After the preparation technology for completing grid, source electrode and drain electrode, shape
Into the substrate for including grid, source electrode and drain electrode, the present invention is not imposed any restrictions to this technique.Then over the substrate use but
It is not limited to strained silicon technology and forms one layer of etching stop layer, the material of etching stop layer can be, but not limited to be SiN, in this implementation
In example, the etching stop layer is strain silicon dielectric layer, and PMOS surfaces are the SiN etching stop layers with compression, NMOS surfaces
It is the SiN etching stop layers with tensile stress.Because PMOS is identical with the preparation method of NMOS, in the present embodiment, entered with PMOS
Row explains description.
Step S02：Fig. 3 is referred to, etching stop layer is exposed and is etched, on the source and drain regions square quarter
Lose and epitaxial growth zone map is defined on stop-layer, etching technics adopted here, including：First use dry etch process
The SiN of epitaxial growth zone map is removed, the extension of cleaning is then obtained in source electrode and drain surface using wet-etching technology
Growth district.
Step S03：Fig. 4 is referred to, using selective epitaxial growth process, in source electrode and the epitaxial growth area of drain surface
Domain carries out vertical ordering growth, forms extension contact hole；In the present embodiment, the material of extension contact hole is germanium silicon, and germanium contains
It is 20%-60% to measure.Wherein, due to the presence of etching stop layer so that epitaxial growth only can be along source electrode and drain surface
Epitaxial growth region is grown, so as to reach the purpose of vertical ordering growth.Here, the height of extension contact hole can basis
Need to set, the invention is not limited in this regard.
Step S04：Refer to Fig. 5, using but be not limited to plasma enhanced chemical vapor deposition method on substrate sink
Product layer of metal front medium layer, the before-metal medium layer can be, but not limited to be fluorodioxy SiClx, medium with low dielectric constant material
Or ultralow dielectric dielectric material.After the deposition for completing before-metal medium layer, formed between source electrode, drain and gate
Air-gap.Because the physical mechanical strength of air-gap is relatively low, therefore in the present embodiment, using low stress or stressless chemical machine
Tool is polished（CMP）Method comes planarization material front medium layer surface.
Step S05：Using photoetching technique, the substrate surface beyond extension contact hole top is covered, only exposure is gone out
Receive contact hole top.
Step S06：Fig. 6 is referred to, externally receiving contact hole carries out heavy doping technique.
Specifically, in the present invention, the doping-sequence for PMOS or the extension contact hole of NMOS area is not limited, and is just
In the present invention is explained, in the present embodiment, only describe to carry out the extension contact hole of PMOS area the technique of heavy doping, NMOS's
Doping process is similar to, and no longer repeats one by one.In the present embodiment, using photoetching technique, other locality protections are got up and is only exposed
Go out the top of the extension contact hole of PMOS area, the boron injection for then using but being not limited to high concentration carries out boron (B) heavy doping,
Heavy doping content is 1016-1017, in the present embodiment, heavy doping content can be, but not limited to be 5 × 1016。
After heavy doping, while can be, but not limited to high-temperature annealing activation treatment to source electrode, drain electrode and extension contact hole, swash
Annealing temperature living is 950 DEG C -1050 DEG C, from 950 DEG C as activation annealing temperature in the present embodiment.
Step S07：Refer to Fig. 7, using but be not limited to chemical vapour deposition technique receive outside contact hole top formed one layer
Silicide.Here, silicide can be, but not limited to be SiCo or SiNi.Here, extension contact hole table is reduced using silicide
The contact resistance in face.
A kind of self aligned extension contact hole structure in the present embodiment, refers to Fig. 7, including：One substrate；Positioned at lining
Etching stop layer on bottom；The extension contact hole of the heavy doping on source electrode and drain electrode；Metal on extension contact hole
Front medium layer；Silicide at the top of extension contact hole；Air-gap is formed between source electrode, drain and gate；And in gold
Air-gap is formed between category front medium layer and etching stop layer.
It should be noted that substrate can be, but not limited to be germanium silicon comprising PMOS or NMOS, PMOS；Using but be not limited to should
Become silicon technology and form one layer of etching stop layer, the material of etching stop layer can be, but not limited to be SiN, in the present embodiment, should
Etching stop layer is strain silicon dielectric layer, and PMOS surfaces are the SiN etching stop layers with compression；In the present embodiment, extension
The material of contact hole is germanium silicon, and the content of germanium is 20%-60%；The before-metal medium layer can be, but not limited to be fluorodioxy SiClx,
Medium with low dielectric constant material or ultralow dielectric dielectric material；Heavy doping content is 1016-1017, it is heavily doped in the present embodiment
Miscellaneous content can be, but not limited to be 5 × 1016；Silicide can be, but not limited to be SiCo or SiNi.
Therefore, a kind of self aligned extension contact hole structure of the invention and preparation method, by using selective epitaxial
Growth technique, realizes contact hole self-aligned vertical epitaxial growth, and by externally receiving, contact hole carries out heavy doping and activation is annealed
Treatment so that the resistivity of the extension contact hole of heavy doping is close with the resistivity of tungsten contact hole, is made annealing treatment by activating,
So that source electrode, drain electrode and extension contact hole between reach good Ohmic contact, using preceding metallic dielectric layer source electrode, drain electrode with
Air-gap is formed between extension contact hole, such that it is able to further reduce RC retardation ratio.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (15)
1. a kind of self aligned extension contact hole structure, the substrate of use includes grid, source electrode and drain electrode, it is characterised in that bag
Include：
Etching stop layer on the substrate；
Extension contact hole on the source electrode and the drain electrode；
Before-metal medium layer on the extension contact hole；
Silicide at the top of the extension contact hole；
Air-gap is formed between the source electrode, the drain electrode and the grid；And in the before-metal medium layer and described
Air-gap is formed between etching stop layer.
2. a kind of self aligned extension contact hole structure according to claim 1, it is characterised in that the extension contact hole
Material be germanium silicon.
3. a kind of self aligned extension contact hole structure according to claim 2, it is characterised in that in the germanium silicon, germanium
Content be 20%-60%.
4. a kind of self aligned extension contact hole structure according to claim 1, it is characterised in that the extension contact hole
It is the extension contact hole of heavy doping.
5. a kind of self aligned extension contact hole structure according to claim 4, it is characterised in that the heavy doping is mixed
Miscellaneous concentration is 1016-1017cm-3。
6. a kind of self aligned extension contact hole structure according to claim 1, it is characterised in that the substrate includes
PMOS or NMOS.
7. a kind of method of the self aligned extension contact hole structure prepared described in claim 1, it is characterised in that including：
Step S01：One layer of etching stop layer is formed on substrate；
Step S02：Exposed and etching, defines epitaxial growth zone map on the etching stop layer, in the source electrode and
The drain surface forms epitaxial growth region；
Step S03：Using selective epitaxial growth process, vertical ordering growth is carried out in the epitaxial growth region surface,
Form extension contact hole；
Step S04：By depositing layer of metal front medium layer over the substrate, in the source electrode, the drain electrode and the grid
Air-gap is formed between pole；
Step S05：Using photoetching technique, the substrate surface beyond extension contact hole top is covered, only expose institute
State extension contact hole top；
Step S06：Heavy doping technique is carried out to the extension contact hole；
Step S07：One layer of silicide is formed at the top of the extension contact hole.
8. preparation method according to claim 7, it is characterised in that in step S04, also including using low stress or without should
The chemically mechanical polishing of power planarizes the before-metal medium layer.
9. preparation method according to claim 7, it is characterised in that right after the heavy doping technique in step S06
The source electrode, the drain electrode and the extension contact hole enter line activating annealing simultaneously.
10. preparation method according to claim 9, it is characterised in that the activation annealing temperature is 950 DEG C -1050 DEG C.
11. preparation methods according to claim 7, it is characterised in that in step S02, the etching technics for using is for advanced
Row dry etching, then carry out wet etching.
12. preparation method according to claim 7 or 9, it is characterised in that the heavy dopant concentration in the heavy doping technique
It is 1016-1017cm-3。
13. preparation methods according to claim 7, it is characterised in that the material of the extension contact hole is germanium silicon.
14. preparation methods according to claim 13, it is characterised in that in the germanium silicon, the content of germanium is 20%-
60%.
15. preparation methods according to claim 7, it is characterised in that the substrate includes PMOS or NMOS.
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| US6093612A (en) * | 1997-05-24 | 2000-07-25 | Lg Semicon Co., Ltd. | Metal oxide silicon field effect transistor (MOSFET) and fabrication method of same |
| CN1437269A (en) * | 2002-02-07 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Gate module and its making process |
| CN102456617A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Method of forming self-aligned local interconnect and structure formed thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010045608A1 (en) * | 1999-12-29 | 2001-11-29 | Hua-Chou Tseng | Transister with a buffer layer and raised source/drain regions |
| US8946048B2 (en) * | 2010-06-19 | 2015-02-03 | Sandisk Technologies Inc. | Method of fabricating non-volatile memory with flat cell structures and air gap isolation |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6093612A (en) * | 1997-05-24 | 2000-07-25 | Lg Semicon Co., Ltd. | Metal oxide silicon field effect transistor (MOSFET) and fabrication method of same |
| CN1437269A (en) * | 2002-02-07 | 2003-08-20 | 台湾积体电路制造股份有限公司 | Gate module and its making process |
| CN102456617A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Method of forming self-aligned local interconnect and structure formed thereby |
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