CN103092588A - Object-oriented VHDL (Vhsic Hardware Description Language) based language implementation method - Google Patents

Abstract

The invention discloses an object-oriented VHDL (Vhsic Hardware Description Language) based language implementation method. C++ codes generated through the method reserve a hierarchical structure relationship of an original VHDL design, and have the characteristics of distinctive nuance, good readability, high efficiency and the like; and a compiling simulator constructed by the codes has the advantages of high simulation speed and strong extendibility, and provides an effective technology for the high-speed simulation of a super-large-scale integrated circuit.

Description

A kind of based on OO VHDL language implementation method

Technical field

The present invention relates to a kind of based on OO VHDL language implementation method, be OO VHDL language (00-VHDL) and the design implementation method.

Background technology

00-VHDL (Object-Orieted VHDL), be OO VHDL, the RASSP that its main concept is supported from U.S. Department of Defense (Rapid Prototyping of Application-Specific Signal Processors, dedicated signal processors prototype fast) plan.OO method obtains extensively to admit in soft project circle in the ability aspect the recyclability of processing complicacy and increase software.And this problem in the urgent need to address in current I C design just.Therefore, people wish object-oriented method is applied in VHDL.The developer of RASSP think OO key element (as abstract, encapsulation, modularity, level etc.) be equally applicable to hardware is carried out abstract, the Vista Technologies company expansion VHDL language of setting out thus.VHDL language after expansion is referred to as the 00-VHDL language.Main expansion is to have introduced new language object Entity Object, is that the feature that increases class on the Entity basis obtains; In addition, Entity and Architecture in 00-VHDL have possessed inheritance mechanism, can communicate by letter with message between different Entity Object.

In fact VHDL itself has possessed abstractness and the modularity of certain procedures.Entity, Procedure and Fuction support abstractness, and Package, Entity and the file that leaves the VHDL code in are all reusable modules.But on abstractness, VHDL has very large deficiency: from the interface of Entity, the deviser can't obtain the function information of element, can only start needed operation by the port level is set accurately, and can not carry out with abstract mode.When particularly carrying out the emulation of higher level, the model of next stage unit is not set up or is also needed toward contact and revises.On encapsulation property, the VHDL ability is also strong not, such as the Variable in Package or Signal can not be packed.The method that 00-VHDL addresses these problems is to introduce Entity Object as the elementary cell of abstract, encapsulation and modularity.In VHDL, reusable level only occurs in the component one-level, deviser or go to use it according to the original configuration of element fully, or redesign new element.But, be usually that existing element is done some modifications or increased some new functions during actual design.If Application standard VHDL have to copy and revise original code usually by hand.The inheritance mechanism of 00-VHDL has solved this problem preferably.

Operation in Entity Object is activated by message (message), from sender of the message's angle, sends a piece of news and is similar to call subroutine.But from recipient's angle, message is to carry out the request of a certain operation, might not be made an immediate response.Therefore, message is a kind of more abstract mechanism, there is no direct corresponding relation with hardware.And in hardware, the communication between element and exchanges data need specific agreement or synchronization mechanism.By message, the deviser can start abstractively a certain operation and needn't be accurately according to agreement or synchronization mechanism.So just improved the dirigibility of modeling; Otherwise.If communication protocol or synchronization mechanism change to some extent, must revise whole VHDL model.At present, Vista Technologies is developing the support environment of 00-VHDL in this environment, the deviser sets up the 00-VHDL model by certain input tool, its source code is translated into the VHDL code of standard by pretreater, this code can be accepted by general VHDL emulation and synthesis tool.When emulation, a trace tool (traceability tool) is shone upon back initial 00-VHDL code to statement in the VHDL code, and debugging can be carried out in the 00-VHDL code like this.

Summary of the invention

Based on the problems referred to above, hereby invent a kind of based on OO VHDL language implementation method; Complete this work by an operation simulation core, the Main Function of operation simulation core is each C++ class member function that is converted by process of adjusting in due course in simulation process in whole design, with the concurrent implementation of simulation process, the modeling algorithm that can use case drives (event-driven) is realized.Its algorithm is as follows:

(1) translation of constant, variable and signal

On method for expressing with constant, variable and signal object in the corresponding VHDL of the class object of C++.Be class of the dtd——data type definition in each VHDL, identifier of definition is in order to distinguish signal, variable and constant in class, define data volume by the mode with the dtd——data type definition object, and by distinguishing signal, variable and constant to the constructed fuction Transfer Parameters.For example, following 402005 years the 6th phases of VHDL Source Description (left side) can be translated as corresponding C++ code (the right):

signal?a：bit：＝’0’；Wbitdata?a(“a”，GVHdLobject::SIGNAL，…，’0’)；

Variable?b：integer：＝10；Wintegerdata?b(“b”，GVHdLobjcct::VARIABLE，…，10)；

constant?c：integer：＝20；Wintegerdata?c(“c”，GVHdLobject::CoNSTANT，…，20)；

Wherein Wbitdata and Wintegerdata are respectively bit in VHdL and two classes of integer type definition, and CoNSTANT, VARIABLE, SIGNAL are the static constants of 3 classes that define in class GVHdLobject, in order to distinguish constant, variable and signal.

(2) translation of entity, structure

Entity, structure are the elementary cells that VHdL organizes whole design.Be defined in the data such as signal of stating in the VHdL structure in C++ structure class, and the function that is entity due to structure realizes, it has all attributes of entity, and this is identical with derived relation in C++, therefore the structure in C++ is derived from from entity class.The corresponding entity class of each entity, the corresponding structure class of each structure.

(3) process translation

Process is the elementary cell of simulator scheduling, and the translation of process plays key effect for operation simulation.Each VHdL process in structure is translated as a C++ process class, member variable during the object that defines in the VHdL process like this etc. all can directly be defined as C++ process class, the order statement in process is translated as a member function (simulate () function) of process class.When simulator is dispatched, take the process class object as scheduler object, when process was activated the needs simulation, simulation was with the simulate () function of calling process class object.

Claims (2)

1. one kind based on OO VHDL language implementation method: the method is mainly to utilize the parallel characteristics that characterizes VHDL with the order statement of C++.

According to claim 1 based on OO VHDL language implementation method, the method mainly comprises three parts namely: the translation of constant, variable and signal; The translation of entity, structure; The process translation.