CN101000541A - Method for automatic converting higher-order program language into hardware descriptive language - Google Patents
Method for automatic converting higher-order program language into hardware descriptive language Download PDFInfo
- Publication number
- CN101000541A CN101000541A CN 200610004903 CN200610004903A CN101000541A CN 101000541 A CN101000541 A CN 101000541A CN 200610004903 CN200610004903 CN 200610004903 CN 200610004903 A CN200610004903 A CN 200610004903A CN 101000541 A CN101000541 A CN 101000541A
- Authority
- CN
- China
- Prior art keywords
- nextport
- hardware component
- description language
- language
- hardware description
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Devices For Executing Special Programs (AREA)
Abstract
A method for converting high-order program language automatically to be hardware description language includes converting original program code of said language program to be extension active map first then converting active map to be hardware component map and finally generating signal connection of corresponding VHDL component according to on-line of hardware component map as well as outputting VHDL entity and frame to a file in character string mode for finalizing complete conversion.
Description
Technical field
The invention relates to the method that a kind of program language in higher converts hardware description language (VHDL) automatically to, especially refer to a kind of via converting original program code (source code) to expanding activity figure (Extended Activity Diagram, EAD), expanding activity figure is converted to nextport hardware component NextPort figure (Hardware Component Graph, HCG) and with nextport hardware component NextPort figure be converted to three phase transition such as hardware description language, and program language in higher converted automatically to the method for hardware description language (VHDL).
Background technology
Traditional program language in higher (for example: Java, C, C++ etc.) can't directly be changed the described function of source code and (for example: VHDL) produce corresponding hardware description language.Because traditional hardware description language (for example: VHDL) and be not suitable for directly describing the programmed logic of program language in higher and carry out flow process, therefore the described function of program language in higher directly can't be converted to corresponding hardware description language, and cause the puzzlement in the design.And because program language in higher is of a great variety, so although designed program function is identical, also can can't unify complete execution flow process because of the characteristic of program language, cause the puzzlement in the nextport hardware component NextPort design, therefore, known method can't be directly changed into corresponding hardware description language with the described function of program language in higher, and gives improved necessity.
Summary of the invention
The object of the present invention is to provide a kind of program language in higher to convert the method for hardware description language automatically to.
For achieving the above object.Provided by the inventionly convert program language in higher the method for hardware description language to automatically, comprise the following steps:
(A) read the source code of a program language in higher;
(B) source code with this program language in higher converts an expanding activity figure to;
(C) convert this expanding activity figure to a nextport hardware component NextPort figure;
(D) convert this nextport hardware component NextPort figure to hardware description language; And
(E) export this hardware description language.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this program language in higher is Java, C or C++ program language.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this expanding activity is a kind of process control chart of representative.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this expanding activity figure comprises: beginning (start), finish (end), intermediate point (curve point), little computing (micro-operation), bifurcated (fork), link (ioin), select (select), merge (merge) totally eight kinds of nodes.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this nextport hardware component NextPort figure is with the annexation between expression nextport hardware component NextPort and the nextport hardware component NextPort.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this nextport hardware component NextPort figure comprises: start node, end node and three kinds of kenels of component nodes.
Describedly convert program language in higher the method for hardware description language to automatically, wherein this hardware description language is VHDL or Verilog.
Describedly convert program language in higher the method for hardware description language to automatically, wherein step (A) also comprises following substep:
(A1) read the source code of delegation's program language in higher;
When (A2) not being a narration instruction, non-narration instruction transformation is become corresponding subactivity figure, again execution in step (A1) as this source code that reads;
(A3) be when instruction narration as this source code that reads, and the place ahead of should narration instructing convert this narrative to a subactivity figure when narrative is arranged;
(A4) produce one and select node;
(A5) produce two intermediate points, this two intermediate point connects this selection node;
(A6) narrative is converted to corresponding subactivity figure;
(A7) produce a merge node to merge subactivity figure;
(A8) connect this narrative via changing the back subactivity figure that is produced to right intermediate point;
(A9) connect this narrative via changing the back subactivity figure that is produced to merge node; And
(A10) judge whether to still have instruction not convert subactivity figure to, if still have, execution in step (A1) again, otherwise, the activity diagram of a complete son of output.
Describedly convert program language in higher the method for hardware description language to automatically, wherein in step (A3), this narration instruction comprises: for, while, do, if, switch instruction.
Describedly convert program language in higher the method for hardware description language to automatically, wherein step (B) also comprises following substep:
(B1) read a subactivity figure among this expanding activity figure, and when the subactivity figure of this expanding activity figure all has been read, execution in step (B5);
(B2) when judging that kenel under this subactivity figure that reads is bifurcated, binding or merges wherein a period of time, be directly changed into corresponding nextport hardware component NextPort figure, and execution in step (A);
(B3) when judging that this subactivity figure that reads be little computing kenel, should carry out grammatical analysis conversion by little operator activity diagram, and convert little operator activity diagram to corresponding nextport hardware component NextPort figure, again execution in step (B1);
(B4) when judging that this subactivity figure that reads be when selecting kenel, after the mark on the output terminal on these nextport hardware component NextPorts figure is analyzed, carry out grammatical analysis conversion again, and after this chooser activity diagram converts nextport hardware component NextPort figure to, again execution in step (B1); And
(B5) connect input end and the output terminal of these nextport hardware component NextPorts figure, export complete nextport hardware component NextPort figure.
Describedly convert program language in higher the method for hardware description language to automatically, wherein step (C) also comprises following substep:
(C1) read a nextport hardware component NextPort figure, wherein this nextport hardware component NextPort figure includes a plural number nextport hardware component NextPort figure;
(C2) find out the initial node of this nextport hardware component NextPort figure, to obtain corresponding sub-nextport hardware component NextPort figure;
(C3) analyze the information of this start node,,, all analyze up to all start nodes and finish to produce the entity of hardware description language in order to do the assembly that adds input and output;
(C4) judge the type of node among this nextport hardware component NextPort figure, produce corresponding hardware description language object, and relevant information is write in the framework of hardware description language;
(C5) online according to this nextport hardware component NextPort figure, the signal that produces corresponding hardware description language assembly connects; And
(C6) export the entity and the framework of hardware description language to archives in the character string mode.
Describedly convert program language in higher the method for hardware description language to automatically, wherein in step (C4), be to use assembly using mode, to produce corresponding hardware description language object.
Describedly convert program language in higher the method for hardware description language to automatically, wherein in step (C1), also comprise and this nextport hardware component NextPort figure is converted to one revises nextport hardware component NextPort figure, in order to do carrying out the hardware description language conversion.
Program language in higher of the present invention (for example: Java, C, C++) converts the method for hardware description language (VHDL) automatically to can changing the mechanism by three phases, and the described function of program language in higher directly is converted to corresponding hardware description language, it is not subject to the kind of program language in higher, and can unify complete execution flow process, and can not cause the puzzlement in the nextport hardware component NextPort design.
Description of drawings
Fig. 1 is directly changed into three phase transition flow processs of hardware description language for the program language in higher of a preferred embodiment of the present invention.
Fig. 2 is a defined activity diagram among the UML of a preferred embodiment of the present invention.
Fig. 3 is a defined activity diagram among the EAD of a preferred embodiment of the present invention.
Fig. 4 converts the flow path switch of EAD to for the source code of a preferred embodiment of the present invention.
Fig. 5 converts the complete flow path switch of EAD to for the source code of a preferred embodiment of the present invention.
Fig. 6 A is the JAVA program of a preferred embodiment of the present invention.
Fig. 6 B is the EAD of the JAVA program correspondence of a preferred embodiment of the present invention.
Fig. 7 A is the start node figure of a preferred embodiment of the present invention.
Fig. 7 B is the end node figure of a preferred embodiment of the present invention.
Fig. 7 C is the component nodes figure of a preferred embodiment of the present invention.
Fig. 7 D is the control path node of a preferred embodiment of the present invention.
Fig. 7 E is the data routing node of a preferred embodiment of the present invention.
Fig. 8 converts process flow diagram with nextport hardware component NextPort to for the EAD of a preferred embodiment of the present invention.
Fig. 9 is the pairing HCG figure of the EAD of a preferred embodiment of the present invention.
Figure 10 converts the process flow diagram of VHDL hardware description language to for the nextport hardware component NextPort figure (HCG) of a preferred embodiment of the present invention.
Figure 11 is the synoptic diagram of the Java totalizer of a preferred embodiment of the present invention.
Figure 12 is the synoptic diagram of the Java totalizer corresponding hardware component drawings of a preferred embodiment of the present invention.
Figure 13,14,15,16,17 be a preferred embodiment of the present invention nextport hardware component NextPort figure makeover process synoptic diagram.
Figure 18,19,20,21,22,23,24,25 converts the synoptic diagram of VHDL program code to for the nextport hardware component NextPort figure of a preferred embodiment of the present invention.
Embodiment
Because traditional method can't directly be directly changed into hardware description language with program language in higher, therefore, the present invention proposes a kind of three phase transition methods, as shown in Figure 1, with the described function of program language in higher (for example: Java, C, C++) via the original program code convert to expanding activity figure (Source code → EAD), expanding activity figure convert to nextport hardware component NextPort figure (EAD → HCG), and nextport hardware component NextPort figure be converted to the hardware description language (HCG → VHDL) conversion of three phases, and program language in higher is changed into hardware description language automatically.As shown in Figure 1, in first stage (among the Sourcecode → EAD), at first read the source code (step S101) of a program language in higher, convert the original program code of program language in higher to an expanding activity figure (step S102), then, enter subordinate phase (EAD → HCG), convert expanding activity figure to a nextport hardware component NextPort figure (step S103), at last, carry out the phase III (HCG → VHDL), online according to nextport hardware component NextPort figure, produce corresponding hardware description language (signal of VHDL assembly connects) (step S104), and export entity and the framework of VHDL to archives in the character string mode, (for example: the VHDL program code) (step S105) produce corresponding hardware description language.
As mentioned above, in the phase one, must convert intermediate form one an activity diagram (Activity Diagram to by first original program code with program language in higher, AD), AD is a kind of description figure of flow process, see also and Figure 2 shows that UML (Unified Modeling Language, UML) defined activity diagram in, it includes five kinds of component drawings: Action state, fork, join, select and merge, in the present invention, in order to keep the required information of some programs, therefore, must revise the assembly of part A D, employed activity diagram is called expanding activity figure (Extended activity diagram, EAD), see also shown in Figure 3.
As shown in Figure 3, EAD is a kind of control chart that converts corresponding flow process in order to the source code with higher level lanquage to, it is made up of a plurality of nodes (node), by the combination of different nodes constituting subactivity figure (sub-graph), three parts such as each self-contained initial, execution and end among each subactivity figure.In the present embodiment, defined multiple different node.Various node below makes introductions all round:
1. begin (start) node: the beginning of a sub-activity diagram of expression;
2. finish (end) node: the end of a sub-activity diagram of expression;
3. intermediate point (curve point) node: represent the connection of two directive connecting lines (edge), do not have actual influence, be generally used for making things convenient for the temporary purposes of transfer process for execution;
4. little computing (micro-operation) node: the processing of an expression expression narration (expressionstatement) or representation (expression);
5. bifurcated (fork) node: represent parallel execution;
6. link (join) node: expression has only when all little computings all arrive, and sending of output signal just arranged;
7. select (select) node: after being illustrated in decoding, can select to send a suitable output signal; And
8. merge (merge) node: expression is merged back output with input signal.
Above-mentioned each node is considered as an object, in this object, can two kinds of data kenels of record connect node (In-Node) of oneself and the node (Out-Node) that oneself will link to each other with other with representative, its node kenel can change with grammer, when resolving each section grammer, all can produce corresponding subactivity figure, and the In-Node and the Out-Node that write down this subactivity figure connect use for other subactivity figure.According to this connected mode, the generation of each section grammer neutron activity diagram also makes in a like fashion.After each subactivity figure linked to each other, can produce and convert the program source code to corresponding activity diagram, present the programmed logic of source code and carry out flow process with visual way.
Fig. 4 shows the flow process that program language in higher is converted automatically to expanding activity figure.As shown in Figure 4, be example with the JAVA program language, to convert the JAVA program to expanding activity figure in fact.It utilizes JavaCC (Java Compiler Compiler, JavaCC) defined Java standard syntax specification is basis (using JDK (Java Development Kit) 1.5), in the grammar of JavaCC file, add one section java applet, and produce Java grammer archives of revising.JavaCC then produces Java resolver (Java Parser) classification and required other classification that uses of Java resolver according to these Java grammer archives, and the Java resolver classification that this generates can provide the function that is converted to corresponding EAD from the Java source code.In the present embodiment, Java resolver classification is integrated in the area of computer aided circuit design software, make software have the function of conversion Java source code to EAD, then, complete Java source code is imported among the Java Parser, different mark (token) in the Java Parser meeting amenable to process, the corresponding new instruction that produces EAD in grammar file is changed out with the EAD figure then.
The present invention proposes a complete flow path switch, see also shown in Figure 5, in the time source code will being converted automatically to corresponding expanding activity figure, at first, read the source code (step S501) of delegation's program language in higher (high levellanguage), then, judge whether the kenel of source code is a narration instruction (statement instruction) (step S502), in the present embodiment, the narration instruction comprises: for, while, do, if, switch instruction.When the kenel of source code is not wherein any instruction in the above-mentioned narration instruction, this non-narration instruction is directly changed into corresponding subactivity figure (step S503), read the source code (step S501) of next line program language in higher more again.
When step S502 judges source code is when instruction narration, need again the place ahead of Rule of judgment expression formula whether one narrative (statement) (step S504) is arranged, if narrative is arranged, convert narrative to corresponding subactivity figure (sub-graph) (step S505) earlier in conditional expression the place ahead.
If no narrative, then directly produces one in conditional expression the place ahead and selects node (selectnode) (step S506); Then, produce two intermediate points (curve point) (step S507), this two intermediate point is connected to the selection node; Then, again narrative is converted to corresponding subactivity figure (step S508), afterwards, produce a merge node (merge node) to merge subactivity figure (step S509); Connect this narrative again via changing the back subactivity figure that is produced to right intermediate point (step S510), connect this narrative via changing the back subactivity figure that is produced to merge node (step S511), at last, judge whether to still have instruction not convert subactivity figure (step S512) yet to again, if still have, then get back to step S501 to read the source code of next line program language in higher again,, then export a complete EAD (step S513) if not having instruction need change.
Via above-mentioned steps, convert one section complete JAVA program language to corresponding EAD, present the programmed logic of source code and carry out flow process with visual means.See also shown in Figure 6ly, Fig. 6 A is the program of utilizing If Statement and being write, and flow path switch and rule according to above-mentioned are convertible into corresponding EAD, shown in Fig. 6 B.In addition, identical program is utilized above-mentioned flow path switch and rule, also is convertible into corresponding EAD.Because the difference of JAVA program syntax, therefore the EAD that is produced is also inequality.
After above-mentioned conversion, finished the conversion of phase one, then, carry out the conversion of subordinate phase, expanding activity figure being converted to nextport hardware component NextPort figure (HCG), represent relation between program language in higher and the hardware with HCG.
See also the figure specification figure of the nextport hardware component NextPort figure shown in Fig. 7 A～7C, HCG is divided into into three kinds of kenels:
1. start node (start node): shown in Fig. 7 A, start node has write down class name, method name, parameter, local variable, global variable, the returntype of JAVA program; It is defined as follows:
I. the information of method (method) comprises the title of method and modifies son (modifier);
Ii. the information of passback value comprises its kenel, position size and passback value title;
Iii. the information of parameter (parameter) comprises its kenel, position size and parameter name;
Iv. the information of area variable (local variable) comprises kenel, position size and area variable title.
2. end node (end node): shown in Fig. 7 B, end node method for expressing (method) finishes, and indicates the variable that tendency to develop is returned; Wherein, the content of end node is the name variable of desire passback, if do not return any variable, then keyword is VOID.
3. component nodes (component node): shown in Fig. 7 C, component nodes indicates nextport hardware component NextPorts such as register, fork, adder...., and has directional ray to be connected with one between node and node and indicate a certain input port (input port) that a certain output port (output port) from origin object is connected to destination object.
Component nodes can be subdivided into two main portions again:
(1) control path module (Control path module) is consulted shown in Fig. 7 D, and it comprises:
■ string type assembly (Q-element) represents that its corresponding hardware must carry out in regular turn when carrying out;
Parallel execution when ■ block form assembly (Fork-element) expression corresponding hardware is carried out;
■ Synchronization Component (Join-element) expression corresponding hardware just has sending of output signal when related operation all arrives;
■ conditional branching assembly (Decoder-element) expression corresponding hardware can select to send a suitable output signal after decoding;
■ merge module (Merge element) expression corresponding hardware is merged back output with input signal;
(2) datapath module (Data path module) is consulted shown in Fig. 7 E, and it comprises:
■ arithmetic and logical unit (ALU): AND-element, OR-element, XOR-element, ADD-element, SUB-element, MUL-element, DIV-element;
■ buffer: register-element;
■ multi-function device and separate multi-function device: RMUXDEMUX-element, WMUXDEMUX-element;
■ constant (Constants): constant-element.
Wherein, the content representation method of component nodes is divided into following two:
(1) representation distinguished of need such as buffer, constant label is:
Component Name _ _ name variable (Component name_variable name);
(2) representation that do not need label to distinguish such as MICROOP, CMP, MERGE is:
Component Name (Component name);
And online representation is between the node:
The input end of the output terminal → impact point of starting point;
Utilize the figure specification figure of above-mentioned nextport hardware component NextPort figure, EAD can be converted to and the more related nextport hardware component NextPort figure of nextport hardware component NextPort.
Fig. 8 shows that expanding activity figure (EAD) converts to and the process flow diagram of nextport hardware component NextPort (HCG), at first, read the subactivity figure (step S801) among this expanding activity figure, then, judge the affiliated kenel (step S802) of the subactivity figure that this reads, when the kenel of this subactivity figure that reads is bifurcated (fork), link (join), or merge (merge) one of them the time, be directly changed into corresponding nextport hardware component NextPort figure (step S803), afterwards, again read the subactivity figure among this expanding activity figure again, when all subactivity figure all have been read and have converted to till the corresponding nextport hardware component NextPort figure.
When step S802 judges that this subactivity figure that reads is little computing (micro-operation) kenel, to carry out grammatical analysis conversion (step S804) to little operator activity diagram, again the chooser activity diagram is converted to (step S806) behind the corresponding nextport hardware component NextPort figure, again read the subactivity figure in this activity diagram, when all subactivity figure all have been read and have converted to till the corresponding nextport hardware component NextPort figure.
When step S802 judges this subactivity figure that reads is when selecting (select) kenel, earlier the mark (label) on the output terminal on these nextport hardware component NextPorts figure is analyzed (step S805), afterwards, the chooser activity diagram is carried out grammatical analysis conversion (step S804), again the chooser activity diagram is converted to corresponding nextport hardware component NextPort figure (step S806), after all subactivity figure all have been read and have converted corresponding nextport hardware component NextPort figure (step S807) to, produce input end and output terminal (step S808) that connecting line connects these nextport hardware component NextPorts figure, at last, promptly exportable complete nextport hardware component NextPort figure (step S809).
Via above-mentioned steps, a complete EAD converts corresponding nextport hardware component NextPort figure (HCG) (as shown in Figure 9) to, wherein, uppermost node is start node (Start Node), and start node is noted down class information and the method information in the JAVA program respectively; Among Fig. 9 the node of below be end node (end node), end node represents that this method has finished and requires return value; Remaining node then indicates nextport hardware component NextPorts such as register, micro-operation, fork and adder respectively among Fig. 9, and indicate with a directive connecting line between node and the node, be connected to an input port of destination object from an outputport of origin object.
After above-mentioned conversion, finished the conversion of subordinate phase, then, carry out the conversion of phase III, will be according to nextport hardware component NextPort figure online, the signal that produces corresponding VHDL assembly connects, and export entity and the framework of VHDL to archives in the character string mode, finish whole conversion.
Figure 10 is the process flow diagram that nextport hardware component NextPort figure of the present invention (HCG) converts the VHDL hardware description language to.At first, read a nextport hardware component NextPort figure (HCG) (step S1001), wherein this nextport hardware component NextPort figure (HCG) includes a plural number nextport hardware component NextPort figure.Then, revise nextport hardware component NextPort figure (step S1003) since between the nextport hardware component NextPort of nextport hardware component NextPort figure (HCG) and reality without any connection, so can't directly convert nextport hardware component NextPort figure (HCG) to the VHDL hardware description language.So need to revise earlier nextport hardware component NextPort figure (HCG), to allow the assembly among the revised nextport hardware component NextPort figure (HCG) can be corresponding with the assembly of VHDL hardware description language.
Present embodiment is that the Java totalizer with Figure 11 is that example describes, and Figure 12 is this Java totalizer corresponding hardware component drawings (HCG).At first, by classification information (class info) and nextport hardware component NextPort figure (HCG), find out corresponding to the open method among the nextport hardware component NextPort figure (HCG) (public method), and partly connecing a line from method start node (method start node) is connected to classification start node (class start node) open method (public method).This connects online label " method_namereq4p ", have the input signal that a name on the corresponding hardware interfaces is called method_name Req4p to represent this open method (public method).The name that this input signal can be received method start node (method start node) is called the port of req4p.And connect a line from classification start node (classstart node) and be connected to method start node (method start node).This connects online label " ack4p method_name ", expression can connect a line is called method_name Ack4p to a name on the hardware interface output signal (as shown in figure 13) from the ack4p port of method start node (method startnode) at last.
Because each passback (return) can reportedly go out a number, and be returned to start node (start node) finishing a signal, thus run into one when judging formula, for the situation of different passback values is arranged.At this moment, then need merge a plurality of passback nodes (merge multiple return node).It puts into a buffer (register) to all values that will return (return value) earlier, this buffer (register) called after " retMethod_name ", use merge module (Merge element) that signal line is received an end node (end node) again, its bookmark name is " return retMethod_name.Because end node (end node) is only represented the end on the flow process, in hardware, do not represent in all senses, and in asynchronous system, carry out and finish to mean that having a passback signal (acknowledgement) passes back, therefore again for end node (end node) being removed and being taken back to method start node (method start node) (as shown in figure 14).
By classification information (class info) and nextport hardware component NextPort figure (HCG), which parameter (parameter) and the passback value (return value) corresponding to nextport hardware component NextPort figure (HCG) is to disclose (public) as can be known.Disclosed parameter (parameter) and passback value (return value) are received classification start node (class startnode), represent these nodes have corresponding hardware interfaces can for outside signal export into.Part in parameter can connect the buffer node (register node) of an input signal from classification start node (class start node) to parameter, and its label is " parameter_name w ", the expression data are input to the buffer from hardware interface.And can connect a signal line to hardware interface from the buffer node (register node) of parameter, and its label is " ack4p parameter_name " represent to confirm that from buffer passback one (acknowledgment) signal is to hardware interface.Passback value (return value) then connects the buffer node (register node) of a line to the passback value from method start node (method start node).But identical because of the port of its output with the port of receiving classification start node (class start node), return buffer node (return register node) so must assign to the line of receiving classification start node (class start node) with a node arranged side by side (fork node).And passback buffer node (return register node) also can connect a line to the worth output of classification start node (class start node) representative passback, and its label is " qretMethod_name " (as shown in figure 15).
Collect its method information (class info) from classification information (class info), and by collecting its output/input connecting line (in/out edges) among the nextport hardware component NextPort figure (HCG), with production method call information (method call info.).Utilizing method call information (method call info.) that the connecting line that is connected to method calling node (method call node) among the nextport hardware component NextPort figure (HCG) is connected to method start node (method start node) instead again comes method for expressing to call out (method call).Must add multi-function device when online and separate multi-function device and control output and go into (as shown in figure 16) handling.A plurality of buffers usually appear in nextport hardware component NextPort figure (HCG).But the buffer of same label refers to same buffer in fact, therefore needs to merge the buffer of these same meanings, to form correction nextport hardware component NextPort figure (modified HCG) as shown in figure 17.
Please consult again shown in Figure 10, through behind the step S1001, carry out revise nextport hardware component NextPort figure (step S1003) after, find out the initial node (Start Node) (step S1005) of this nextport hardware component NextPort figure, to obtain corresponding sub-nextport hardware component NextPort figure.Start node among the step S1005 (Start Node) is meant method start node (method start node).At this moment, can be corresponding one by one owing to revise nextport hardware component NextPort figure (modified HCG) with VHDL hardware description language object, so begin to convert to VHDL hardware description language object by method start node (method startnode).
Step S1007 analyzes the information of this method start node (method start node), in order to do the assembly that adds input and output, produces the entity (entity) of hardware description language, all analyzes up to all start nodes (Start Node) and finishes.
Please in the lump with reference to Figure 18～25, Figure 18～25th, the VHDL program code of being changed out according to the nextport hardware component NextPort figure of Fig. 9 in the present embodiment.In Figure 18～25, the title of entity (entity) is method start node (method start node), and the connection in the method start node (method start node) now is converted to output in the entity (entity)/and input port.
Step S1009 is to judge the type of node (node) among this nextport hardware component NextPort figure, produces corresponding hardware description language (VHDL) object, and relevant information is write in the framework (Architecture) of hardware description language.Wherein, use assembly (component instantiation) mode of using, to produce corresponding hardware description language (VHDL) object.
Step S1011 is according to revising the online of nextport hardware component NextPort figure, and the signal that produces corresponding hardware description language (VHDL) assembly connects.In step S1013, with entity (entity) and framework (Architecture) output the archives as Figure 18～25 shown in of character string mode with hardware description language (VHDL).Wherein, this revise nextport hardware component NextPort figure can with the VHDL assembly one to one, so can convert the VHDL program code easily to.Can avoid nextport hardware component NextPort figure (HCG) can't convert the problem of correct VHDL program code to.
Via above-mentioned steps, can in three phases, convert a complete HCG to corresponding hardware description language.
By above explanation as can be known, program language in higher of the present invention (for example: Java, C, C++) converts the method for hardware description language (VHDL) automatically to can changing the mechanism by three phases, and the described function of program language in higher directly is converted to corresponding hardware description language, it is not subject to the kind of program language in higher, and can unify complete execution flow process, and can not cause the puzzlement in the nextport hardware component NextPort design.
The foregoing description only is to give an example for convenience of description, and the claim scope that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (13)
1. one kind converts program language in higher the method for hardware description language to automatically, comprises the following steps:
(A) read the source code of a program language in higher;
(B) source code with this program language in higher converts an expanding activity figure to;
(C) convert this expanding activity figure to a nextport hardware component NextPort figure;
(D) convert this nextport hardware component NextPort figure to hardware description language; And
(E) export this hardware description language.
2. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein this program language in higher is Java, C or C++ program language.
3. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein this expanding activity is a kind of process control chart of representative.
4. the method that program language in higher is converted automatically to hardware description language as claimed in claim 1, it is characterized in that wherein this expanding activity figure comprises: beginning (start), end (end), intermediate point (curve point), little computing (micro-operation), bifurcated (fork), binding (join), selection (select), merging (merge) be totally eight kinds of nodes.
5. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein this nextport hardware component NextPort figure is with the annexation between expression nextport hardware component NextPort and the nextport hardware component NextPort.
6. as claimed in claim 5ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein this nextport hardware component NextPort figure comprises: start node, end node and three kinds of kenels of component nodes.
7. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein this hardware description language is VHDL or Verilog.
8. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein step (A) also comprises following substep:
(A1) read the source code of delegation's program language in higher;
When (A2) not being a narration instruction, non-narration instruction transformation is become corresponding subactivity figure, again execution in step (A1) as this source code that reads;
(A3) be when instruction narration as this source code that reads, and the place ahead of should narration instructing convert this narrative to a subactivity figure when narrative is arranged;
(A4) produce one and select node;
(A5) produce two intermediate points, this two intermediate point connects this selection node;
(A6) narrative is converted to corresponding subactivity figure;
(A7) produce a merge node to merge subactivity figure;
(A8) connect this narrative via changing the back subactivity figure that is produced to right intermediate point;
(A9) connect this narrative via changing the back subactivity figure that is produced to merge node; And
(A10) judge whether to still have instruction not convert subactivity figure to, if still have, execution in step (A1) again, otherwise, the activity diagram of a complete son of output.
9. as claimed in claim 8ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein in step (A3), this narration instruction comprises: for, while, do, if, switch instruction.
10. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein step (B) also comprises following substep:
(B1) read a subactivity figure among this expanding activity figure, and when the subactivity figure of this expanding activity figure all has been read, execution in step (B5);
(B2) when judging that kenel under this subactivity figure that reads is bifurcated, binding or merges wherein a period of time, be directly changed into corresponding nextport hardware component NextPort figure, and execution in step (A);
(B3) when judging that this subactivity figure that reads be little computing kenel, should carry out grammatical analysis conversion by little operator activity diagram, and convert little operator activity diagram to corresponding nextport hardware component NextPort figure, again execution in step (B1);
(B4) when judging that this subactivity figure that reads be when selecting kenel, after the mark on the output terminal on these nextport hardware component NextPorts figure is analyzed, carry out grammatical analysis conversion again, and after this chooser activity diagram converts nextport hardware component NextPort figure to, again execution in step (B1); And
(B5) connect input end and the output terminal of these nextport hardware component NextPorts figure, export complete nextport hardware component NextPort figure.
11. as claimed in claim 1ly convert program language in higher the method for hardware description language to automatically, it is characterized in that wherein step (C) also comprises following substep:
(C1) read a nextport hardware component NextPort figure, wherein this nextport hardware component NextPort figure includes a plural number nextport hardware component NextPort figure;
(C2) find out the initial node of this nextport hardware component NextPort figure, to obtain corresponding sub-nextport hardware component NextPort figure;
(C3) analyze the information of this start node,,, all analyze up to all start nodes and finish to produce the entity of hardware description language in order to do the assembly that adds input and output;
(C4) judge the type of node among this nextport hardware component NextPort figure, produce corresponding hardware description language object, and relevant information is write in the framework of hardware description language;
(C5) online according to this nextport hardware component NextPort figure, the signal that produces corresponding hardware description language assembly connects; And
(C6) export the entity and the framework of hardware description language to archives in the character string mode.
12. as claimed in claim 11ly convert program language in higher the method for hardware description language to automatically, it is characterized in that, wherein in step (C4), be to use assembly using mode, to produce corresponding hardware description language object.
13. the method that program language in higher is converted automatically to hardware description language as claimed in claim 11, it is characterized in that, wherein in step (C1), also comprise and this nextport hardware component NextPort figure is converted to one revises nextport hardware component NextPort figure, to carry out the hardware description language conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100049032A CN100470468C (en) | 2006-01-11 | 2006-01-11 | Method for automatic converting higher-order program language into hardware descriptive language |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100049032A CN100470468C (en) | 2006-01-11 | 2006-01-11 | Method for automatic converting higher-order program language into hardware descriptive language |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101000541A true CN101000541A (en) | 2007-07-18 |
| CN100470468C CN100470468C (en) | 2009-03-18 |
Family
ID=38692530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100049032A Expired - Fee Related CN100470468C (en) | 2006-01-11 | 2006-01-11 | Method for automatic converting higher-order program language into hardware descriptive language |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100470468C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092588A (en) * | 2011-11-01 | 2013-05-08 | 镇江华扬信息科技有限公司 | Object-oriented VHDL (Vhsic Hardware Description Language) based language implementation method |
| CN103412783A (en) * | 2013-08-27 | 2013-11-27 | 杭州友声科技有限公司 | Method for converting script codes into user flow diagram based on business logic layer |
| CN110109658A (en) * | 2019-04-17 | 2019-08-09 | 首都师范大学 | A kind of ROS code generator and code generating method based on formalized model |
-
2006
- 2006-01-11 CN CNB2006100049032A patent/CN100470468C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092588A (en) * | 2011-11-01 | 2013-05-08 | 镇江华扬信息科技有限公司 | Object-oriented VHDL (Vhsic Hardware Description Language) based language implementation method |
| CN103412783A (en) * | 2013-08-27 | 2013-11-27 | 杭州友声科技有限公司 | Method for converting script codes into user flow diagram based on business logic layer |
| CN110109658A (en) * | 2019-04-17 | 2019-08-09 | 首都师范大学 | A kind of ROS code generator and code generating method based on formalized model |
| CN110109658B (en) * | 2019-04-17 | 2022-08-23 | 首都师范大学 | ROS code generator based on formalized model and code generation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100470468C (en) | 2009-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Gajski et al. | SpecC: Specification language and methodology | |
| US20070157132A1 (en) | Process of automatically translating a high level programming language into a hardware description language | |
| JP2003223473A (en) | Design method for integrated circuit and integrated circuit designed thereby | |
| CN101777004A (en) | Method and system for realizing BPEL sub-process multiplexing based on template in service-oriented environment | |
| JP3803561B2 (en) | Logic circuit design method | |
| CN100470468C (en) | Method for automatic converting higher-order program language into hardware descriptive language | |
| US20070271080A1 (en) | Model generation method for software/hardware collaboration design | |
| JPH11250112A (en) | Method and device for synthesizing hardware and recording medium recorded with hardware synthesizing program | |
| CN104503733A (en) | Merging method and device for state machine | |
| CN100468329C (en) | Method for automatic converting program language in higher level to activity diagram | |
| JP2007183897A (en) | Method for automatically converting high-level programming language into ead | |
| US8752075B1 (en) | Method for data transport | |
| CN100442224C (en) | Method for converting hardware component graph into hardware descriptive language | |
| CN100424639C (en) | Method for automatic converting extension active picture into hardware component picture | |
| CN106557312B (en) | Program development support device and program development support software | |
| JP2007183902A (en) | Automatic conversion method of extended activity diagram (ead) into hardware component graph (hcg) | |
| JP2001209670A (en) | High order synthesis method and recording medium used for execution of high order synthesis method | |
| JP4177851B2 (en) | Logic circuit design method | |
| CN101957772B (en) | Compiler for generating lightweight comparison instruction | |
| JP2008217071A (en) | High-level synthesis apparatus and high-level synthesis method | |
| Gajski et al. | Methodology for design of embedded systems | |
| US20070157147A1 (en) | Hardware component graph to hardware description language translation method | |
| WO2009128465A1 (en) | Service change component generation system, method and recording medium | |
| KR20140087557A (en) | A display device and a method for processing a screen using it | |
| Araki et al. | Rapid prototyping with HW/SW codesign tool |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090717 Address after: Taiwan, Taipei, China Co-patentee after: Datong University Patentee after: Tatung Company Address before: Taipei City, Taiwan, China Patentee before: Datong Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090318 Termination date: 20130111 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |