CN100424639C - Method for automatic converting extension active picture into hardware component picture - Google Patents
Method for automatic converting extension active picture into hardware component picture Download PDFInfo
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- CN100424639C CN100424639C CNB2006100049051A CN200610004905A CN100424639C CN 100424639 C CN100424639 C CN 100424639C CN B2006100049051 A CNB2006100049051 A CN B2006100049051A CN 200610004905 A CN200610004905 A CN 200610004905A CN 100424639 C CN100424639 C CN 100424639C
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Abstract
A method for automatically converting an extended activity diagram into hardware component graph includes using hardware element map to present connection relation between hardware element and hardware element and then generating program code of corresponding hardware description language according to said hardware component graph.
Description
Technical field
The invention relates to a kind of method of automatic converting extension active picture into hardware component picture, refer to that especially a kind of expanding activity figure of the execution flow process with representation program converts the step of hardware element figure to, be used for representing the annexation between hardware element and hardware element.
Background technology
Traditional hardware description language (for example: VHDL, Verilog) and can't directly be used for describing the programmed logic of program language in higher and carry out flow process, therefore, must convert program language in higher to UML (Unified ModelingLanguage earlier, UML) defined activity diagram (Activity Diagram in, be called for short AD), because AD is a kind of description figure of flow process, can be in order to the programmed logic and the execution flow process of expression program language in higher, but AD follows between the actual hardware element without any connection, therefore, also can't directly convert AD to hardware description language, simultaneously, therefore, known method can't be directly changed into program language in higher corresponding hardware description language, so give improved necessity.
Summary of the invention
The object of the present invention is to provide the method for a kind of automatic converting extension active picture into hardware component picture (HCG), so that expanding activity figure (EAD) can be converted to hardware element figure (HCG), the demand that is beneficial to follow-up emulation and is converted to hardware description language (VHDL) earlier.
Another object of the present invention is in the method that a kind of automatic converting extension active picture into hardware component picture (HCG) is provided, so that can utilize hardware element figure to represent annexation between hardware element and hardware element.
The invention provides a kind of method of automatic converting extension active picture into hardware component picture, this expanding activity figure includes a plurality of subactivity figure, it is characterized in that, this method comprises:
(A) read a subactivity figure among this expanding activity figure, and when the subactivity figure of this expanding activity figure all has been read, execution in step (E);
(B) when the affiliated type of judging this subactivity figure that reads be bifurcated, binding or when merging one of them, be directly changed into corresponding hardware element figure, and execution in step (A);
(C) when judging that this subactivity figure that reads is little arithmetic type, this little operator activity diagram is carried out grammatical analysis, and convert little operator activity diagram to corresponding hardware element figure, again execution in step (A);
(D) when judging that this subactivity figure that reads be the selection type, after the mark on the output terminal on this hardware element figure analyzed, carry out grammatical analysis again, and after this chooser activity diagram converts hardware element figure to, again execution in step (A); And
(E) connect input end and the output terminal of this hardware element figure, export complete hardware element figure.
Wherein this expanding activity figure comprises: beginning, end, intermediate point, little computing, bifurcated, binding, selection, merging be totally eight kinds of nodes.
Wherein this hardware element figure comprises: begin three types of end and elements.
Wherein this expanding activity figure is by being defined in the UML program language, and it represents a kind of process control chart.
Wherein this hardware element figure is used to represent the annexation between hardware element and the hardware element.
In the method for automatic converting extension active picture into hardware component picture of the present invention, expanding activity figure (Extended activity diagram) revises defined activity diagram (activity diagram) in the part UML program language, and expanding activity figure represents a kind of process control chart.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is the EAD figure specification figure of a preferred embodiment of the present invention.
Fig. 2 A is the start node figure of a preferred embodiment of the present invention.
Fig. 2 B is the end node figure of a preferred embodiment of the present invention.
Fig. 2 C is the element node diagram of a preferred embodiment of the present invention.
Fig. 2 D is the control path node of a preferred embodiment of the present invention.
Fig. 2 E is the data path node of a preferred embodiment of the present invention.
Fig. 3 A is little computing of a preferred embodiment of the present invention and the corresponding diagram of hardware element figure.
Fig. 3 B is little computing of a preferred embodiment of the present invention and the corresponding diagram of hardware element figure.
Fig. 3 C is little computing of a preferred embodiment of the present invention and the corresponding diagram of hardware element figure.
Fig. 3 D is selection of a preferred embodiment of the present invention and the corresponding diagram of hardware element figure.
Fig. 4 is that the EAD of a preferred embodiment of the present invention converts the process flow diagram with hardware element to.
Fig. 5 is the pairing EAD figure of the JAVA program of a preferred embodiment of the present invention.
Fig. 6 is the pairing HCG figure of the EAD of a preferred embodiment of the present invention.
Embodiment
Because traditional method can't directly be directly changed into program language in higher (High LevelLanguage) hardware description language (for example: VHDL, Verilog), therefore, when the user will be with program language in higher (for example: Java, C, C++ ...) convert hardware description language to before, must convert program language in higher to an intermediate form earlier, be called activity diagram (Activity Diagram is called for short AD) at this.AD is a kind of description figure of flow process, programmed logic and execution flow process with the expression program language in higher, but AD follows between the actual hardware element without any connection, therefore, must again AD be converted to (Hardware Component Graph with the more related hardware element figure of hardware element, be called for short HCG), could produce corresponding hardware description language according to hardware element figure and describe program language in higher.
In the present embodiment, utilize to revise part UML (Unified ModelingLanguage, UML) in the employed activity diagram of defined activity diagram be called expanding activity figure (Extended activity diagram, EAD).Wherein, a complete EAD is made up of a plurality of subactivity figure (sub-graph), EAD also is a kind of control chart that converts corresponding flow process in order to the source code with higher level lanquage to, it is made up of a plurality of nodes (node), is made up to constitute subactivity figure (sub-graph) by different nodes.In the present embodiment, see also the figure specification figure of subactivity figure shown in Figure 1, EAD is divided into into eight kinds of nodes:
1. begin (start) node: the beginning of a sub-activity diagram of expression;
2. finish (end) node: the end of a sub-activity diagram of expression;
3. intermediate point (curve point) node: represent the connection of two directive connecting lines (edge), do not have actual influence, be generally used for making things convenient for the temporary purposes of transfer process for execution;
4. little computing (micro-operation) node: represent the processing of a narration (expression statement) or representation (expression);
5. bifurcated (fork) node: represent parallel execution;
6. link (join) node: expression has only when all little computings all arrive, and sending of output signal just arranged;
7. select (select) node: after being illustrated in decoding, can select to send a suitable output signal; And
8. merge (merge) node: expression is merged back output with input signal.
Aforementioned each node is considered as an object, after each subactivity figure is linked to each other, can produce and convert the program source code to corresponding expanding activity figure, presents the programmed logic of source code and carries out flow process with visual way.
Above-mentioned content by among the present invention the figure specification of all subactivity figure of use introduce.
In an embodiment of the present invention, a complete EAD will convert corresponding hardware element figure (HCG) to, represents relation between program language in higher and the hardware with HCG.See also the figure specification figure of the hardware element figure shown in Fig. 2 A～Fig. 2 C, HCG is divided into into three kinds of kenels:
1. start node (start node): see also shown in Fig. 2 A, start node has write down class name, method name, parameter, local variable, global variable, the return type of JAVA program; Its parameter is defined as follows:
I, M are the information of method (method), comprise the title of method and modify son (modifier)
Ii, R are the information of passback value, comprise its kenel, position size and passback value title
Iii, P are the information of parameter (parameter), comprise its kenel, position size and parameter name
Iv, L are the information of area variable (local variable), comprise kenel, position size and area variable title
2. end node (end node): see also shown in Fig. 2 B, end node represents that this method finishes, and indicates the variable that tendency to develop is returned; Wherein, the content of end node End node is the name variable of desire passback, if do not return any variable, then keyword is VOID.
3. element node (component node): see also shown in Fig. 2 C, the element node indicates register, fork, adder ... Deng hardware element, and there is directional ray to be connected with one between node and node and indicates a certain input port that is connected to destination object from a certain output port of origin object.
In the present embodiment, element node (Component node) can be subdivided into two main portions again:
(1) control path module (Control path modules) sees also shown in Fig. 2 D, and it comprises:
■ string type element (Q-element)
■ block form element (Fork-element)
■ synchronous element (Join-element)
■ condition difference element (Decoder-element)
■ merges element (Merge element)
(2) data path module (Data path modules) sees also shown in Fig. 2 E, and it comprises:
■ arithmetic and logical unit (ALU): AND-element, OR-element, XOR-element, ADD-element, SUB-element, MUL-element, DIV-element,
■ buffer: register-element
■ multi-function device and separate multi-function device:
RMUXDEMUX-element、
WMUXDEMUX-element
■ constant (Constants): constant-element wherein, the content representation method of element node (Component node) is divided into following two:
(1) buffer, these representations that need label to distinguish of constant are: element title _ name variable (Component name_variable name)
(2) representation that do not need label to distinguish such as MICROOP, CMP, MERGE is:
Element title (Component name)
And online representation is between the node:
The input end of the output terminal → impact point of starting point (source node outputport → target node input port)
In the present embodiment, convert the EAD subgraph to corresponding hardware element figure, see also shown in Fig. 3 A, the left side is the subgraph of EAD, the right is corresponding hardware element figure, wherein, the subgraph of EAD is little computing (micro-operation) node (seeing also shown in Figure 1), and little compute node is in order to represent the processing of a narration (expression statement) or representation (expression).
Example 1: when narrating (expression statement) when being a=b, its pairing hardware element figure is a Q-element, at first, receive the signal of a req2p, then read the data of b, then the data storage with b arrives a, after finishing a=b, pass back to Q again, and send passback ack 2q, finish relative hardware element figure.
Example 2: see also shown in Fig. 3 B, the left side is the subgraph of EAD, the right is corresponding hardware element figure, the subgraph of EAD is little computing (micro-operation) node, when the narration (expressionstatement) of EAD is a=b+c, its pairing hardware element figure is a Q-element, at first, receive the signal of a req 2p, then read the data of b and c, see through the ADD-element addition again, and be stored into a, finish a=b+c after, pass back to Q again, and send passback ack 2q, finish relative hardware element figure.
Example 3: see also shown in Fig. 3 C, when the narration (expressionstatement) of EAD is sum+=i, at first, resolve sum+=i, that is sum=sum+i, therefore must be in conjunction with 2 Q-element, be divided into twice action, at last, send passback ack 2q, finish relative hardware element figure.
Example 4: see also shown in Fig. 3 D, when the instructing of EAD for the judgement formula, when judging a＞b or two kinds of situations of a＜=b, utilize a CMP to compare the size of a and b, at last and produce two paths, when a＞b (TRUE), then send a return path signal gt 4p, if a＜=b (FALSE) then sends a return path signal cf 4p by another path, pass back to D again, finish relative hardware element figure.
Utilize the figure specification figure of above-mentioned hardware element figure, EAD can be converted to and the more related hardware element figure of hardware element, Fig. 4 shows that EAD converts the process flow diagram with hardware element to, at first, read the subactivity figure (step S401) among this expanding activity figure, then, judge the affiliated kenel (step S402) of the subactivity figure that this reads, when the kenel of this subactivity figure that reads is bifurcated (fork), link (join), or merge (merge) a period of time wherein, be directly changed into corresponding hardware element figure (step S403), afterwards, again read the subactivity figure among this expanding activity figure again, when all subactivity figure all have been read and have converted to till the corresponding hardware element figure.
When in (step S402), judging that this subactivity figure that reads is little computing (micro-operation) kenel, to carry out grammatical analysis conversion (step S404) to little operator activity diagram, again the chooser activity diagram is converted to (step S406) behind the corresponding hardware element figure, again read the subactivity figure in this activity diagram, when all subactivity figure all have been read and have converted to till the corresponding hardware element figure.
When judging that in (step S402) this subactivity figure that reads is when selecting (select) kenel, earlier the mark (label) on the output terminal on these hardware elements figure is analyzed back (step S405), afterwards, the chooser activity diagram is carried out grammatical analysis conversion (step S404), again the chooser activity diagram is converted to (step S406) behind the corresponding hardware element figure, after all subactivity figure all have been read and have converted corresponding hardware element figure (step S407) to, produce input end and output terminal (step S408) that connecting line connects these hardware elements figure, at last, promptly exportable complete hardware element figure (step S409).
In the present invention, be to convert one section complete JAVA program language to corresponding hardware element figure, in the present embodiment, be example with a JAVA program that adds up,
Above-mentioned JAVA program is convertible into corresponding EAD figure, sees also shown in Figure 5ly, then, the EAD figure is converted to hardware element figure HCG, as shown in Figure 6 again.
By above explanation as can be known, the method of automatic converting extension active picture into hardware component picture of the present invention can be with multiple this different program language in higher (for example: Java, C, C++ ...) source code convert corresponding expanding activity figure (EAD) automatically to, see through expanding activity figure (EAD) again and convert (Hardware Component Graph to the more related hardware element figure of hardware element, HCG), could produce corresponding hardware description language according to hardware element figure and describe program language in higher.
Via above-mentioned transfer process, the JAVA program can be converted to hardware element figure, as shown in Figure 6, wherein, uppermost node is start node (Start Node), start node is noted down class information and the method information in the JAVA program respectively; Among Fig. 6 the node of below be end node (endnode), end node represents that this method has finished and requires return value; Remaining node then indicates hardware elements such as register, micro-operation, fork and adder respectively among Fig. 6, and indicate with a directive connecting line between node and the node, be connected to an input port of destination object from an output port of origin object.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (5)
1. the method for an automatic converting extension active picture into hardware component picture, this expanding activity figure includes a plurality of subactivity figure, it is characterized in that, and this method comprises:
(A) read a subactivity figure among this expanding activity figure, and when the subactivity figure of this expanding activity figure all has been read, execution in step (E);
(B) when the affiliated type of judging this subactivity figure that reads be bifurcated, binding or when merging one of them, be directly changed into corresponding hardware element figure, and execution in step (A);
(C) when judging that this subactivity figure that reads is little arithmetic type, this little operator activity diagram is carried out grammatical analysis, and convert little operator activity diagram to corresponding hardware element figure, again execution in step (A);
(D) when judging that this subactivity figure that reads be the selection type, after the mark on the output terminal on this hardware element figure analyzed, carry out grammatical analysis again, and after this chooser activity diagram converts hardware element figure to, again execution in step (A); And
(E) connect input end and the output terminal of this hardware element figure, export complete hardware element figure.
2. the method for automatic converting extension active picture into hardware component picture as claimed in claim 1 is characterized in that, wherein this expanding activity figure comprises: beginning, end, intermediate point, little computing, bifurcated, binding, selection, merging be totally eight kinds of nodes.
3. the method for automatic converting extension active picture into hardware component picture as claimed in claim 1 is characterized in that, wherein this hardware element figure comprises: begin three types of end and elements.
4. the method for automatic converting extension active picture into hardware component picture as claimed in claim 1 is characterized in that, wherein this expanding activity figure is by being defined in the UML program language, and it represents a kind of process control chart.
5. the method for automatic converting extension active picture into hardware component picture as claimed in claim 1 is characterized in that, wherein this hardware element figure is used to represent the annexation between hardware element and the hardware element.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050044532A1 (en) * | 2001-12-12 | 2005-02-24 | Gotthard Pfander | System and method for testing and/or debugging runtime sytems for solving mes manufacturing execution system problems |
| US20050144529A1 (en) * | 2003-10-01 | 2005-06-30 | Helmut Gotz | Method for defined derivation of software tests from use cases |
| US20050256665A1 (en) * | 2004-01-26 | 2005-11-17 | Jean Hartmann | System and method for model based system testing of interactive applications |
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| US20050044532A1 (en) * | 2001-12-12 | 2005-02-24 | Gotthard Pfander | System and method for testing and/or debugging runtime sytems for solving mes manufacturing execution system problems |
| US20050144529A1 (en) * | 2003-10-01 | 2005-06-30 | Helmut Gotz | Method for defined derivation of software tests from use cases |
| US20050256665A1 (en) * | 2004-01-26 | 2005-11-17 | Jean Hartmann | System and method for model based system testing of interactive applications |
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Effective date of registration: 20090424 Address after: Taiwan, Taipei, China Co-patentee after: Datong University Patentee after: Tatung Company Address before: Taipei City, Taiwan, China Patentee before: Datong Co., Ltd. |
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