CN103078728A - Time synchronizing system - Google Patents
Time synchronizing system Download PDFInfo
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- CN103078728A CN103078728A CN2013100472807A CN201310047280A CN103078728A CN 103078728 A CN103078728 A CN 103078728A CN 2013100472807 A CN2013100472807 A CN 2013100472807A CN 201310047280 A CN201310047280 A CN 201310047280A CN 103078728 A CN103078728 A CN 103078728A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
- H04J3/065—Synchronisation among TDM nodes using timestamps
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Abstract
The invention provides a time synchronizing system, which comprises a main station time server, sub-station time servers, a multiple-E1 (European basic muliplex rate)/PTP (precision time protocol) time channel adapter and single-E1/PTP time channel adapters, wherein the multiple-E1/PTP time channel adapter exchanges information with the single-E1/PTP time channel adapters through a transmission network, so as to realize time synchronizing. Since the number of equipment participating in the whole time synchronizing process is little, and the data exchange is only carried out among the main station time server, the multiple-E1/PTP time channel adapter, the single-E1/PTP time channel adapters and the sub-station time servers, the delay is greatly reduced, and the time synchronizing precision is greatly improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to clock synchronization system.
Background technology
Along with the development of technology, clock synchronization system is applied in increasing industry and field.For example, in power industry, clock synchronization system mainly with the time consistency of guaranteeing between power plant's power station collection control appliance, is convenient to analyze and monitoring operation of power networks state; In telecommunications industry, clock synchronization system is mainly used at charging and distributed data acquisition; In mobile field, clock synchronization system be mainly used in based on the base of time division multiplexing mechanism is vertical between accounting for synchronously.
In existing numerous clock synchronization system, having a kind of is by the SDH (Synchronous Digital Hierarchy) transmission network, utilize the E1 signal of SDH (Synchronous Digital Hierarchy), in conjunction with accurate clock synchronization protocol (Precision Time Protocol, PTP) technology reaches the time synchronized of substation and main website, and the technical scheme that this system adopts generally is applied to a main website to the scene of many substations.
Adaptive device by E1 passage transmission PTP signal only provides 1 road interface at present, so use this system to realize the process need of time synchronized, generally adopt the main station time server to go out 1 road PTP signal at the main website end, advance the PTP switch, by PTP switch expansion multichannel PTP signal, corresponding 1 to N is passed through the adapter that the E1 passage transmits the PTP signal respectively, being connected PTP OVER E1 adapter with the substation end by transmission network connects, the PTP OVER E1 adapter of substation end goes out the PTP signal and is connected with the substation time server, set up the PTP time channel path of ground whole process, realize time synchronized.
This implementation causes the main website end need to configure PTP switch and a plurality of PTP OVER E1 adapter, and number of devices is many, has increased the link that signal transforms, and is unfavorable for that practical implementation and synchronization accuracy improve.
Summary of the invention
Based on this, be necessary there is the problem that number of devices is many, synchronization accuracy is poor in many substations scene for existing clock synchronization system being applied to a main website, a kind of simple in structure and clock synchronization system with good synchronisation precision is provided.
A kind of clock synchronization system, comprise primary time server, sub-time server, many E1/PTP time channel adapter and single E1/PTP time channel adapter, described primary time server is connected with described many E1/PTP time channel adapter, described sub-time server is connected with described single E1/PTP time channel adapter, and described many E1/PTP time channel adapter is connected with described single E1/PTP time channel adapter by transmission network;
Described many E1/PTP time channel adapter is provided with ether PTP interface and a plurality of E1 interface, and described many E1/PTP time channel adapter is used for setting up the mapping of corresponding relation, realization ether PTP interface signal and the E1 interface signal of described a plurality of E1 interface and sub-time server hardware address to be conciliate mapping, according to the PTP agreement PTP message is processed;
Described single E1/PTP time channel adapter is provided with single ether PTP interface and single E1 interface, and described single E1/PTP time channel adapter be used for to be realized mapping is conciliate in the mapping of ether PTP interface signal and E1 interface signal, mapping is conciliate in the mapping of calculating described PTP interface signal and described E1 interface signal time-delay, according to described PTP agreement the PTP message processed.
Among embodiment, described many E1/PTP time channel adapter and described single E1/PTP time channel adapter are all realized by the FPGA design therein.
Among embodiment, described many E1/PTP time channel adapter comprises therein:
The first sync message processing unit, be used for sending sync message to described E1 interface with broadcast mode, described sync message is mapped to described E1 interface signal, calculates the processing time-delay of described sync message from described ether PTP interface to described E1 interface, insert described sync message correction territory field;
First follows message process unit, is used for following message to described E1 interface with the broadcast mode transmission, and the described message of following is mapped to described E1 interface signal;
The first Delay computing request message processing unit, be used for the processing time-delay of computing relay computation requests message from described E1 interface to described ether PTP interface, insert the correction territory of described Delay computing request message, record simultaneously the described sub-time server hardware address that E1 interface number and described Delay computing request message carry;
The first Delay computing request response message processing unit is used for the corresponding relation according to E1 interface number and described sub-time server hardware address, with described Delay computing request response message by sending with E1 interface corresponding to described sub-time server.
Among embodiment, described single E1/PTP time channel adapter comprises therein:
The second sync message processing unit, be used for sending sync message to described E1 interface and described PTP interface, with described sync message respectively solution be mapped to E1 interface signal and PTP interface signal, calculate described sync message in the solution mapping time-delay of E1 interface to described PTP interface, insert sync message correction territory field;
Second follows message process unit, be used for to send to follow message to described E1 interface and described PTP interface, with described follow message respectively solution be mapped to described E1 interface signal and described PTP interface signal;
The second Delay computing request message processing unit is used for realizing that substation PTP interface signal shines upon to the E1 interface signal, calculate described substation PTP interface signal to the mapping time-delay of described E1 interface signal, inserts the correction territory of described Delay computing request message;
The second Delay computing request response message processing unit is used for transmission lag computation requests response message to described E1 interface and described PTP interface, with described Delay computing request response message respectively solution be mapped to described E1 interface signal and described PTP interface signal.
Among embodiment, described primary time server is used for receiving time reference signal therein, and described time reference signal comprises satellite time signal and cesium-beam atomic clock time signal.
Among embodiment, described transmission network is synchronous digital transmission system therein.
Among embodiment, described sub-time server comprises PTP from the clock interface, described sub-time server process IEEE1588V2 agreement therein.
Among embodiment, described ether PTP interface physical interface is 100,000,000/gigabit Ethernet photoelectric port therein.
Among embodiment, the number of described single E1/PTP time channel adapter is between 2 to 32 therein.
Among embodiment, the number of described single E1/PTP time channel adapter and described substation time server equates therein.
Clock synchronization system of the present invention, comprise many E1/PTP time channel adapter and single E1/PTP time channel adapter, described many E1/PTP time channel adapter carries out information interaction by transmission network and described single E1/PTP time channel adapter, realize time synchronized, because participation device quantity is few in the process of whole time synchronized, its data interaction only is at the main station time server, many E1/PTP time channel adapter, carry out mutual between single E1/PTP time channel adapter and the substation time server, so its time-delay greatly reduces, its time synchronization accuracy is greatly improved, so clock synchronization system of the present invention is a kind of simple in structure and clock synchronization system with good synchronisation precision.
Description of drawings
Fig. 1 is the structural representation of one of them embodiment of clock synchronization system of the present invention.
Embodiment
As shown in Figure 1, a kind of clock synchronization system, comprise primary time server 100, sub-time server 200, many E1/PTP time channel adapter 300 and single E1/PTP time channel adapter 400, described primary time server 100 is connected with described many E1/PTP time channel adapter 300, described sub-time server 200 is connected with a plurality of described single E1/PTP time channel adapters 400, and described many E1/PTP time channel adapter is connected with a plurality of described single E1/PTP time channel adapters by transmission network;
Described many E1/PTP time channel adapter 300 is provided with ether PTP interface and a plurality of E1 interface, and described many E1/PTP time channel adapter is used for setting up the mapping of corresponding relation, realization ether PTP interface signal and the E1 interface signal of described a plurality of E1 interface and sub-time server hardware address to be conciliate mapping, according to the PTP agreement PTP message is processed;
Described single E1/PTP time channel adapter 400 is provided with single ether PTP interface and single E1 interface, and described single E1/PTP time channel adapter be used for to be realized mapping is conciliate in the mapping of ether PTP interface signal and E1 interface signal, mapping is conciliate in the mapping of calculating described PTP interface signal and described E1 interface signal time-delay, according to described PTP agreement the PTP message processed.
Clock synchronization system of the present invention, comprise many E1/PTP time channel adapter and single E1/PTP time channel adapter, described many E1/PTP time channel adapter carries out information interaction by transmission network and described single E1/PTP time channel adapter, realize time synchronized, because participation device quantity is few in the process of whole time synchronized, its data interaction only is at the main station time server, many E1/PTP time channel adapter, carry out mutual between single E1/PTP time channel adapter and the substation time server, so its time-delay greatly reduces, its time synchronization accuracy is greatly improved, so clock synchronization system of the present invention is a kind of simple in structure and clock synchronization system with good synchronisation precision.
Among embodiment, described many E1/PTP time channel adapter and described single E1/PTP time channel adapter are all realized by the FPGA design therein.
Among embodiment, described many E1/PTP time channel adapter comprises therein:
The first sync message processing unit, be used for sending sync message to described E1 interface with broadcast mode, described sync message is mapped to described E1 interface signal, calculates the processing time-delay of described sync message from described ether PTP interface to described E1 interface, insert described sync message correction territory field;
First follows message process unit, is used for following message to described E1 interface with the broadcast mode transmission, and the described message of following is mapped to described E1 interface signal;
The first Delay computing request message processing unit, be used for the processing time-delay of computing relay computation requests message from described E1 interface to described ether PTP interface, insert the correction territory of described Delay computing request message, record simultaneously the described sub-time server hardware address that E1 interface number and described Delay computing request message carry;
The first Delay computing request response message processing unit is used for the corresponding relation according to E1 interface number and described sub-time server hardware address, with described Delay computing request response message by sending with E1 interface corresponding to described sub-time server.
Among embodiment, described single E1/PTP time channel adapter comprises therein:
The second sync message processing unit, be used for sending sync message to described E1 interface and described PTP interface, with described sync message respectively solution be mapped to E1 interface signal and PTP interface signal, calculate described sync message in the solution mapping time-delay of E1 interface to described PTP interface, insert sync message correction territory field;
Second follows message process unit, be used for to send to follow message to described E1 interface and described PTP interface, with described follow message respectively solution be mapped to described E1 interface signal and described PTP interface signal;
The second Delay computing request message processing unit is used for realizing that substation PTP interface signal shines upon to the E1 interface signal, calculate described substation PTP interface signal to the mapping time-delay of described E1 interface signal, inserts the correction territory of described Delay computing request message;
The second Delay computing request response message processing unit is used for transmission lag computation requests response message to described E1 interface and described PTP interface, with described Delay computing request response message respectively solution be mapped to described E1 interface signal and described PTP interface signal.
The below will describe many E1/PTP time channel adapter and single E1/PTP time channel adapter in detail to the processing procedure of message.
Main website mails to the processing procedure of the sync message (PTP Sync message) of substation.
The main station time server sends PTP Sync message, many E1/PTP time channel adapter is received the PTPSync message, start ether PTP interface to the mapping process of E1 interface, finish PTP Sync message to the mapping of all N E1 interfaces, be equivalent to PTP Sync message and broadcast to all N E1 interfaces.Calculate simultaneously ether PTP interface Sync message and enter the processing time-delay (each E1 interface calculates respectively) that goes out to the E1 interface, insert Sync message correction territory field CorrectFieldSync1.The message of substation time server E1 interface is PTP Sync message+CorrectFieldSync1.This message of transmission network transparent transmission, the message that single E1/PTP time channel adapter device E1 interface enters also is PTP Sync message+CorrectFieldSync1.Single E1/PTP time channel adapter device is received PTP Sync message+CorrectFieldSync1 message, start, the E1 interface signal calculates the E1 interface to the solution mapping time-delay of PTP interface to the mapping of PTP interface signal solution, inserts Sync message correction territory field CorrectFieldSync2.The message that single E1/PTP time channel adapter device ether PTP interface goes out is that PTP Sync message+CorrectFieldSync1+CorrectFieldSync2 arrives sub-time server apparatus.
Main website mails to the processing procedure of following message (PTP follow up) message of substation.
Primary time server equipment sends PTP follow up message (PTP follow uo message), many E1/PTP time channel adapter device is received PTP follow up message message, start ether PTP interface to the mapping process of E1 interface, finish PTP follow up message message to the mapping of all N E1 interfaces, be equivalent to PTP follow up message message and broadcast to all N E1 interfaces.Transmission network transparent transmission PTP follow up message message, single E1/PTP time channel adapter device carry out the E1 interface signal to the mapping of PTP interface signal solution, transparent transmission PTP follow up message message.Sub-time server apparatus is received PTP follow up message message.
The processing procedure of the Delay computing request message (PTP Delay_Req message) of main website is mail in the substation.
Sub-time server apparatus sends PTP Delay_Req message (PTP Delay_Req message) after receiving PTP Sync message message and PTP follow up message message.Single E1/PTP time channel adapter device is received PTP Delay_Req message message, start ether PTP interface to the mapping process of E1 interface, calculate ether PTP interface PTP Delay_Req message message and enter the processing time-delay that goes out to the E1 interface, insert Delay_Req message correction territory field CorrectFieldDelayReq2.The message that single E1/PTP time channel adapter device E1 interface goes out is PTP Delay_Req message+CorrectFieldDelayReq2.This message of transmission network transparent transmission, the message that many E1/PTP time channel adapter device E1 interface enters also is PTP Delay_Req message+CorrectFieldDelayReq2.Many E1/PTP time channel adapter device is received PTP Delay_Req message+CorrectFieldDelayReq2 message, starting the E1 interface signal shines upon to PTP interface signal solution, calculate the E1 interface to the solution mapping time-delay of PTP interface, insert Delay_Req message correction territory field CorrectFieldDelayReq1.Many E1/PTP time channel adapter device is extraction source MAC (substation MAC) address from PTP Delay_Req message message, and records the corresponding relation between sub-time server hardware address and the E1 interface number.The message that many E1/PTP time channel adapter device ether PTP interface goes out is that PTP Delay_Req message+CorrectFieldDelayReq2+CorrectFieldDelayReq1 arrives primary time server equipment.
Main website mails to the processing procedure of the Delay computing request response message (PTP Delay_Resp message) of substation.
After primary time server equipment is received PTP Delay_Req message message, send PTP Delay_Resp message (PTP Delay_Resp message).Many E1/PTP time channel adapter device is received PTP Delay_Resp message message, extract the target MAC (Media Access Control) address (sub-time server hardware address) in the PTP Delay_Resp message message, according to the corresponding relation between many E1/PTP time channel adapter device server hardware address of sub-time and the E1 interface number, determining needs to start ether PTP interface to the E1 interface number of the mapping process of E1 interface, finishes PTP Delay_Resp message message to the mapping of determining the E1 interface.Transmission network transparent transmission PTP Delay_Resp message message, single E1/PTP time channel adapter device carry out the E1 interface signal to the mapping of PTP interface signal solution, transparent transmission PTP Delay_Resp message message.Sub-time server apparatus is received PTP Delay_Resp message message.
Among embodiment, described primary time server is used for receiving time reference signal therein, and described time reference signal comprises satellite time signal and cesium-beam atomic clock time signal.
Among embodiment, described transmission network is synchronous digital transmission system therein.
SDH (Synchronous Digital Hierarchy) is the digital communication system in a kind of optical fiber telecommunications system, and optical fiber communication obtains a wide range of applications in telecommunications network, and it has, and transmission quality is high, and reliability is high, strong security; Network delay is little, and antijamming capability is strong, noiseless accumulation, all-transparent network; Connected mode flexibly, network environment; Adopt the circuitous and standby mode of route, make the characteristics such as circuit safety is reliable.
Among embodiment, described sub-time server comprises PTP from the clock interface, described sub-time server process IEEE1588V2 agreement therein.
Among embodiment, described ether PTP interface physical interface is 100,000,000/gigabit Ethernet photoelectric port therein.
Among embodiment, the number of described single E1/PTP time channel adapter is between 2 to 32 therein.
Select the number of suitable single E1/PTP time channel adapter guaranteeing the equipment in the to greatest extent minimizing system in the time synchronized function of realizing, simplied system structure.
Among embodiment, the number of described single E1/PTP time channel adapter and described substation time server equates therein.
Each substation time server connects respectively the time synchronized function that a single E1/PTP time channel adapter can more efficient, more accurately be realized clock synchronization system of the present invention.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. clock synchronization system, it is characterized in that, comprise primary time server, sub-time server, many E1/PTP time channel adapter and single E1/PTP time channel adapter, described primary time server is connected with described many E1/PTP time channel adapter, described sub-time server is connected with described single E1/PTP time channel adapter, and described many E1/PTP time channel adapter is connected with described single E1/PTP time channel adapter by transmission network;
Described many E1/PTP time channel adapter is provided with ether PTP interface and a plurality of E1 interface, and described many E1/PTP time channel adapter is used for setting up the mapping of corresponding relation, realization ether PTP interface signal and the E1 interface signal of described a plurality of E1 interface and sub-time server hardware address to be conciliate mapping, according to the PTP agreement PTP message is processed;
Described single E1/PTP time channel adapter is provided with single ether PTP interface and single E1 interface, and described single E1/PTP time channel adapter be used for to be realized mapping is conciliate in the mapping of ether PTP interface signal and E1 interface signal, mapping is conciliate in the mapping of calculating described PTP interface signal and described E1 interface signal time-delay, according to described PTP agreement the PTP message processed.
2. clock synchronization system according to claim 1 is characterized in that, described many E1/PTP time channel adapter and described single E1/PTP time channel adapter are all realized by the FPGA design.
3. clock synchronization system according to claim 1 and 2 is characterized in that, described many E1/PTP time channel adapter comprises:
The first sync message processing unit, be used for sending sync message to described E1 interface with broadcast mode, described sync message is mapped to described E1 interface signal, calculates the processing time-delay of described sync message from described ether PTP interface to described E1 interface, insert described sync message correction territory field;
First follows message process unit, is used for following message to described E1 interface with the broadcast mode transmission, and the described message of following is mapped to described E1 interface signal;
The first Delay computing request message processing unit, be used for the processing time-delay of computing relay computation requests message from described E1 interface to described ether PTP interface, insert the correction territory of described Delay computing request message, record simultaneously the described sub-time server hardware address that E1 interface number and described Delay computing request message carry;
The first Delay computing request response message processing unit is used for the corresponding relation according to E1 interface number and described sub-time server hardware address, with described Delay computing request response message by sending with E1 interface corresponding to described sub-time server.
4. clock synchronization system according to claim 1 and 2 is characterized in that, described single E1/PTP time channel adapter comprises:
The second sync message processing unit, be used for sending sync message to described E1 interface and described PTP interface, with described sync message respectively solution be mapped to E1 interface signal and PTP interface signal, calculate described sync message in the solution mapping time-delay of E1 interface to described PTP interface, insert sync message correction territory field;
Second follows message process unit, be used for to send to follow message to described E1 interface and described PTP interface, with described follow message respectively solution be mapped to described E1 interface signal and described PTP interface signal;
The second Delay computing request message processing unit is used for realizing that substation PTP interface signal shines upon to the E1 interface signal, calculate described substation PTP interface signal to the mapping time-delay of described E1 interface signal, inserts the correction territory of described Delay computing request message;
The second Delay computing request response message processing unit is used for transmission lag computation requests response message to described E1 interface and described PTP interface, with described Delay computing request response message respectively solution be mapped to described E1 interface signal and described PTP interface signal.
5. clock synchronization system according to claim 1 and 2 is characterized in that, described primary time server is used for receiving time reference signal, and described time reference signal comprises satellite time signal and cesium-beam atomic clock time signal.
6. clock synchronization system according to claim 1 and 2 is characterized in that, described transmission network is synchronous digital transmission system.
7. clock synchronization system according to claim 1 and 2 is characterized in that, described sub-time server comprises PTP from the clock interface, described sub-time server process IEEE1588V2 agreement.
8. clock synchronization system according to claim 1 and 2 is characterized in that, described ether PTP interface physical interface is 100,000,000/gigabit Ethernet photoelectric port.
9. clock synchronization system according to claim 1 and 2 is characterized in that, the number of described single E1/PTP time channel adapter is between 2 to 32.
10. clock synchronization system according to claim 1 and 2 is characterized in that, the number of described single E1/PTP time channel adapter and described substation time server equates.
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| CN107247405A (en) * | 2017-04-14 | 2017-10-13 | 广州北极瑞光电子科技有限公司 | A kind of satellite navigation time service is kept time the solution in clock system |
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