CN103069718A - Frequency divider circuit, pll circuit provided therewith, and semiconductor integrated circuit - Google Patents
Frequency divider circuit, pll circuit provided therewith, and semiconductor integrated circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
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Abstract
The disclosed frequency divider circuit is provided with: a variable frequency divider (2) which frequency-divides a periodic signal (s5) with two frequency division ratios and outputs a first frequency-divided signal (c1); a counter circuit (3) which outputs a count value (c2) of the number of cycles of the first frequency-divided signal (c1) and which, when reset, restarts the counting operation to count from an initial value; a comparator (4) which outputs as a second frequency-divided signal a pulse signal (s1) that reverses High and Low each time the count value (c2) matches a comparison reference value (a), which supplies said pulse signal (s1) as the frequency division ratio switch signal to the variable frequency divider (2), and which outputs a reset signal (r) to the counter circuit (3) each time the count value (c2) matches the comparison reference value (a); and a control circuit (5) for supplying the comparison reference value (a) to the comparator (4).
Description
Technical field
The present invention relates to a kind of circuit that the input periodic signal is carried out frequency division.
Background technology
At the PLL(Phase Locked Loop that generates the stabilize desirable frequency signal with the benchmark oscillator signal: phase-locked loop) in the circuit, have a kind ofly to be called pulse and to swallow up the technology of (pulse swallow) mode, this technology is in order to realize high-speed response and to increase the frequency dividing ratio variable range.Pulse is swallowed up in the mode, controls the frequency dividing ratio of dual-mode frequency divider (dual modulus prescal er) by swallowing up counter, and generates thus larger frequency dividing ratio.The variable frequency divider that possesses in the dual-mode frequency divider has adopted 1/(N+1) and these 2 kinds of frequency dividing ratios of 1/N.Generally speaking, come in the Integer-N type PLL circuit of control generator at the integral multiple with reference frequency, above-mentioned 2 kinds of frequency dividing ratios of variable frequency divider are fixed, and have reserved in advance how many overtones bands that will obtain reference frequency in the system.
Fig. 3 represents the structure of PLL circuit that counter circuit is swallowed up in this type of pulse of employing in the patent documentation 1.
The PLL circuit of Fig. 3 has possessed voltage-controlled oscillator 101, frequency divider 102, frequency divider 103, comparator 104, phase detectors 105, reference frequency signal source R and reference divider 106.Frequency divider 102 is variable frequency dividers, and it holds frequency dividing ratio 1/(N+1) and frequency dividing ratio 1/N.Frequency divider 103 be by each clock signal subtract calculate elemental motion subtract calculation type frequency divider, or by the add type that the adds frequency divider of elemental motion of each clock signal, it has the fractional frequency signal output as the 1st output.In addition, frequency divider 103 also according to the value n from external setting-up come to this n+1 of 0～n (n=1,2,3 ...) input pulse counts, and have the 2nd output, the 2nd output in order to output with above-mentioned count the corresponding plus and minus calculation of value result midway.Comparator 104 with the output valve of the 2nd output of frequency divider 103, with value A(n from external setting-up A, A=0,1,2 ...) compare, then according to the logical value of numerical value comparative result, the logic control signal that will use when being created on the frequency dividing ratio of selecting frequency divider 102, and this logic control signal exported to frequency divider 102.For the delay that prevents that set point from just occuring after changing, frequency divider 102, frequency divider 103 and phase comparator 105 all are transfused to reset signal, and they carry out initialization action with injunction.
The output signal of voltage-controlled oscillator 101 is input to frequency divider 102.Frequency divider 102 according to through initialization action and fixed frequency dividing ratio 1/(N+1) carry out frequency division action, and the output pulse of 103 pairs of frequency dividers 102 of frequency divider is counted.Frequency divider 103 just resets when having counted n+1, again counts from initial value thus.Comparator 104 will compare with value A from the count value that the 2nd output of frequency divider 103 is exported, if this count value is consistent with value A, then exports the signal that switches to 1/N in order to the frequency dividing ratio with frequency divider 102.
Therefore, frequency divider 103 during n+1 pulse counted in, can receive and count following output pulse from frequency divider 102: in frequency dividing ratio from 1/(N+1) become behind the 1/N divide the output that occurs frequently pulse.
Frequency divider 103 is when having counted n+1, and just the signal that one-period has finished is expressed in 105 outputs from the 1st output to phase detectors.Therefore, the output signal of voltage-controlled oscillator 101 be by the frequency division shown in the following formula recently by frequency division: (N+1) * (A+1)+N * (n-A)=nN+A+1.Phase detectors 105 compare the reference frequency signal of this frequency division input signal and reference frequency signal source R output, and the corresponding control signal of phase difference that then will get with comparing is exported to voltage-controlled oscillator 101.By such closed-loop control, the frequency of oscillation of voltage-controlled oscillator 101 is able to stabilisation.
[prior art document]
Patent documentation 1: Japan's Patent Application Publication communique " Unexamined Patent 7-111452 communique "; April 25 nineteen ninety-five is open.
Summary of the invention
[problem to be solved by this invention]
In the PLL of patent documentation 1 circuit, frequency divider 102, frequency divider 103 and comparator 104 can be considered and consisted of pulse and swallow up counter circuit.And, if set n and A for variable mode, just this pulse is swallowed up counter circuit and be can be used as frequency synthesizer and come work so.
For example establish n=1 at this, A=0 then, so shown in Fig. 4 (a), 103 pairs of 2 pulses of frequency divider count during be divided into: 1 with 1/(N+1) frequency division during during the corresponding counting and during 1 frequency division with 1/N during the corresponding counting.At this moment, whole pulse is swallowed up the frequency dividing ratio X of counter circuit and is: (N+1) * and 1+N * 1=2N+1.Therefore the fractional frequency signal of frequency divider 103 outputs is to be the signal in 1 cycle during 2 countings of frequency divider 103.
In addition, for example establish n=3, then A can be set for 0,1,2 these 3 values.Therefore the fractional frequency signal of frequency divider 103 outputs is to be the signal in 1 cycle during 4 countings of frequency divider 103.Below, the action difference that the A value is brought is described when n=3.
If n=3, A=0, then shown in Fig. 4 (b), 103 pairs of 4 pulses of frequency divider count during be divided into: 1 with 1/(N+1) frequency division during during the corresponding counting and during 3 frequency divisions with 1/N during the corresponding counting.At this moment, whole pulse is swallowed up the frequency dividing ratio X of counter circuit and is: (N+1) * and 1+N * 3=4N+1.
If n=3, A=1, then shown in Fig. 4 (c), 103 pairs of 4 pulses of frequency divider count during be divided into: 2 with 1/(N+1) frequency division during during the corresponding counting and during 2 frequency divisions with 1/N during the corresponding counting.At this moment, whole pulse is swallowed up the frequency dividing ratio X of counter circuit and is: (N+1) * and 2+N * 2=4N+2.
If n=3, A=2, then shown in Fig. 4 (d), 103 pairs of 4 pulses of frequency divider count during be divided into: 3 with 1/(N+1) frequency division during during the corresponding counting and during 1 frequency division with 1/N during the corresponding counting.At this moment, whole pulse is swallowed up the frequency dividing ratio X of counter circuit and is: (N+1) * and 3+N * 1=4N+3.
In counter circuit is swallowed up in the pulse of patent documentation 1, if the n of frequency divider 103 can set in 1～3, the X=2N+1 when then its minimum frequency dividing ratio is n=1, A=0, and the X=4N+3 of its maximum frequency dividing ratio when being n=3, A=2.
If yet to want to set more local frequency with the PLL circuit, above-mentioned variable dividing radio is not enough sometimes.During this situation, the counts (counts of the frequency divider 103 in the example of patent documentation 1) that needs the output signal of increase variable frequency divider, want the increasing circuit scale but the increase counts just means, and then mean the increase of power consumption, therefore unsatisfactory.
The present invention researches and develops in view of above-mentioned existing problem, purpose be to realize a kind of can be in the situation that do not cause increasing circuit scale and the power consumption further frequency dividing circuit of increasing circuit frequency dividing ratio variable range on the whole and PLL circuit and the semiconductor integrated circuit that possesses this frequency dividing circuit.
[in order to the technical scheme of dealing with problems]
For addressing the above problem, frequency dividing circuit of the present invention is characterised in that to possess: variable frequency divider, it can recently carry out frequency division by 2 kinds of frequency divisions, and the periodic signal of input being come by the above-mentioned frequency dividing ratio of appointment carries out frequency division, thereby generates the 1st fractional frequency signal and the 1st fractional frequency signal is exported; Counter circuit, it is counted the period of above-mentioned the 1st fractional frequency signal of above-mentioned variable frequency divider output from initial value, thereby obtains count value and with this count value output, and again counts from initial value after resetting; Comparator, it compares above-mentioned count value and benchmark value, and the pulse signal that when above-mentioned count value is consistent with above-mentioned benchmark value, just carries out the high-low level counter-rotating that will generate, both exported as the 2nd fractional frequency signal that is directed to above-mentioned periodic signal, again as will in above-mentioned variable frequency divider, the switching signal of the above-mentioned frequency dividing ratio of appointment offering above-mentioned variable frequency divider, and also when above-mentioned count value is consistent with above-mentioned benchmark value, make above-mentioned counter circuit reset to above-mentioned counter circuit output reset signal; Control circuit offers above-mentioned comparator with above-mentioned benchmark value.
In foregoing invention, variable frequency divider is by an initial specified wherein side frequency dividing ratio, and the periodic signal that input is come carries out frequency division.The 1st fractional frequency signal of variable frequency divider output is counted by counter circuit.Counter circuit is exported to comparator with count value successively, until count value is when reaching identical with the benchmark value.In comparator, the count value of coming when input and benchmark are worth when inconsistent, then pulse signal are remained " height " level or " low " level; And when the input count value of coming is consistent with the benchmark value, inversion pulse signal between " height " level and " low " level then.This pulse signal inputs to variable frequency divider as switching signal, then variable frequency divider frequency dividing ratio is switched to that next will appointment, the opposing party's frequency dividing ratio wherein.In addition, comparator is also simultaneously to counter circuit output reset signal.
Counter circuit through resetting begins counting again to the 1st fractional frequency signal of variable frequency divider output from initial value, and exports successively count value to comparator, until count value is when reaching identical with the benchmark value.In comparator, the count value of coming when input and benchmark are worth when inconsistent, then pulse signal are remained " height " level or " low " level; And when the input count value of coming is consistent with the benchmark value, inversion pulse signal between " height " level and " low " level then.This pulse signal inputs to variable frequency divider as switching signal, so variable frequency divider switches to again an above-mentioned wherein side frequency dividing ratio with frequency dividing ratio.In addition, comparator is also simultaneously to counter circuit output reset signal.
Like this, pulse signal becomes the 2nd fractional frequency signal that has the cycle that is made of sum during following two frequency divisions, is equivalent to respectively during this two frequency division during following two countings: count down in the counter circuit during the counting till the benchmark value, corresponding with a side's wherein frequency dividing ratio; Count down in the counter circuit during the counting till the benchmark value, corresponding with the opposing party's wherein frequency dividing ratio.At this moment, with regard to be directed to the frequency dividing circuit output signal be periodic signal, namely with regard to the 2nd fractional frequency signal, the maximum frequency dividing ratio of the 2nd fractional frequency signal is very large to the frequency dividing circuit input signal, and minimum frequency dividing ratio is with equaling minimum frequency dividing ratio of the prior art.
According to such scheme, effect of the present invention be to realize a kind of can be in the situation that do not cause the further frequency dividing circuit of increasing circuit frequency dividing ratio variable range on the whole of increasing circuit scale and power consumption.
[invention effect]
As mentioned above, frequency dividing circuit of the present invention possesses: variable frequency divider, it can recently carry out frequency division by 2 kinds of frequency divisions, and the periodic signal of input being come by the above-mentioned frequency dividing ratio of appointment carries out frequency division, thereby generates the 1st fractional frequency signal and the 1st fractional frequency signal is exported; Counter circuit, it is counted the period of above-mentioned the 1st fractional frequency signal of above-mentioned variable frequency divider output from initial value, thereby obtains count value and with this count value output, and again counts from initial value after resetting; Comparator, it compares above-mentioned count value and benchmark value, and the pulse signal that when above-mentioned count value is consistent with above-mentioned benchmark value, just carries out the high-low level counter-rotating that will generate, both exported as the 2nd fractional frequency signal that is directed to above-mentioned periodic signal, again as will in above-mentioned variable frequency divider, the switching signal of the above-mentioned frequency dividing ratio of appointment offering above-mentioned variable frequency divider, and also when above-mentioned count value is consistent with above-mentioned benchmark value, make above-mentioned counter circuit reset to above-mentioned counter circuit output reset signal; Control circuit offers above-mentioned comparator with above-mentioned benchmark value.
According to such scheme, effect of the present invention be to realize a kind of can be in the situation that do not cause the further frequency dividing circuit of increasing circuit frequency dividing ratio variable range on the whole of increasing circuit scale and power consumption.
Description of drawings
Fig. 1 represents embodiments of the present invention, is the circuit block diagram of expressing the PLL circuit structure.
Fig. 2 represents embodiments of the present invention, (a) is the sequential chart of the action of PLL circuit shown in Figure 1 to (d).
Fig. 3 represents prior art, is the circuit block diagram of expressing existing PLL circuit structure
(a) of Fig. 4 is the sequential chart of the action of PLL circuit shown in Figure 3 to (d).
Fig. 5 is the circuit structure diagram that is used in the variable frequency divider in the PLL circuit shown in Figure 1.
Fig. 6 is the circuit structure diagram that is used in the counter circuit in the PLL circuit shown in Figure 1.
Fig. 7 is the circuit structure diagram that is used in the comparator in the PLL circuit shown in Figure 1.
[description of reference numerals]
1 oscillating circuit
2 variable frequency dividers
3 counter circuits
4 comparators
5 control circuits
6 phase comparators
7 reference signal oscillators
8 charge pump circuits
9 loop filters
10 memories
20 PLL circuit
41,42 AND circuit
43 T triggers
S5 oscillator signal (periodic signal)
C1 fractional frequency signal (the 1st fractional frequency signal)
The c2 count value
A benchmark value
D frequency dividing ratio set information (information that relates to the benchmark value)
S1 pulse signal (the 2nd fractional frequency signal, switching signal)
The r reset signal
Embodiment
Following according to Fig. 1 and Fig. 2, embodiments of the present invention are described.
(structure of the PLL circuit of present embodiment)
Fig. 1 represents the structure of the PLL circuit 20 of present embodiment.
PLL circuit 20 is that the PLL circuit of mode is swallowed up in pulse, and it possesses oscillating circuit 1, variable frequency divider 2, counter circuit 3, comparator 4, control circuit 5, phase detectors 6, reference signal oscillator 7, charge pump circuit 8, loop filter 9 and memory 10.Variable frequency divider 2, counter circuit 3, comparator 4, control circuit 5 and memory 10 have consisted of pulse and have swallowed up counter circuit (frequency dividing circuit).
Fig. 5 illustration the structure during N=3 in the variable frequency divider 2, the structure when namely variable frequency divider 2 is as 3/4 frequency divider.Variable frequency divider 2 shown in Figure 5 comprises trigger 21 and 22 these 2 d type flip flops, 1 AND circuit 23,1 switch 24.Oscillator signal s5 is input to clock signal input terminal of trigger 21 and 22.The output of trigger 21 is connected to a wherein side the input of two inputs of AND circuit 23.The output signal of AND circuit 23 is input to the D input terminal of trigger 22.The output signal of trigger 22 also is input to the D input terminal (also can with the output signal of the trigger 21 fractional frequency signal c1 as variable frequency divider 2 outputs) of trigger 21 in the fractional frequency signal c1 as variable frequency divider 2 output.AND circuit 23 the opposing party's input, being situated between is connected to the output of trigger 22 or is connected to the GND current potential by switch 24.Switch 24 carries out change action by the pulse signal s1 from aftermentioned comparator 4.In the variable frequency divider 2 with circuit structure shown in Figure 5, when switch 24 is communicated with left side (GND current potential), then carry out the action of 4 frequency divisions; And when switch 24 is communicated with right side (output of trigger 22), then carry out the action of 3 frequency divisions.That is, in variable frequency divider 2, by coming diverter switch 24 with pulse signal s1, just can switch the action of 3 frequency divisions and the action of 4 frequency divisions.
Although Fig. 5 illustration the scheme (during N=3) of variable frequency divider 2 during as 3/4 frequency divider, the present invention is not limited thereto, and also can adopt the variable frequency divider beyond the N=3.Even if the variable frequency divider 2 beyond the N=3, its structure also is known in this area.
In the counter circuit 3 with circuit structure shown in Figure 6, the output signal of d type flip flop 31 at different levels has consisted of the position signal of expressing count value c2.That is to say, the output of the 1st grade d type flip flop 31 produce count value c2, count the 1st signal from low level, the output of the 2nd grade d type flip flop 31 produce count value c2, count the 2nd signal, the d type flip flop 31 of final level from low level
Output produce signal count value c2, count (n+1) position from low level.
In addition, each d type flip flop 31 is transfused to respectively the reset signal r from aftermentioned comparator 4.Thus, in counter circuit 3, when reset signal r was " high (High) ", then count value c2 resetted back 0.
It is as shown in Figure 6 asynchronous type binary counter that counter circuit 3 of the present invention is not limited to, and also can adopt other known counters.For example, counter circuit 3 can be synchronous mode, also can be the counter of Gray's (Gray) counter or other structures.
The count value c2 that comparator 4 is come counter circuit 3 inputs, the benchmark value a as setting signal that comes with control circuit 5 input compares, and with pulse signal s1 as whole pulse swallow up counter circuit fractional frequency signal (the 2nd fractional frequency signal) and export to phase comparator 6.This pulse signal s1 reverses between " high (High) " and " low (Low) " when count value c2 is consistent with benchmark value a.That is to say, pulse signal s1 is that the fractional frequency signal of counter circuit is swallowed up in whole pulse, is again the switching signal of the frequency dividing ratio of variable frequency divider 2.About the pulse signal s1 as switching signal, its each counter-rotating action of carrying out between " height " and " low " is equivalent to the switching indication of frequency dividing ratio.
Fig. 7 represents a routine concrete structure of comparator 4.Comparator 4 shown in Figure 7 is made of a plurality of the 1st grade of AND circuit 41 and the 2nd grade of AND circuit 42, T trigger 43.The number of the 1st grade of AND circuit 41 equals the figure place (being (n+1) position at this) of the count value c2 of counter circuit 3 outputs.Each AND circuit 41 has 2 inputs, is transfused among the count value c2 signal of certain on one of them input, and is transfused to fiducial value a as a comparison on another input and certain place value of setting.In each AND circuit 41, the position signal of the count value c2 that inputs, the place value that sets with fiducial value a as a comparison are mutual corresponding.The output signal of all the 1st grade of AND circuit 41 all inputs to the 2nd grade of AND circuit 42.Thus, when the output signal of all the 1st grade of AND circuit 41 was " height ", namely when count value c2 was consistent with benchmark value a, the output signal of AND circuit 42 just was " height "; And when count value c2 and benchmark value a were inconsistent, the output signal of AND circuit 42 just was " low ".
In addition, the output signal of the 2nd grade of AND circuit 42 is imported into the T trigger 43 that is arranged on rear class.The output signal of T trigger 43 is exported as pulse signal s1.That is, when count value c2 was consistent with benchmark value a, the pulse signal s1 of comparator 4 outputs just switched between " height " and " low ".In addition, comparator 4 is also to counter circuit 3 output reset signals.This reset signal is so long as just be that the signal of " height " gets final product when count value c2 is consistent with benchmark value a, therefore the output signal of AND circuit 42 exported as reset signal r to get final product.
Frequency dividing ratio set information (information that the relates to the benchmark value) d of storage in control circuit 5 read memories 10, and will set according to frequency dividing ratio set information d, swallow up the corresponding benchmark value a of the frequency dividing ratio of counter circuit with whole pulse, input to comparator 4.Benchmark value a is variable, and it is individual how much quantity of the frequency dividing ratio set information d for preparing has, and it is individual how many benchmark value a just has.If store a plurality of frequency dividing ratio set information ds corresponding with benchmark value a in the memory 10, then PLL circuit 20 can come work as frequency synthesizer.
Frequency dividing ratio set information d for example is that the mode with question blank (look-up table) is stored in the memory 10, has recorded and narrated control circuit 5 wishs in this question blank and has set to pulse and swallow up the frequency dividing ratio of counter circuit and the corresponding relation between the benchmark value a.When control circuit 5 references to storage 10 read the frequency dividing ratio of institute's wish setting, this processing of just carrying out from question blank, reading corresponding benchmark value a.Perhaps, for example can in memory 10, store the sequence of reserving in advance, be used for switching in time benchmark value a, with as frequency dividing ratio set information d.When control circuit 5 references to storage 10 read, just carry out reading successively from memory 10 according to this sequence this processing of a plurality of benchmark value a.
In addition, also can replace memory 10 with initialization circuit (not shown), or append this initialization circuit possessing the basis that memory 10 is arranged.This initialization circuit is accepted from PLL circuit 20 outsides, is namely swallowed up the frequency dividing ratio set information d of counter circuit outside from pulse as interface.This scheme is applicable to following two kinds of situations: (1) sets frequency dividing ratio by other control circuits in the equipment that is mounted with PLL circuit 20; (2) user by equipment carries out the input indication relevant with frequency dividing ratio etc.When adopting this scheme, control circuit 5 provides benchmark value a according to being input to information its initialization circuit, relevant with frequency dividing ratio set information d to comparator 4.
Phase comparator 6 detects the phase difference between the reference frequency signal s0 of the pulse signal s1 that comes from comparator 4 inputs and reference signal oscillator 7 generations, and testing result is exported to charge pump circuit 8 as phase signal s2.At this, reference signal oscillator 7 is made of crystal oscillator etc.
The phase signal s2 that charge pump circuit 8 is come phase comparator 6 input converts voltage signal or current signal to, and will change and must signal export to loop filter 9 as signal s3.
(the present invention as semiconductor integrated circuit time scheme)
In having the PLL circuit 20 of said structure, oscillating circuit 1, variable frequency divider 2, counter circuit 3, comparator 4 and control circuit 5 also can be formed on and consist of 1 semiconductor integrated circuit on the same semiconductor substrate.In addition, phase comparator 6 and charge pump circuit 8 can be formed on other the same semiconductor substrate and consist of 1 semiconductor integrated circuit.In addition, loop filter 9 can be formed on and consist of 1 semiconductor integrated circuit on the another semiconductor substrate.In addition, reference signal oscillator 7, phase comparator 6, charge pump circuit 8, loop filter 9, memory 10 and above-mentioned initialization circuit can also be formed on oscillating circuit 1, variable frequency divider 2, counter circuit 3, comparator 4 and control circuit 5 whole or in part and consist of 1 semiconductor integrated circuit on the same semiconductor substrate.
If integrated circuit more on same semiconductor substrate is just can correspondingly realize the miniaturization of circuit, the reduction of manufacturing cost, the easy of operation and the raising of signal quality.
(action of PLL circuit)
Below, the action of PLL circuit 20 is described according to Fig. 2, especially be conceived to pulse and swallow up the action of counter circuit and describe.
In PLL circuit 20, counter circuit 3 can count down to till the 4th.In this scheme, if design value can change between 0 to 3, just benchmark value a can be set for 0,1,2,3 these 4 values.The power supply that is mounted with for example communicator of PLL circuit 20 is switched on, control circuit 5 is just according to the frequency setting situation of reserving the high-frequency circuit that will use in this device, from memory 10, read frequency dividing ratio set information d, and benchmark value a is offered comparator 4.And about the action after this, be illustrated hereinafter.In addition, the free-running frequence of imagination oscillating circuit 1 is controlled in locking states.
At first, imagination control circuit 5 offers comparator 4(with reference to Fig. 2 (a) with benchmark value a=0).
When installation's power source was connected, counter circuit 3 carried out initialization, begins to count from " 0 " thus.Variable frequency divider 2 is at first according to 1/(N+1) frequency dividing ratio, the oscillator signal s5 of oscillating circuit 1 output is carried out frequency division.The fractional frequency signal c1 of 3 pairs of variable frequency dividers of counter circuit, 2 outputs counts, and " 0 " is exported to comparator 4 as count value c2.Because it is consistent with benchmark value a to input to the count value c2 of comparator 4, so comparator 4 is such shown in Fig. 2 (a), makes pulse signal s1 be inverted to " height " level from " low " level.Should " height " level input to variable frequency divider 2 as switching signal, so variable frequency divider 2 switches to 1/N with frequency dividing ratio.In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
The fractional frequency signal c1 of 3 pairs of variable frequency dividers of the counter circuit through resetting, 2 outputs begins counting from " 0 " again, and " 0 " is exported to comparator 4 as count value c2.Because it is consistent with benchmark value a to input to the count value c2 of comparator 4, so comparator 4 makes pulse signal s1 be inverted to " low " level from " height " level.Should input to variable frequency divider 2 as switching signal by " low " level, so variable frequency divider 2 switches back again 1/(N+1 with frequency dividing ratio).In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
Like this, pulse signal s1 is the signal with the cycle that is made of sum during following two frequency divisions, during this two frequency division is: occupy in the counter circuit 3 during 1 counting, with frequency dividing ratio 1/(N+1) during the corresponding frequency division; Occupy in the counter circuit 3 during the frequency division during 1 counting, corresponding with frequency dividing ratio 1/N.In this scheme, swallow up the pulse signal s1 of output signal of counter circuit as pulse, that to swallow up the input signal of counter circuit with pulse be mutually corresponding signal of oscillator signal s5, and the frequency dividing ratio Y(s1 of this pulse signal s1 representative) be (N+1) * 1+N * 1=2N+1.This frequency dividing ratio Y(s1) be the minimum frequency dividing ratio of PLL circuit 20, it equals the frequency dividing ratio X=2N+1 of Fig. 3 and existing PLL circuit shown in Figure 4.
After this pulse signal s1 inputed to phase comparator 6, phase comparator 6 just detected the phase difference between the reference frequency signal s0 that this pulse signal s1 and reference signal oscillator 7 provide.The phase signal s2 of phase comparator 6 outputs is input to charge pump circuit 8, is converted into thus voltage signal or current signal.The signal s3 of charge pump circuit 8 outputs is input to loop filter 9, extracts flip-flop by loop filter 9 from signal s3.This flip-flop is input to oscillating circuit 1 as voltage signal.This voltage signal is used for the frequency of oscillation of control oscillating circuit 1, to eliminate the phase difference between pulse signal s1 and reference frequency signal s0.Phase comparator 6, charge pump circuit 8, loop filter 9 and oscillating circuit 1 action separately also are same in the aftermentioned example.
Below, imagination control circuit 5 offers comparator 4(with reference to Fig. 2 (b) with benchmark value a=1).
When installation's power source was connected, counter circuit 3 carried out initialization, begins to count from " 0 " thus.Variable frequency divider 2 is at first according to 1/(N+1) frequency dividing ratio, the oscillator signal s5 of oscillating circuit 1 output is carried out frequency division.The fractional frequency signal c1 of 3 pairs of variable frequency dividers of counter circuit, 2 outputs counts, and " 0 " is exported to comparator 4 as initial count value c2.Because it is inconsistent to input to count value c2 and the benchmark value a of comparator 4, so comparator 4 is maintained " low " level with pulse signal s1.And when counter circuit 3 is exported to comparator 4 with " 1 " as next count value c2, because it is consistent with benchmark value a that input to this count value c2 of comparator 4 this moment, so comparator 4 makes pulse signal s1 be inverted to " height " level from " low " level.Should " height " level input to variable frequency divider 2 as switching signal, so variable frequency divider 2 switches to 1/N with frequency dividing ratio.In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
The fractional frequency signal c1 of 3 pairs of variable frequency dividers of the counter circuit through resetting, 2 outputs again begins counting from " 0 ", and successively comparator 4 is exported to as count value c2 in " 0 ", " 1 ".When the count value c2 that inputs to comparator 4 was " 1 ", because this moment, count value c2 was consistent with benchmark value a, so comparator 4 made pulse signal s1 be inverted to " low " level from " height " level.Should input to variable frequency divider 2 as switching signal by " low " level, so variable frequency divider 2 switches back again 1/(N+1 with frequency dividing ratio).In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
Like this, pulse signal s1 is the signal with the cycle that is made of sum during following two frequency divisions, during this two frequency division is: occupy in the counter circuit 3 during 2 countings, with frequency dividing ratio 1/(N+1) during the corresponding frequency division; Occupy in the counter circuit 3 during the frequency division during 2 countings, corresponding with frequency dividing ratio 1/N.In this scheme, swallow up the pulse signal s1 of output signal of counter circuit as pulse, that to swallow up the input signal of counter circuit with pulse be mutually corresponding signal of oscillator signal s5, and the frequency dividing ratio Y(s1 of this pulse signal s1 representative) be (N+1) * 2+N * 2=4N+2.
Below, imagination control circuit 5 offers comparator 4(with reference to Fig. 2 (c) with benchmark value a=2).
When installation's power source was connected, counter circuit 3 carried out initialization, begins to count from " 0 " thus.Variable frequency divider 2 is at first according to 1/(N+1) frequency dividing ratio, the oscillator signal s5 of oscillating circuit 1 output is carried out frequency division.The fractional frequency signal c1 of 3 pairs of variable frequency dividers of counter circuit, 2 outputs counts, and successively comparator 4 is exported to as count value c2 in " 0 ", " 1 ", " 2 ".When the count value c2 that inputs to comparator 4 was " 0 " or " 1 ", count value c2 and benchmark value a were inconsistent owing to this moment, so comparator 4 is maintained " low " level with pulse signal s1.And when the count value c2 that inputs to comparator 4 was " 2 ", because count value c2 this moment is consistent with benchmark value a, so comparator 4 made pulse signal s1 be inverted to " height " level from " low " level.Should " height " level input to variable frequency divider 2 as switching signal, so variable frequency divider 2 switches to 1/N with frequency dividing ratio.In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
The fractional frequency signal c1 of 3 pairs of variable frequency dividers of the counter circuit through resetting, 2 outputs again begins counting from " 0 ", and successively comparator 4 is exported to as count value c2 in " 0 ", " 1 ", " 2 ".When the count value c2 that inputs to comparator 4 was " 2 ", because this moment, count value c2 was consistent with benchmark value a, so comparator 4 made pulse signal s1 be inverted to " low " level from " height " level.Should input to variable frequency divider 2 as switching signal by " low " level, so variable frequency divider 2 switches back again 1/(N+1 with frequency dividing ratio).In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
Like this, pulse signal s1 is the signal with the cycle that is made of sum during following two frequency divisions, during this two frequency division is: occupy in the counter circuit 3 during 3 countings, with frequency dividing ratio 1/(N+1) during the corresponding frequency division; Occupy in the counter circuit 3 during the frequency division during 3 countings, corresponding with frequency dividing ratio 1/N.In this scheme, swallow up the pulse signal s1 of output signal of counter circuit as pulse, that to swallow up the input signal of counter circuit with pulse be mutually corresponding signal of oscillator signal s5, and the frequency dividing ratio Y(s1 of this pulse signal s1 representative) be (N+1) * 3+N * 3=6N+3.
Below, imagination control circuit 5 offers comparator 4(with reference to Fig. 2 (d) with benchmark value a=3).
When installation's power source was connected, counter circuit 3 carried out initialization, begins to count from " 0 " thus.Variable frequency divider 2 is at first according to 1/(N+1) frequency dividing ratio, the oscillator signal s5 of oscillating circuit 1 output is carried out frequency division.The fractional frequency signal c1 of 3 pairs of variable frequency dividers of counter circuit, 2 outputs counts, and successively comparator 4 is exported to as count value c2 in " 0 ", " 1 ", " 2 ", " 3 ".When the count value c2 that inputs to comparator 4 was " 0 " or " 1 " or " 2 ", count value c2 and benchmark value a were inconsistent owing to this moment, so comparator 4 is maintained " low " level with pulse signal s1.And when the count value c2 that inputs to comparator 4 was " 3 ", because count value c2 this moment is consistent with benchmark value a, so comparator 4 made pulse signal s1 be inverted to " height " level from " low " level.Should " height " level input to variable frequency divider 2 as switching signal, so variable frequency divider 2 switches to 1/N with frequency dividing ratio.In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
The fractional frequency signal c1 of 3 pairs of variable frequency dividers of the counter circuit through resetting, 2 outputs again begins counting from " 0 ", and successively comparator 4 is exported to as count value c2 in " 0 ", " 1 ", " 2 ", " 3 ".When the count value c2 that inputs to comparator 4 was " 3 ", because this moment, count value c2 was consistent with benchmark value a, so comparator 4 made pulse signal s1 be inverted to " low " level from " height " level.Should input to variable frequency divider 2 as switching signal by " low " level, so variable frequency divider 2 switches back again 1/(N+1 with frequency dividing ratio).In addition, comparator 4 is simultaneously also to counter circuit 3 output reset signal r.
Like this, pulse signal s1 is the signal with the cycle that is made of sum during following two frequency divisions, during this two frequency division is: occupy in the counter circuit 3 during 4 countings, with frequency dividing ratio 1/(N+1) during the corresponding frequency division; Occupy in the counter circuit 3 during the frequency division during 4 countings, corresponding with frequency dividing ratio 1/N.In this scheme, swallow up the pulse signal s1 of output signal of counter circuit as pulse, that to swallow up the input signal of counter circuit with pulse be mutually corresponding signal of oscillator signal s5, and the frequency dividing ratio Y(s1 of this pulse signal s1 representative) be (N+1) * 4+N * 4=8N+4.
In benchmark value a is above-mentioned each example of 0～3, the Y(s1 during a=3)=8N+4, be maximum frequency dividing ratio.This frequency dividing ratio is greater than the maximum frequency dividing ratio X=4N+3 that swallows up counter that can carry out 4 countings in Fig. 3 and the existing PLL circuit shown in Figure 4.In the present embodiment, respectively with 1/(N+1) during the corresponding frequency division and with the corresponding frequency division of 1/N during in, count down in the counter circuit 3 till set and the limit count value that benchmark value a equates, and sum has determined the Cycle Length of final fractional frequency signal during these two frequency divisions, so present embodiment can be set very large frequency dividing ratio.
If be natural number with k(k) express pulse and swallow up the number of times that counter can count, then general obtainable maximum frequency dividing ratio is X=(N+1 in Fig. 3 and existing PLL circuit shown in Figure 4) * (k-1)+N * 1=kN+k-1.And in the present embodiment, obtainable maximum frequency dividing ratio is Y(s1)=(N+1) * k+N * k=2kN+k.If adopt existing PLL circuit, pulse is swallowed up whole cycle of final frequency division output signal of counter circuit and will be constrained to like that as shown in Figures 3 and 4 so: the number of times k that the counter that swallows up can be counted is just counted up to during one time required.And this phenomenon is not limited in and occurs in Fig. 3 and the scheme shown in Figure 4.Therefore in the maximum frequency dividing ratio of prior art, the multiplier of " N " is k.And with regard to the maximum frequency dividing ratio of present embodiment, pulse is swallowed up and can be comprised in whole cycle of final frequency division output signal of counter circuit: pulse is swallowed up number of times k that counter can count and is just counted up to during during one time required 2 times.Therefore in maximum frequency dividing ratio of the present invention, the multiplier of " N " is 2k, so can obtain very large maximum frequency dividing ratio.
On the other hand, the minimum frequency dividing ratio in the present embodiment and existing PLL circuit are same, be according to during 2 countings that swallow up in the counter, minimum period of final frequency division output signal of deciding pulse to swallow up counter circuit.So can similarly realize less frequency dividing ratio with prior art.
As mentioned above, by present embodiment, can realize a kind of can be in the situation that do not cause increasing circuit scale and the power consumption further frequency dividing circuit of increasing circuit frequency dividing ratio variable range on the whole and PLL circuit and the semiconductor integrated circuit that possesses this frequency dividing circuit.
In addition, although the action of Integer-N type PLL circuit that in above example, comes control generator take the integral multiple by reference frequency as example, the present invention will be described.But the present invention also is applicable to come by minute several times of reference frequency the Fractional-N type PLL circuit of control generator.
The present invention is not limited to the respective embodiments described above, in conjunction with routine techniques changes above-mentioned execution mode technical scheme and the combination the respective embodiments described above and technical scheme be also contained in the embodiments of the present invention scope.
[utilizing on the industry possibility]
The present invention can be applicable to adopt communication equipment, high-frequency circuit of the stabilisation frequency signals such as local oscillation signal etc. preferably.
Claims (6)
1. frequency dividing circuit is characterized in that possessing:
Variable frequency divider, it can recently carry out frequency division by 2 kinds of frequency divisions, and the periodic signal of input being come by the described frequency dividing ratio of appointment carries out frequency division, thereby generates the 1st fractional frequency signal and the 1st fractional frequency signal is exported;
Counter circuit, it is counted the period of described the 1st fractional frequency signal of described variable frequency divider output from initial value, thereby obtains count value and with this count value output, and again counts from initial value after resetting;
Comparator, it compares described count value and benchmark value, and the pulse signal that when described count value is consistent with described benchmark value, just carries out the high-low level counter-rotating that will generate, both exported as the 2nd fractional frequency signal that is directed to described periodic signal, again as will in described variable frequency divider, the switching signal of the described frequency dividing ratio of appointment offering described variable frequency divider, and also when described count value is consistent with described benchmark value, make described counter circuit reset to described counter circuit output reset signal;
Control circuit offers described comparator with described benchmark value.
2. frequency dividing circuit according to claim 1 is characterized in that:
Possess memory, store the information that relates to described benchmark value in this memory;
Described control circuit is read the information that relates to described benchmark value from described memory, thereby described benchmark value is offered described comparator.
3. frequency dividing circuit according to claim 1 and 2 is characterized in that:
Possess initialization circuit, this initialization circuit is accepted from the information that relates to described benchmark value of outside input;
Described control circuit offers described comparator according to the information that is input to described benchmark value of relating to of described initialization circuit with described benchmark value.
4. PLL circuit is characterized in that possessing:
Each described frequency dividing circuit in the claims 1 to 3; And
Oscillating circuit, it can change frequency of oscillation, and output is as the oscillator signal of described periodic signal;
Reference signal oscillator, it produces reference frequency signal;
Phase comparator, it detects the phase difference between described the 2nd fractional frequency signal and the described reference frequency signal;
Charge pump circuit, it converts the detected described phase difference of described phase comparator to voltage signal or current signal;
Loop filter, filtering is carried out in its output to described charge pump circuit, and the signal of output in order to the described frequency of oscillation of described oscillating circuit is controlled.
5. semiconductor integrated circuit is characterized in that:
Possesses each described frequency dividing circuit in oscillating circuit and the claims 1 to 3;
Described oscillating circuit can change frequency of oscillation, and output is as the oscillator signal of described periodic signal;
Described variable frequency divider, described counter circuit, described comparator, described control circuit and described oscillating circuit are formed on the same semiconductor substrate.
6. semiconductor integrated circuit according to claim 5 is characterized in that:
On the semiconductor substrate that is formed with described variable frequency divider, described counter circuit, described comparator, described control circuit and described oscillating circuit, also be formed with:
Detect the phase difference between described the 2nd fractional frequency signal and the reference frequency signal phase comparator and
The detected described phase difference of described phase comparator is converted to the charge pump circuit of voltage signal or current signal.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-207220 | 2010-09-15 | ||
| JP2010207220 | 2010-09-15 | ||
| JP2011150344A JP5184680B2 (en) | 2010-09-15 | 2011-07-06 | Frequency divider circuit, PLL circuit including the same, and semiconductor integrated circuit |
| JP2011-150344 | 2011-07-06 | ||
| PCT/JP2011/069029 WO2012035941A1 (en) | 2010-09-15 | 2011-08-24 | Frequency divider circuit, pll circuit provided therewith, and semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
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| CN103069718A true CN103069718A (en) | 2013-04-24 |
| CN103069718B CN103069718B (en) | 2015-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201180039918.1A Expired - Fee Related CN103069718B (en) | 2010-09-15 | 2011-08-24 | Frequency divider circuit, pll circuit provided therewith, and semiconductor integrated circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5184680B2 (en) |
| CN (1) | CN103069718B (en) |
| TW (1) | TWI458262B (en) |
| WO (1) | WO2012035941A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106168751A (en) * | 2015-05-18 | 2016-11-30 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN107306134A (en) * | 2016-04-25 | 2017-10-31 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN109167597A (en) * | 2018-09-10 | 2019-01-08 | 佛山科学技术学院 | A kind of frequency dividing circuit, frequency divider and electronic equipment |
| CN111092617A (en) * | 2018-10-23 | 2020-05-01 | 台湾积体电路制造股份有限公司 | Frequency divider circuit |
| CN111970001A (en) * | 2019-05-20 | 2020-11-20 | 意法半导体(格勒诺布尔2)公司 | Method for supply voltage regulation and corresponding device |
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| CN103684423A (en) * | 2012-09-25 | 2014-03-26 | 上海华虹集成电路有限责任公司 | Variable synchronous clock frequency division circuit |
| AU2015399336B2 (en) * | 2015-06-16 | 2018-12-06 | Telefonaktiebolaget Lm Ericsson (Publ) | Frequency divider, phase-locked loop, transceiver, radio station and method of frequency dividing |
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- 2011-08-24 WO PCT/JP2011/069029 patent/WO2012035941A1/en active Application Filing
- 2011-08-24 CN CN201180039918.1A patent/CN103069718B/en not_active Expired - Fee Related
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| JPH07111452A (en) * | 1993-03-31 | 1995-04-25 | Kiyoshi Kase | Phase locked loop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106168751A (en) * | 2015-05-18 | 2016-11-30 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN106168751B (en) * | 2015-05-18 | 2019-11-26 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN107306134A (en) * | 2016-04-25 | 2017-10-31 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN109167597A (en) * | 2018-09-10 | 2019-01-08 | 佛山科学技术学院 | A kind of frequency dividing circuit, frequency divider and electronic equipment |
| CN109167597B (en) * | 2018-09-10 | 2023-09-01 | 佛山科学技术学院 | Frequency dividing circuit, frequency dividing device and electronic equipment |
| CN111092617A (en) * | 2018-10-23 | 2020-05-01 | 台湾积体电路制造股份有限公司 | Frequency divider circuit |
| CN111092617B (en) * | 2018-10-23 | 2024-05-14 | 台湾积体电路制造股份有限公司 | Frequency divider circuit, method for frequency divider circuit and compensation circuit |
| CN111970001A (en) * | 2019-05-20 | 2020-11-20 | 意法半导体(格勒诺布尔2)公司 | Method for supply voltage regulation and corresponding device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5184680B2 (en) | 2013-04-17 |
| TWI458262B (en) | 2014-10-21 |
| JP2012085265A (en) | 2012-04-26 |
| CN103069718B (en) | 2015-05-20 |
| WO2012035941A1 (en) | 2012-03-22 |
| TW201223154A (en) | 2012-06-01 |
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