CN103066006B - Shallow trench isolation structure, manufacturing method thereof and non-volatile random access memory (RAM) manufacturing method - Google Patents
Shallow trench isolation structure, manufacturing method thereof and non-volatile random access memory (RAM) manufacturing method Download PDFInfo
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Abstract
The invention relates to a shallow trench isolation structure, a manufacturing method thereof and a non-volatile random access memory (RAM) manufacturing method which can be used for manufacturing of a non-volatile RAM. The methods comprise the following steps: preparing a silicon substrate; forming a mat oxide layer on the silicon substrate; forming a silicon nitride pattern on the mat oxide layer; etching the silicon substrate and the silicon nitride pattern to enable a height difference to be formed between the silicon substrate which is covered by the silicon nitride pattern and the silicon substrate which is not covered by the silicon nitride pattern; and then, a light resistance pattern is formed on the silicon substrate and the structure of the silicon substrate; and selectively etching on the silicon substrate and the structure of the silicon substrate to form a plurality of trenches. After the trenches are formed, the light resistance pattern is removed by etching; the oxide layer is formed on the silicon substrate and the structure of the silicon substrate; part of the oxide layer is removed by chemical mechanical polishing to expose the silicon nitride pattern; and the silicon nitride pattern is removed by etching to obtain the shallow trench isolation structure.
Description
Technical field
The present invention relates to the manufacture method of shallow slot isolation structure, the manufacture method of the shallow slot isolation structure particularly relating to a kind of non-voltile memory and the non-voltile memory with this shallow slot isolation structure.
Background technology
When the size of semiconductor subassembly is constantly advanced towards the direction of microminiaturization, in order to ensure assembly non-interference and can normal operation each other, inter-module need be isolated.Territory, the isolation many exploiting fields silica (LOCOS of early stage inter-module, Local Oxidation of Silicon) processing procedure, but this processing procedure easily produces so-called beak (Bird ' s Beak) phenomenon, and the area of isolation of inter-module can be made excessive, be unfavorable for the micro of processing procedure, therefore shallow trench isolation (STI, Shallow Trench Isolation) processing procedure in response to and give birth to.
Fig. 1 a to Fig. 1 g is the manufacturing process schematic diagram of the shallow slot isolation structure of traditional non-voltile memory.As shown in the figure, tradition shallow trench isolation processing procedure comprises the following steps: on a silicon substrate 100, form a pad oxide 110(pad oxide layer) (refer to Fig. 1 a), in order to avoid adhering to hypodynamic problem between contingent silicon nitride and silicon substrate 100 in successive process; Then on described pad oxide 110, form a silicon nitride pattern 120(refer to Fig. 1 b); The silicon substrate 100 being coated with described silicon nitride pattern 120 is etched, with etch not the silicon substrate 100 that covers by silicon nitride pattern 120, and then form multiple irrigation canals and ditches 130(and refer to Fig. 1 c); After forming described multiple irrigation canals and ditches 130, utilize high density plasma enhanced chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition) formed an oxide layer 140 in described silicon substrate 100 and on structure on (referring to Fig. 1 d); Then cmp mode is utilized to grind described oxide layer 140, to expose described silicon nitride pattern 120(please refer to the drawing 1e); And utilize etching mode to remove described silicon nitride pattern 120, to form existing shallow slot isolation structure (please refer to the drawing 1f and Fig. 1 g).Please note, when removing silicon nitride pattern 120, pad oxide 110 below silicon nitride pattern 120 can as an etch stop layer, and after completing and removing silicon nitride pattern 120, originally possibility residual fraction pad oxide 110 below silicon nitride pattern 120, for asking the clear display of icon, have and usually know that the knowledgeable is under the understanding of this prior art not affecting the art, Fig. 1 f and Fig. 1 g does not draw the pad oxide 110 that may remain.Separately please note, Fig. 1 g contains top view and the profile of Fig. 1 f, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S)), and correspondence has the profile of same code.
After completing the manufacture of above-mentioned shallow slot isolation structure, still need and perform subsequent step to complete the manufacture of non-volatile memory components.Please refer to the drawing 2a to Fig. 2 d, described subsequent step comprises: form a gate pole oxidation layer (not shown); With chemical vapor deposition polysilicon in and by its one patterned, to form a suspension gate district 200 along bit line direction, described suspension gate district 200 is in along on source electrode line (Source Line) direction, only cover beneath portions structure, that is meeting compartment of terrain exposes the rectangular structure (please refer to the drawing 2a) along source electrode line direction; Then in described suspension gate district 200, insulating barrier (not shown) and control grid district 210(please refer to the drawing 2b is sequentially formed); Again using described control grid district 210 as shielding, aforementioned dielectric floor and suspension gate district 200 are etched, and due to the rectangular structure along source electrode line direction only part cover by suspension gate district 200, therefore in time etching, not capped part can be etched comparatively dark, thus causes the structure along source electrode line direction to produce high or low out-of-flatness phenomenon (please refer to the drawing 2c).Note that above-mentioned gate pole oxidation layer and insulating barrier although not shown, so do not affect the art and have and usually know the understanding of the knowledgeable to this prior art, and due to the knowledge being formed as this area of described gate pole oxidation layer and insulating barrier, therefore do not repeat them here.In addition, Fig. 2 a to Fig. 2 c, each figure all comprises top view and profile, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S)), and correspondence has the profile of same code.
Hold above-mentioned, the described out-of-flatness phenomenon along source electrode line direction can cause resistance value to increase, so cause access non-volatile memory components deposit data time difficulty, under the trend of assembly small-sized, this problem will more shape be severe, cannot ignore as passing.
Summary of the invention
In view of this, main purpose of the present invention is the manufacture method providing a kind of shallow slot isolation structure and manufacture method and non-voltile memory, thus addresses the deficiencies of the prior art problem.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of shallow slot isolation structure manufacture method, an embodiment of described method comprises the following step: prepare a silicon substrate; Form a pad oxide on described silicon substrate; On described pad oxide, form one first etching stop pattern (explanation of following summary of the invention is for silicon nitride pattern); To foregoing silicon substrate plate and on silicon nitride pattern etch, form a difference in height to allow between the silicon substrate that covered by silicon nitride pattern and the silicon substrate do not covered by silicon nitride pattern; After forming described difference in height, foregoing silicon substrate plate and on structure on formed one second etching stop pattern (explanation of following summary of the invention is for photoresistance pattern); After forming described photoresistance pattern, to foregoing silicon substrate plate and on structure carry out selective etch, to etch described silicon substrate and to form multiple irrigation canals and ditches; After forming described multiple irrigation canals and ditches, remove described photoresistance pattern via etching; After removing described photoresistance pattern, in described silicon substrate and on structure on form an oxide layer; After forming described oxide layer, then remove the described oxide layer of part, to expose described silicon nitride pattern; And after exposing described silicon nitride pattern, utilize etching to remove described silicon nitride pattern, to obtain shallow slot isolation structure of the present invention.
In one embodiment of the invention, aforesaid silicon nitride pattern is many silicon nitrides, and described many silicon nitrides are parallel to each other along a first direction.
In one embodiment of the invention, aforesaid photoresistance pattern is many photoresistances, and described many photoresistances are parallel to each other along a second direction.
In one embodiment of the invention, aforesaid first direction and second direction are mutually vertical.
In one embodiment of the invention, aforesaid difference in height is between 100 dust to 1000 dusts, and preferably is 200 dust to 500 dusts.Described difference in height is in order in source electrode line direction, compared to bit line direction, reserved more height space for forming thicker oxide layer, and by this structure in compensating source electrode line direction in processing procedure compared to the irregular problem of structure that the structure of bit line direction causes because bearing more etching.
Based on shallow slot isolation structure manufacture method of the present invention, the present invention separately provides a kind of manufacture method of stacking-type non-voltile memory, and an embodiment of described manufacture method comprises: prepare a silicon substrate; Form a pad oxide on described silicon substrate; A silicon nitride pattern is formed on described pad oxide; After described silicon nitride forming step completes, to described silicon substrate and on structure etch, to make to form a difference in height between the described silicon substrate that covered by described silicon nitride pattern and the described silicon substrate do not covered by described silicon nitride pattern; After described difference in height forming step completes, in described silicon substrate and on structure on form a photoresistance pattern; After described photoresistance forming step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches; After described irrigation canals and ditches forming step completes, remove described photoresistance pattern; Remove after step completes in described photoresistance, formed an oxide layer in described silicon substrate and on structure on; After described oxide layer forming step completes, remove the described oxide layer of part, to expose described silicon nitride pattern; Remove after step completes in described oxide layer portion, remove described silicon nitride pattern; Next, formed a gate pole oxidation layer in described silicon substrate and on structure on; After described gate pole oxidation layer forming step completes, on described gate pole oxidation layer, form a suspension gate district; After suspension gate district forming step completes, in described suspension gate district, form an insulating barrier; After described insulating barrier forming step completes, on described insulating barrier, form a control grid district; And after described control grid district forming step completes, using described control grid district as a shielding, described insulating barrier and described suspension gate district are etched, to define each mnemon.
Based on shallow slot isolation structure manufacture method of the present invention, the present invention also provides a kind of manufacture method being separated lock formula non-voltile memory, and an embodiment of described manufacture method comprises: prepare a silicon substrate; Form a pad oxide on described silicon substrate; A silicon nitride pattern is formed on described pad oxide; After described silicon nitride forming step completes, to described silicon substrate and on structure etch, to make to form a difference in height between the described silicon substrate that covered by described silicon nitride pattern and the described silicon substrate do not covered by described silicon nitride pattern; After described difference in height forming step completes, in described silicon substrate and on structure on form a photoresistance pattern; After described photoresistance forming step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches; After described irrigation canals and ditches forming step completes, remove described photoresistance pattern; Remove after step completes in described photoresistance, formed an oxide layer in described silicon substrate and on structure on; After described oxide layer forming step completes, remove the described oxide layer of part, to expose described silicon nitride pattern; Remove after step completes in described oxide layer portion, remove described silicon nitride pattern; Then, formed a gate pole oxidation layer in described silicon substrate and on structure on; After described gate pole oxidation layer forming step completes, on described gate pole oxidation layer, form a suspension gate district; After suspension gate district forming step completes, in described suspension gate district, form an insulating barrier; After described insulating barrier forming step completes, on described insulating barrier, form a control grid district; After described control grid district forming step completes, using described control grid district as a shielding, described insulating barrier and described suspension gate district are etched, to define each mnemon; And after described suspension gate district etching step completes, in described silicon substrate and on structure on form multiple selection lock polysilicon spacer.
Based on shallow slot isolation structure manufacture method of the present invention, the present invention provides again a kind of manufacture method being separated lock formula non-voltile memory, and an embodiment of described manufacture method comprises: prepare a silicon substrate; Form a pad oxide on described silicon substrate; A silicon nitride pattern is formed on described pad oxide; After described silicon nitride forming step completes, to described silicon substrate and on structure etch, to make to form a difference in height between the described silicon substrate that covered by described silicon nitride pattern and the described silicon substrate do not covered by described silicon nitride pattern; After described difference in height forming step completes, in described silicon substrate and on structure on form a photoresistance pattern; After described photoresistance forming step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches; After described irrigation canals and ditches forming step completes, remove described photoresistance pattern; Remove after step completes in described photoresistance, formed an oxide layer in described silicon substrate and on structure on; After described oxide layer forming step completes, remove the described oxide layer of part, to expose described silicon nitride pattern; Remove after step completes in described oxide layer portion, remove described silicon nitride pattern; Next, formed a gate pole oxidation layer in described silicon substrate and on structure on; After described gate pole oxidation layer forming step completes, on described gate pole oxidation layer, form multiple polysilicon select lock; After described polysilicon selects lock forming step to complete, select to form at least one suspension lock polysilicon spacer between lock in polysilicon described in two; After described suspension lock polysilicon spacer forming step completes, described multiple suspension lock polysilicon spacer is etched, to separate out each mnemon; And after described suspension lock polysilicon spacer etching step completes, select to form a control grid between lock in polysilicon described in two.
The present invention more provides a kind of shallow slot isolation structure, and it can utilize aforesaid shallow slot isolation structure manufacture method or its equivalent method to be manufactured, and can be applicable to manufacture non-voltile memory.One embodiment of described shallow slot isolation structure comprises: a silicon substrate, in this silicon substrate along a first direction, there is multiple first elongate structure, separately in silicon substrate along a second direction, there is multiple second elongate structure, described multiple first elongate structure and described multiple second elongate structure interlaced and form a grating texture, described grating texture comprises multiple irrigation canals and ditches, when described silicon substrate is placed in horizontal plane, often the level height of described first elongate structure is greater than the level height of often described second elongate structure, and forms a difference in height; And monoxide, fill up described multiple irrigation canals and ditches, and cover the surface of described multiple second elongate structure, thus form multiple shallow slot isolation structure.
In one embodiment of the invention, foregoing silicon substrate plate, multiple first elongate structure and multiple second elongate structure are integrated, that is described first and second elongate structure multiple is the part for silicon substrate.
In one embodiment of the invention, aforementioned first direction and second direction are mutually vertical.
In one embodiment of the invention, aforementioned height difference is between 100 dust to 1000 dusts, and preferably is 200 dust to 500 dusts.Described difference in height is in order in source electrode line direction, compared to bit line direction, reserved more height space for forming thicker oxide layer, and by this structure in compensating source electrode line direction in processing procedure compared to the irregular problem of structure that the structure of bit line direction causes because bearing more etching.
The manufacture method of shallow slot isolation structure of the present invention and manufacture method and non-voltile memory, has following beneficial effect:
The manufacture method of this shallow slot isolation structure and manufacture method and stacking-type and separation lock formula non-voltile memory can form a difference in height, thicker oxide layer is formed with the region in this difference in height place, oxide layer thicker by this again compensates this region can be etched darker phenomenon originally in successive process, thus improve originally along the phenomenon that is uneven that the structure in source electrode line direction there will be, improve this structure simultaneously and to be uneven the problems such as resistance increase that phenomenon brings.
Accompanying drawing explanation
Fig. 1 a is silicon substrate and the pad oxide schematic diagram of prior art.
Fig. 1 b is for forming the schematic diagram of silicon nitride pattern based on the structure shown in Fig. 1 a.
Fig. 1 c is for going out the schematic diagram of shallow trench based on the etch structures shown in Fig. 1 b.
Fig. 1 d is for forming the schematic diagram of oxide layer based on the structure shown in Fig. 1 c.
Fig. 1 e for based on the structure shown in Fig. 1 d via planarization process to expose the schematic diagram of silicon nitride pattern.
Fig. 1 f is for removing the schematic diagram of silicon nitride pattern based on the structure shown in Fig. 1 e.
Fig. 1 g is top view and the profile of Fig. 1 f.
Fig. 2 a is for forming the schematic diagram in suspension gate district based on the structure shown in Fig. 1 g.
Fig. 2 b is the schematic diagram based on the structure formation control gate district shown in Fig. 2 a.
Fig. 2 c is the schematic diagram based on the etch structures suspension gate district shown in Fig. 2 b.
Fig. 3 a is the schematic diagram of the silicon substrate preparation process of shallow slot isolation structure manufacture method of the present invention.
Fig. 3 b is the schematic diagram of the structure formation pad oxide based on Fig. 3 a.
Fig. 3 c is for forming the schematic diagram of silicon nitride pattern based on the structure shown in Fig. 3 b.
Fig. 3 d is the schematic diagram based on the structure height of formation difference shown in Fig. 3 c.
Fig. 3 e is for forming the schematic diagram of photoresistance pattern based on the structure shown in Fig. 3 d.
Fig. 3 f for based on shown in Fig. 3 e structure formed shallow trench schematic diagram.
Fig. 3 g is for removing the schematic diagram of photoresistance pattern based on the structure shown in Fig. 3 f.
Fig. 3 h is for forming the schematic diagram of oxide layer based on the structure shown in Fig. 3 g.
Fig. 3 i for based on the structure shown in Fig. 3 h via planarization to expose the schematic diagram of silicon nitride pattern.
Fig. 3 j is for removing the schematic diagram of silicon nitride pattern based on the structure shown in Fig. 3 i.
Fig. 3 k is schematic top view and the profile of Fig. 3 j.
Fig. 4 a is for forming the schematic diagram of pad oxide based on the structure shown in Fig. 3 k.
Fig. 4 b is for forming the schematic diagram in suspension gate district based on the structure shown in Fig. 4 a.
Fig. 4 c is for forming the schematic diagram of insulating barrier based on the structure shown in Fig. 4 b.
Fig. 4 d is the schematic diagram based on the structure formation control gate district shown in Fig. 4 c.
Fig. 4 e is the schematic diagram based on the etch structures suspension gate district shown in Fig. 4 d.
Fig. 5 a is for forming the schematic diagram of pad oxide based on the structure shown in Fig. 3 j.
Fig. 5 b is for forming the schematic diagram in suspension gate district based on the structure shown in Fig. 5 a.
Fig. 5 c is for forming the schematic diagram of insulating barrier based on the structure shown in Fig. 5 b.
Fig. 5 d is the schematic diagram based on the structure formation control gate district shown in Fig. 5 c.
Fig. 5 e is the schematic diagram based on the etch structures suspension gate district shown in Fig. 5 d.
Fig. 5 f is for forming the schematic diagram selecting lock polysilicon spacer based on the structure shown in Fig. 5 e.
Fig. 6 a is for forming the schematic diagram of pad oxide based on the structure shown in Fig. 3 k.
Fig. 6 b is for forming based on the structure shown in Fig. 6 a the schematic diagram that polysilicon selects lock.
Fig. 6 c is for forming the schematic diagram of suspension lock polysilicon spacer based on the structure shown in Fig. 6 b.
Fig. 6 d is the schematic diagram based on the etch structures suspension lock polysilicon spacer shown in Fig. 6 c.
Fig. 6 e is for forming the schematic diagram of insulating barrier based on the structure shown in Fig. 6 d.
Fig. 6 f is the schematic diagram based on the structure formation control gate shown in Fig. 6 e.
Fig. 7 a is the shallow trench structural representation of non-voltile memory of the present invention.
Fig. 7 b is the schematic diagram of the oxide in the structure shown in hiding Fig. 7 a.
[primary clustering symbol description]
100 silicon substrates
110 pad oxides
120 silicon nitride patterns
130 irrigation canals and ditches
140 oxide layers
200 suspension gate districts
210 control grid districts
300 silicon substrates
310 pad oxides
320 silicon nitride patterns
330 differences in height
340 photoresistance patterns
350 irrigation canals and ditches
360 oxide layers
400 gate pole oxidation layers
410 suspension gate districts
415 insulating barriers
420 control grid districts
500 gate pole oxidation layers
510 suspension gate districts
515 insulating barriers
520 control grid districts
530 select lock polysilicon spacer
600 gate pole oxidation layers
610 polysilicons select lock
620 suspension lock polysilicon spacers
625 insulating barriers
630 control grids
700 silicon substrates
710 first elongate structure
720 second elongate structure
730 differences in height
740 oxides.
Embodiment
Below in conjunction with accompanying drawing and embodiments of the invention, the manufacture method to shallow slot isolation structure of the present invention and manufacture method and non-voltile memory is described in further detail.
Term mentioned by this specification, as " on ", D score, " in " etc., be embodied as under possible prerequisite, connotation can comprise directly or indirectly something or certain references object " on ", D score, and directly or indirectly " in " something or certain references object, so-called " indirectly " refers to the existence still having intermediate or physical space therebetween; When mention " vicinity ", " between " etc. term time, be embodied as under possible prerequisite, connotation can comprise between two things or two references object and there is other intermediate or space, and there is not other intermediate or space.Moreover, following content is about manufacture of semiconductor, for technology such as the common oxide layer generation in manufacture of semiconductor field, micro-shadow, etching, cleaning, diffusion, implanted ions, chemistry and physical vapour deposition (PVD)s, if do not relate to technical characteristic of the present invention, will it will not go into details.In addition, the shape, size, ratio etc. of the shown assembly of icon are only signal, are to have for the art usually to know that the knowledgeable understands the present invention, but not are limited practical range of the present invention.
Refer to Fig. 3 a to Fig. 3 k, it is an embodiment schematic diagram of the shallow slot isolation structure manufacture method disclosed by the present invention, and it can be applicable in the manufacture of non-voltile memory.As shown in the figure, this embodiment comprises the following step: prepare a silicon substrate 300(and refer to Fig. 3 a); Form a pad oxide 310(pad oxide layer) on this silicon substrate 300(refer to Fig. 3 b), because the adhesive force between the silicon nitride (Nitride) that formed in successive process and silicon substrate 300 is not good, therefore first form this pad oxide 310, to increase the adhesive force of silicon nitride in successive process; Then on this pad oxide 310, form one first etching stop that the explanation of pattern 320(following examples is for silicon nitride pattern) (referring to Fig. 3 c), in this enforcement, this silicon nitride pattern 320 is many silicon nitrides be parallel to each other; Then to foregoing silicon substrate plate 300 and on silicon nitride pattern 320 etch, form a difference in height 330(between the silicon substrate 300 that covered by silicon nitride pattern 320 and the silicon substrate 300 do not covered by silicon nitride pattern 320 refer to Fig. 3 d to allow); After forming this difference in height 330, foregoing silicon substrate plate 300 and on structure on (that is on partial silicon nitride pattern 320) form one second etching and stop that the explanation of pattern 340(following examples is for photoresistance pattern) (referring to Fig. 3 e), in the present embodiment, this photoresistance pattern 340 is many photoresistances be parallel to each other; After forming this photoresistance pattern 340, to foregoing silicon substrate plate 300 and on structure (that is photoresistance pattern 340 and silicon nitride pattern 320) carry out selective etch, refer to Fig. 3 f to etch this silicon substrate 300 and to form multiple irrigation canals and ditches 350(); After forming the plurality of irrigation canals and ditches 350, remove this photoresistance pattern 340(via etching and refer to Fig. 3 g); After removing this photoresistance pattern 340, in this silicon substrate 300 and on structure on (that is on silicon nitride pattern 320) form an oxide layer 360(and refer to Fig. 3 h); After forming this oxide layer 360, then remove this oxide layer 360 of part, refer to Fig. 3 i to expose this silicon nitride pattern 320(); And after exposing this silicon nitride pattern 320, utilize etching to remove this silicon nitride pattern 320(and refer to Fig. 3 j and Fig. 3 k), to form shallow slot isolation structure of the present invention, wherein on source electrode line direction, aforementioned height differs from the region at 330 places, in bit line direction, do not have the region of this difference in height 330, can have thicker oxide layer, the structure in order to compensating source electrode line direction bears the irregular problem of structure that more etching causes in successive process.
Please note, when removing silicon nitride pattern 320, pad oxide 310 below silicon nitride pattern 320 can as an etch stop layer, and after completing and removing silicon nitride pattern 320, originally possibility residual fraction pad oxide 310 below silicon nitride pattern 320, for asking the clear display of icon, have and usually know that the knowledgeable complies with under disclosure of the present invention implements prerequisite of the present invention not affecting the art, Fig. 3 j and Fig. 3 k does not draw the pad oxide 110 that may remain.Separately please note, Fig. 3 k shows top view and the profile of Fig. 3 j, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S)), and correspondence has the profile of same code.
The visual demand of aforesaid silicon substrate 300 selects P type or N-type silicon substrate; The visual demand of photoresistance selects positive photoresistance or negative photoresistance; The visual demand of etching mode selects dry type or Wet-type etching; The visual demand of mode forming oxide layer 360 selects chemical vapour deposition technique or physical vaporous deposition, such as high density plasma enhanced chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition); One patterned as silicon nitride and photoresistance then can utilize the processing procedure means such as existing deposition/coating, micro-shadow, etching.In addition, though aforementioned first etching stops that the material of pattern 320 is silicon nitride, so this is not limitation of the present invention, this area has knows that the knowledgeable can select other applicable material to stop pattern 320 to form this first etching according to exposure of the present invention usually, and such as the first etching stops that the material of pattern 320 can be selected from the composite of silicon nitride and polysilicon one or the two composition wherein; Similarly, though the second etching stops that the material of pattern 340 is photoresistance, so this is not limitation of the present invention, and this area has knows that the knowledgeable can select other applicable material to stop pattern 340 to form this second etching according to exposure of the present invention usually.Letter speech, above-mentioned and all the other selections about conventional material, formula or people having a common goal's processing procedure means usually know known to the knowledgeable for the art has, if therefore the non-part about technical characteristic of the present invention, will it will not go into details in this specification.
In addition, as shown in Figure 3 c, aforesaid silicon nitride pattern 320 comprises many silicon nitrides, and these many silicon nitrides are parallel to each other along a first direction.In addition, as shown in Figure 3 e, aforesaid photoresistance pattern 340 comprises many photoresistances, and these many photoresistances are parallel to each other along a second direction.In the present embodiment, second direction is perpendicular to first direction.
Moreover, refer to Fig. 3 d, in the present embodiment, aforesaid difference in height 330 is between 100 dusts (ngstr m,) to 1000 dusts (), preferably is 200 dust to 500 dusts, and so this not limitation of the present invention, that is the art has knows that the knowledgeable can pass through the modes such as the formula of time or the adjustment etchant extending etching to control required difference in height 330 usually.This difference in height 330 is in order in source electrode line direction, compared to bit line direction, reserved more height space to form thicker oxide layer in successive process, the structure in compensating source electrode line direction bears compared to the structure of bit line direction the irregular problem of structure that more etching causes in successive process by this, also improves the problem that source electrode line resistance value that this out-of-flatness structure originally brings increases simultaneously.
Based on aforementioned shallow slot isolation structure manufacture method of the present invention, the present invention discloses a kind of manufacture method of stacking-type non-voltile memory on this basis further.Refer to Fig. 3 a to Fig. 3 k and Fig. 4 a to Fig. 4 e, this stacking-type non-voltile memory manufacture method comprises: prepare a silicon substrate 300(and refer to Fig. 3 a); Form a pad oxide 310 300(on this silicon substrate and refer to Fig. 3 b), because the adhesive force between the silicon nitride (such as Si3N4) that formed in successive process and silicon substrate 300 is not good, therefore first form this pad oxide 310, to increase the adhesive force of silicon nitride in successive process; On this pad oxide 310, form a silicon nitride pattern 320(refer to Fig. 3 c); To foregoing silicon substrate plate 300 and on silicon nitride pattern 320 etch, form a difference in height 330(between the silicon substrate 300 that covered by silicon nitride pattern 320 and the silicon substrate 300 do not covered by silicon nitride pattern 320 refer to Fig. 3 d to allow); After forming this difference in height 330, foregoing silicon substrate plate 300 and on structure on (that is on partial silicon nitride pattern 320) form a photoresistance pattern 340(and refer to Fig. 3 e); After forming this photoresistance pattern 340, to foregoing silicon substrate plate 300 and on structure (that is photoresistance pattern 340 and silicon nitride pattern 320) carry out selective etch, refer to Fig. 3 f to etch this silicon substrate 300 and to form multiple irrigation canals and ditches 350(); After forming the plurality of irrigation canals and ditches 350, remove this photoresistance pattern 340(via etching and refer to Fig. 3 g); After removing this photoresistance pattern 340, in this silicon substrate 300 and on structure on (that is on silicon nitride pattern 320) form an oxide layer 360(and refer to Fig. 3 h); After forming this oxide layer 360, then remove this oxide layer 360 of part, refer to Fig. 3 i to expose this silicon nitride pattern 320(); After exposing this silicon nitride pattern 320, utilize etching to remove this silicon nitride pattern 320(and refer to Fig. 3 j and Fig. 3 k); Then formed a gate pole oxidation layer (Gate Oxide) 400 in this silicon substrate 300 and on structure on (refer to Fig. 4 a); After this gate pole oxidation layer 400 forming step completes, a suspension gate district (Floating Gate Region) 410 is formed on this gate pole oxidation layer 400, this suspension gate district 410 only covers the beneath portions structure along source electrode line direction, that is meeting compartment of terrain exposes the structure (referring to Fig. 4 b) along source electrode line direction; After suspension gate district 410 forming step completes, in this suspension gate district 410, form an insulating barrier 415(such as Oxide-Nitride-Oxide floor) (referring to Fig. 4 c); After this insulating barrier 415 forming step completes, on this insulating barrier 415, form a control grid district (Control Gate Region) 420(refer to Fig. 4 d); And after this control grid district 420 forming step completes, using this control grid district 420 as a shielding, this insulating barrier 415 and this suspension gate district 410 are etched, to define each mnemon (referring to Fig. 4 e).Be formed at the region that source electrode do not overlap with bit line online because aforementioned height differs from 330; thus thicker oxide layer can be formed in this region in time forming aforementioned oxidation layer 360; although therefore this region is not covered completely by suspension gate district 410; can be etched darker as protective layer because having lacked suspension gate district 410 in time etching; but because this thicker oxide layer also discloses more etching protection simultaneously; thus can compensate this region and originally can be etched darker phenomenon, and then improve the rugged phenomenon that the structure along source electrode line direction occurs.
Please note, in Fig. 4 a to Fig. 4 e, each figure all comprises top view and profile, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S)), and correspondence has the profile of same code.
The formation of above-mentioned gate pole oxidation layer 400, the formation in suspension gate district 410, insulating barrier 415 and the formation in control grid district 420 and the carrying out of etching, current existing process technique all can be utilized to complete, such as, utilize the processing procedure means such as existing deposition/coating, micro-shadow, etching.Selection as material, formula or people having a common goal's processing procedure means usually knows known to the knowledgeable for the art has, the material in such as suspension gate district 410 can select polysilicon, insulating barrier can by oxide layer-nitride layer-oxide layer to form and the material in control grid district 420 can select polysilicon.As for the existing skill of non-pass technical characteristic of the present invention, by it will not go into details in this specification.
Based on aforementioned shallow slot isolation structure manufacture method of the present invention, the present invention discloses again a kind of manufacture method being separated lock formula non-voltile memory.Refer to Fig. 3 a to Fig. 3 k and Fig. 5 a to Fig. 5 f, this separation lock formula non-voltile memory manufacture method comprises the following step: prepare a silicon substrate 300(and refer to Fig. 3 a); Form a pad oxide 310 300(on this silicon substrate and refer to Fig. 3 b), because the adhesive force between the silicon nitride that formed in successive process and silicon substrate 300 is not good, therefore first form this pad oxide 310, to increase the adhesive force of silicon nitride in successive process; On this pad oxide 310, form a silicon nitride pattern 320(refer to Fig. 3 c); To foregoing silicon substrate plate 300 and on silicon nitride pattern 320 etch, form a difference in height 330(between the silicon substrate 300 that covered by silicon nitride pattern 320 and the silicon substrate 300 do not covered by silicon nitride pattern 320 refer to Fig. 3 d to allow); After forming this difference in height 330, foregoing silicon substrate plate 300 and on structure on (that is on partial silicon nitride pattern 320) form a photoresistance pattern 340(and refer to Fig. 3 e); After forming this photoresistance pattern 340, to foregoing silicon substrate plate 300 and on structure (that is photoresistance pattern 340 and silicon nitride pattern 320) carry out selective etch, refer to Fig. 3 f to etch this silicon substrate 300 and to form multiple irrigation canals and ditches 350(); After forming the plurality of irrigation canals and ditches 350, remove this photoresistance pattern 340(via etching and refer to Fig. 3 g); After removing this photoresistance pattern 340, in this silicon substrate 300 and on structure on (that is on silicon nitride pattern 320) form an oxide layer 360(and refer to Fig. 3 h); After forming this oxide layer 360, then remove this oxide layer 360 of part, refer to Fig. 3 i to expose this silicon nitride pattern 320(); After exposing this silicon nitride pattern 320, utilize etching to remove this silicon nitride pattern 320(and refer to Fig. 3 j and Fig. 3 k); Next, formed a gate pole oxidation layer 500 in this silicon substrate 300 and on structure on (refer to Fig. 5 a); After this gate pole oxidation layer 500 forming step completes, on this gate pole oxidation layer 500, form a suspension gate district 510(refer to Fig. 5 b); After suspension gate district 510 forming step completes, in this suspension gate district 510, form an insulating barrier 515(refer to Fig. 5 c); After this insulating barrier 515 forming step completes, on this insulating barrier 515, form a control grid district 520(refer to Fig. 5 d); After this control grid district 520 forming step completes, using this control grid district 520 as a shielding, this insulating barrier 515 and this suspension gate district 510 are etched, to define each mnemon (referring to Fig. 5 e); And after this suspension gate district 510 etching step completes, in this silicon substrate 300 and on structure on form multiple selection lock polysilicon spacer 530(Select Gate Poly Spacer Formation) (referring to Fig. 5 f).
Please note, in Fig. 5 a to Fig. 5 f, each figure all comprises top view and profile, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S)), and correspondence has the profile of same code.
The formation in the formation of above-mentioned gate pole oxidation layer 500, the formation in suspension gate district 510, insulating barrier 515 and control grid district 520, select the formation of lock polysilicon spacer 530 and the carrying out of etching, current existing process technique all can be utilized to complete, such as, utilize the processing procedure means such as existing deposition/coating, micro-shadow, etching.Selection as material, formula or people having a common goal's processing procedure means usually knows known to the knowledgeable for the art has, therefore the non-part about technical characteristic of the present invention, by it will not go into details in this specification.
Based on aforementioned shallow slot isolation structure manufacture method of the present invention, the present invention also discloses the another kind of manufacture method being separated lock formula non-voltile memory.Refer to Fig. 3 a to Fig. 3 k and Fig. 6 a to Fig. 6 f, this separation lock formula non-voltile memory manufacture method comprises the following step: prepare a silicon substrate 300(and refer to Fig. 3 a); Form a pad oxide 310 300(on this silicon substrate and refer to Fig. 3 b), because the adhesive force between the silicon nitride that formed in successive process and silicon substrate 300 is not good, therefore first form this pad oxide 310, to increase the adhesive force of silicon nitride in successive process; On this pad oxide 310, form a silicon nitride pattern 320(refer to Fig. 3 c); To foregoing silicon substrate plate 300 and on silicon nitride pattern 320 etch, form a difference in height 330(between the silicon substrate 300 that covered by silicon nitride pattern 320 and the silicon substrate 300 do not covered by silicon nitride pattern 320 refer to Fig. 3 d to allow); After forming this difference in height 330, foregoing silicon substrate plate 300 and on structure on (that is on partial silicon nitride pattern 320) form a photoresistance pattern 340(and refer to Fig. 3 e); After forming this photoresistance pattern 340, to foregoing silicon substrate plate 300 and on structure (that is photoresistance pattern 340 and silicon nitride pattern 320) carry out selective etch, refer to Fig. 3 f to etch this silicon substrate 300 and to form multiple irrigation canals and ditches 350(); After forming the plurality of irrigation canals and ditches 350, remove this photoresistance pattern 340(via etching and refer to Fig. 3 g); After removing this photoresistance pattern 340, in this silicon substrate 300 and on structure on (that is on silicon nitride pattern 320) form an oxide layer 360(and refer to Fig. 3 h); After forming this oxide layer 360, then remove this oxide layer 360 of part, refer to Fig. 3 i to expose this silicon nitride pattern 320(); After exposing this silicon nitride pattern 320, recycling etching removes this silicon nitride pattern 320(and refers to Fig. 3 j and Fig. 3 k); Next, formed a gate pole oxidation layer 600 in this silicon substrate and on structure on (refer to Fig. 6 a); After this gate pole oxidation layer 600 forming step completes, on this gate pole oxidation layer 600, form multiple polysilicon select lock 610(Select Gate Poly Formation) (referring to Fig. 6 b); After this polysilicon selects lock 610 forming step to complete, select to form at least one suspension lock polysilicon spacer 620(Floating Gate Poly Spacer Formation between lock 610 in two these polysilicons) (referring to Fig. 6 c); After this suspension lock polysilicon spacer 620 forming step completes, the plurality of suspension lock polysilicon spacer 620 is etched, to separate out each mnemon (referring to Fig. 6 d); After the plurality of suspension lock polysilicon spacer 620 etching, form an insulating barrier 625 in selecting on lock 610 (please refer to the drawing 6e) in the plurality of polysilicon; And after this suspension lock polysilicon spacer 620 etching step completes, select to form a control grid 630(between lock in two these polysilicons and refer to Fig. 6 f).
Please note, in Fig. 6 a to Fig. 6 f, each figure all comprises top view and profile, wherein top view is painted with hatching, each hatching all indicates code (X1 (WL), X1 (SL), Y1 (BL), Y2 (BL_S), X1 (SP)), and correspondence has the profile of same code.
The formation of lock 610, the formation of suspension lock polysilicon spacer 620, insulating barrier 652 and the formation of control grid 630 and the carrying out of etching are selected in the formation of above-mentioned gate pole oxidation layer 600, polysilicon, current existing process technique all can be utilized to complete, such as, utilize the processing procedure means such as existing deposition/coating, micro-shadow, etching.Selection as material, formula or people having a common goal's processing procedure means usually knows known to the knowledgeable for the art has, so the non-part about technical characteristic of the present invention, by it will not go into details in this specification.
The present invention also discloses a kind of shallow slot isolation structure, and it can utilize aforesaid shallow slot isolation structure manufacture method or its equivalent method to be manufactured, and can be applicable to the manufacture of non-voltile memory or the manufacture of other suitable semiconductor subassembly.Refer to Fig. 7 a and Fig. 7 b, and coordinate and consult 3a to 3j and scheme, one embodiment of this shallow slot isolation structure comprises: a silicon substrate 700, along a first direction, there is multiple first elongate structure 710 on this silicon substrate 700 surface, separately in silicon substrate along a second direction, there is multiple second elongate structure 720, the plurality of first elongate structure 710 is interlaced and form a grating texture with the plurality of second elongate structure 720, this grating texture comprises in multiple irrigation canals and ditches 730(the present embodiment, each lattice defines irrigation canals and ditches 730), when this silicon substrate 700 is placed in horizontal plane, the level height of each the first elongate structure 710 is greater than the level height of each the second elongate structure 720, thus a difference in height 740 is formed, and monoxide 750, be used for filling up the plurality of irrigation canals and ditches 730, and cover the surface of the plurality of second elongate structure 720, thus form multiple shallow slot isolation structure.
Note that Fig. 7 b is the schematic diagram after the oxide 750 shown in hiding Fig. 7 a, in order to the shallow slot isolation structure helping the reader of this specification to better understand the present embodiment, in fact not remove this oxide 750.
In the above embodiments, this silicon substrate 700, multiple first elongate structure 710 are be integrated with multiple second elongate structure 720, and in other words, first and second elongate structure the plurality of is the part for silicon substrate 700; In addition, described first direction and second direction are mutually vertical; Moreover this difference in height 740 is between 100 dust to 1000 dusts, preferably is 200 dust to 500 dusts.Similarly, this difference in height 740 is in order in source electrode line direction, compared to bit line direction, reserved more height space for forming thicker oxide layer, and by this structure in compensating source electrode line direction in processing procedure compared to the irregular problem of structure that the structure of bit line direction causes because bearing more etching.
The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (9)
1. a manufacture method for stacking-type non-voltile memory, is characterized in that, the manufacture method of described stacking-type non-voltile memory comprises:
One silicon substrate preparation process is preparation one silicon substrate;
One pad oxide forming step is that formation one pad oxide is on described silicon substrate;
One first etch stop layer forming step is that formation one first etches stop pattern on described pad oxide;
One difference in height forming step, after described first etch stop layer forming step completes, to described silicon substrate and on structure etch, form a difference in height to make to be etched between the described silicon substrate stopping that pattern covers and the described silicon substrate being stopped pattern covering by described first etching by described first, wherein said difference in height is between 100 dust to 1000 dusts;
One second etch stop layer forming step is after described difference in height forming step completes, formed one second etching stop pattern in described silicon substrate and on structure on;
One irrigation canals and ditches forming step is after described second etching stops that forming step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches;
One second etch stop layer removes step, is after described irrigation canals and ditches forming step completes, and removes described second etching and stops pattern;
One oxide layer forming step, is remove after step completes in described second etch stop layer, forms an oxide layer on described silicon substrate, and covers described first etching and stop pattern and described multiple irrigation canals and ditches;
One oxide layer portion removes step, is after described oxide layer forming step completes, removes the described oxide layer of part, stops pattern to expose described first etching;
One first etch stop layer removes step, is to remove after step completes in described oxide layer portion, removes described first etching and stops pattern;
One gate pole oxidation layer forming step removes after step completes in described first etch stop layer, formed a gate pole oxidation layer in described silicon substrate and on structure on;
One suspension gate district forming step is after described gate pole oxidation layer forming step completes, and forms a suspension gate district on described gate pole oxidation layer;
One insulating barrier forming step, is after suspension gate district forming step completes, in described suspension gate district, forms an insulating barrier;
One control grid district forming step, is after described insulating barrier forming step completes, forms a control grid district on described insulating barrier; And
One suspension gate district etching step is after described control grid district forming step completes, and using described control grid district as a shielding, etches described insulating barrier and described suspension gate district, to define each mnemon.
2. be separated a manufacture method for lock formula non-voltile memory, it is characterized in that, the manufacture method of described separation lock formula non-voltile memory comprises:
One silicon substrate preparation process is preparation one silicon substrate;
One pad oxide forming step is that formation one pad oxide is on described silicon substrate;
One first etch stop layer forming step is that formation one first etches stop pattern on described pad oxide;
One difference in height forming step, after described first etching stops that pattern formation step completes, to described silicon substrate and on structure etch, form a difference in height to make to be etched between the described silicon substrate stopping that pattern covers and the described silicon substrate being stopped pattern covering by described first etching by described first, wherein said difference in height is between 100 dust to 1000 dusts;
One second etch stop layer forming step is after described difference in height forming step completes, formed one second etching stop pattern in described silicon substrate and on structure on;
One irrigation canals and ditches forming step is after described second etching stops that pattern formation step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches;
One second etch stop layer removes step, is after described irrigation canals and ditches forming step completes, and removes described second etching and stops pattern;
One oxide layer forming step, is remove after step completes in described second etch stop layer, forms an oxide layer on described silicon substrate, and covers described first etching and stop pattern and described multiple irrigation canals and ditches;
One oxide layer portion removes step, is after described oxide layer forming step completes, removes the described oxide layer of part, stops pattern to expose described first etching;
One first etch stop layer removes step, is to remove after step completes in described oxide layer portion, removes described first etching and stops pattern;
One gate pole oxidation layer forming step removes after step completes in described first etch stop layer, formed a gate pole oxidation layer in described silicon substrate and on structure on;
One suspension gate district forming step is after described gate pole oxidation layer forming step completes, and forms a suspension gate district on described gate pole oxidation layer;
One insulating barrier forming step, is after suspension gate district forming step completes, in described suspension gate district, forms an insulating barrier;
One control grid district forming step, is after described insulating barrier forming step completes, forms a control grid district on described insulating barrier;
One suspension gate district etching step is after described control grid district forming step completes, and using described control grid district as a shielding, etches described insulating barrier and described suspension gate district, to define each mnemon; And
One selects lock polysilicon spacer forming step, is after described suspension lock district etching step completes, in described silicon substrate and on structure on form multiple selection lock polysilicon spacer.
3. be separated a manufacture method for lock formula non-voltile memory, it is characterized in that, the manufacture method of described separation lock formula non-voltile memory comprises:
One silicon substrate preparation process is preparation one silicon substrate;
One pad oxide forming step is that formation one pad oxide is on described silicon substrate;
One first etch stop layer forming step on described pad oxide, forms one first etching stop pattern;
One difference in height forming step, after described first etch stop layer forming step completes, to described silicon substrate and on structure etch, form a difference in height to make to be etched between the described silicon substrate stopping that pattern covers and the described silicon substrate being stopped pattern covering by described first etching by described first, wherein said difference in height is between 100 dust to 1000 dusts;
One second etch stop layer forming step is after described difference in height forming step completes, in described silicon substrate and on structure on formed one second etching stop pattern;
One irrigation canals and ditches forming step is after described second etch stop layer forming step completes, to described silicon substrate and on structure carry out selective etch, to etch described silicon substrate, and form multiple irrigation canals and ditches;
One second etch stop layer removes step, is after described irrigation canals and ditches forming step completes, and removes described second etching and stops pattern;
One oxide layer forming step removes after step completes in described second etch stop layer, formed an oxide layer in described silicon substrate and on structure on;
One oxide layer portion removes step, is after described oxide layer forming step completes, removes the described oxide layer of part, stops pattern to expose described first etching;
One first etch stop layer removes step, is to remove after step completes in described oxide layer portion, removes described first etching and stops pattern;
One gate pole oxidation layer forming step removes after step completes in described first etch stop layer, formed a gate pole oxidation layer in described silicon substrate and on structure on;
One polysilicon selects lock forming step, is after described gate pole oxidation layer forming step completes, and forms multiple polysilicon and select lock on described gate pole oxidation layer;
One suspension lock polysilicon spacer forming step is after described polysilicon selects lock forming step to complete, and selects to form at least one suspension lock polysilicon spacer between lock in polysilicon described in two;
One suspension lock polysilicon spacer etching step, is after described suspension lock polysilicon spacer forming step completes, etches, to separate out each mnemon described multiple suspension lock polysilicon spacer;
One insulating barrier forming step is after described suspension lock polysilicon spacer etching step completes, and forms an insulating barrier and selects on lock in described multiple polysilicon; And
One polysilicon control gate forming step is after described insulating barrier forming step completes, and selects to form a control grid between lock in polysilicon described in two.
4. a shallow slot isolation structure, is characterized in that, described shallow slot isolation structure comprises:
One silicon substrate, in described silicon substrate along a first direction, there is multiple first elongate structure, in described silicon substrate along a second direction, there is multiple second elongate structure, described multiple first elongate structure and described multiple second elongate structure interlaced and form multiple irrigation canals and ditches, often the level height of described first elongate structure is greater than the level height of often described second elongate structure, and form a difference in height, wherein said difference in height is between 100 dust to 1000 dusts, and described first direction is perpendicular to described second direction; And
Monoxide, fills up described multiple irrigation canals and ditches, and covers the surface of described multiple second elongate structure, thus forms described shallow slot isolation structure.
5. shallow slot isolation structure according to claim 4, is characterized in that, wherein said silicon substrate, described multiple first elongate structure and described multiple second elongate structure are integrated.
6. shallow slot isolation structure according to claim 4, wherein said difference in height is between 200 dust to 500 dusts.
7. the manufacture method according to claim 1,2 or 3, is characterized in that, wherein said difference in height is between 200 dust to 500 dusts.
8. the manufacture method according to claim 1,2 or 3, is characterized in that, wherein said first etching stops that the material of pattern is the composite being selected from silicon nitride and polysilicon one or the two composition wherein.
9. the manufacture method according to claim 1,2 or 3, is characterized in that, wherein said second etching stops that the material of pattern is photoresistance.
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| CN201210211405.0A CN103066006B (en) | 2012-06-21 | 2012-06-21 | Shallow trench isolation structure, manufacturing method thereof and non-volatile random access memory (RAM) manufacturing method |
| TW101136981A TWI482237B (en) | 2012-06-21 | 2012-10-05 | Shallow trench isolation structure and fabrication method thereof, and method for fabricating non-volatile memory |
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| KR100335999B1 (en) * | 2000-07-25 | 2002-05-08 | 윤종용 | Method for Self-Aligned Shallow Trench Isolation and Method of manufacturing Non-Volatile Memory Device comprising the same |
| KR100469128B1 (en) * | 2002-11-07 | 2005-01-29 | 삼성전자주식회사 | Method of forming floating gate of non-volatile memory device having self-aligned shallow trench isolation |
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| US8008701B2 (en) * | 2004-12-22 | 2011-08-30 | Giorgio Servalli | Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained |
| KR100812080B1 (en) * | 2007-06-26 | 2008-03-07 | 주식회사 동부하이텍 | Non volatile memory device and method for fabricating the same |
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