CN103064223A - Array substrate and display panel - Google Patents
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- CN103064223A CN103064223A CN2013100040023A CN201310004002A CN103064223A CN 103064223 A CN103064223 A CN 103064223A CN 2013100040023 A CN2013100040023 A CN 2013100040023A CN 201310004002 A CN201310004002 A CN 201310004002A CN 103064223 A CN103064223 A CN 103064223A
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Abstract
The invention discloses an array substrate and a display panel which are used for realizing no height difference in binding areas in a double-layer wired display and avoiding defective display generated by poor binding uniformity. A non-display area of the array substrate comprises a data signal input end inputting signals into the non-display area. The data signal input end comprises a plurality of first leads and second leads which correspond to data lines of a display area and are arranged at intervals. Each first lead comprises a first grating lead and a first data line lead, a first via hole and a second via hole are formed above the first grating lead and the first data line lead, and the first grating lead and the first data line lead are conducted through a first conducting layer. The second leads and the data lines in the display area share the same layer to form second data line leads, and third via holes and a second conducting layer are formed above the second data line leads. A driving circuit is bound on the first conducting layer above the first data line leads and on the second conducting layer above the second data line leads.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of array base palte and a kind of display panel.
Background technology
The display apparatus modules such as Thin Film Transistor-LCD connect driving circuit by the active array panel usually, then connect other necessary external circuit and consist of.Wherein driving circuit is connected connection and usually need to is bound to realize at the signal input part of arraying bread board with arraying bread board, be that integrated circuit or thin film chip are integrated, flexible PCB etc. is crimped on the signal input part of panel by anisotropy conductiving glue, thereby realizes the conducting of signal.At present, in some small sizes or the high-resolution product, because the increase of wiring density on the arraying bread board, signal input part adopts grid metal level and data wire metal layer double layer of metal to realize usually.As shown in Figure 1, the non-display area of panel comprises data-signal input end A and signal input end B, is used for receiving signal input or data-signal input.Wherein, data-signal input end A comprises the regional A1 with the driving circuit binding, concrete, as shown in Figure 2: the regional A1 of binding comprises a plurality of the 010 and second binding districts 020, the first binding district that replace, the 010 and second binding district 020, the first binding district is the data-signal of receiving integrate circuit pin output respectively, then transmits along corresponding cabling.
Array base palte shown in Figure 3 is respectively the binding of first in the corresponding diagram 2 district 010 along sectional view and the second binding district 020 sectional view along b-b ' direction of a-a ' direction.Corresponding the first binding district 010 side, as shown in Figure 3, this array base palte comprises glass substrate 100, grid line 110, the first insulation course 130, data line 120, the second insulation courses 140, conductive layer 150, and wherein, on grid line 110, be provided with the first binding area 0 10; Corresponding the second binding district 020 side, as shown in Figure 3, array base palte comprises on lower and comprises successively glass substrate 100, the first insulation course 130, active layer 160, data line 120, the second insulation course 140 and conductive layer 150, wherein, be provided with the second binding district 020 on the data line 120.
Because the difference of material and technique unavoidably can produce certain difference in height in the binding district.The height in the first binding district 010 be 4-1. with 4-2., the height in the second binding district 020 be 4-3. with 4-4..Because the difference of thicknesses of layers is higher than 4-h1 such as 4-h2 among Fig. 3, so 4-1. ≠ 4-3., 4-2. ≠ 4-4..Because the first binding district is different with the height in the second binding district, the homogeneity difference when causing integrated circuit and array base palte crimping between line.Therefore greatly increased because of the bad risk of the binding poor demonstration that produces of homogeneity.
Summary of the invention
The embodiment of the invention provides a kind of array base palte, without difference in height, and then has avoided the bad problem of demonstration because of binding homogeneity poor generation in order to the binding district in the display of realizing two-layer wiring.
A kind of array base palte that the embodiment of the invention provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises many data lines and many grid lines, described non-display area comprises that to the data-signal input end of the data line input signal of described viewing area described data-signal input end comprises that many first of and interval setting corresponding with described viewing area data line go between and the second lead-in wire; Wherein said the first lead-in wire comprises the first grid lead-in wire that forms with layer with the grid line of described viewing area and first data cable lead wire that forms with layer with the data line of described viewing area, described first grid lead-in wire and described the first data cable lead wire top are formed with the first via hole and the second via hole, and described first grid lead-in wire and described the first data cable lead wire are by covering the first conductive layer conducting of described the first via hole and the second via hole; Second conductive layer that second data cable lead wire of described the second lead-in wire for forming with layer with the data line of described viewing area, described the second data cable lead wire top are provided with the 3rd via hole and cover described the 3rd via hole and form with layer with described the first conductive layer; Described driving circuit is bundled on first conductive layer and the second conductive layer above the second data cable lead wire of described the first data cable lead wire top.
A kind of display panel that the embodiment of the invention provides comprises above-mentioned array base palte.
The array base palte that the embodiment of the invention provides, the zone of the data-signal input end in non-display area and integrated circuit binding, conductive layer is identical apart from the height of glass substrate, thereby can not cause the difference that produces crimped status between line when being connected with integrated circuit, avoid because of the bad problem of the binding poor demonstration that produces of homogeneity.
Description of drawings
Fig. 1 is the binding synoptic diagram of glass-chip integrated (Chip on Glass) technology in the prior art;
Fig. 2 is the vertical view of the structure of binding in the prior art;
Fig. 3 is the cross-sectional view in the 010 and second binding district 020, the first binding district in the structure shown in Figure 2;
The schematic top plan view of a kind of data-signal input end that Fig. 4 provides for the embodiment of the invention;
Fig. 5 is the first lead-in wire and the second cross-sectional view that goes between in the structure shown in Figure 4;
Prepare the structural representation of grid line pattern among the preparation method of Fig. 6 (a) for the array base palte of structure shown in Figure 5;
Fig. 6 (b) is the structural representation after the substrate shown in Fig. 6 (a) is prepared active layer and data line layer;
Fig. 6 (c) is the structural representation after the substrate shown in Fig. 6 (b) is prepared insulation course;
Fig. 6 (d) is the structural representation after the substrate shown in Fig. 6 (c) is prepared via hole;
Fig. 6 (e) is the structural representation after the substrate shown in Fig. 6 (d) is prepared conductive layer;
Another kind the first lead-in wire and the second cross-sectional view that goes between that Fig. 7 provides for the embodiment of the invention;
Prepare the structural representation of grid line pattern among the preparation method of Fig. 8 (a) for array base palte shown in Figure 7;
Fig. 8 (b) is the structural representation after the substrate shown in Fig. 8 (a) is prepared data line layer;
Fig. 8 (c) is the structural representation after the substrate shown in Fig. 8 (b) is prepared insulation course;
Fig. 8 (d) is the structural representation after the substrate shown in Fig. 8 (c) is prepared via hole;
Fig. 8 (e) is the structural representation after the substrate shown in Fig. 8 (d) is prepared conductive layer.
Embodiment
The embodiment of the invention provides a kind of array base palte, without difference in height, and then has avoided the bad problem of demonstration because of binding homogeneity poor generation in order to the binding district in the display of realizing two-layer wiring.
A kind of array base palte that the embodiment of the invention provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises many data lines and many grid lines, described non-display area comprises that to the data-signal input end of the data line input signal of described viewing area described data-signal input end comprises that many first of and interval setting corresponding with described viewing area data line go between and the second lead-in wire; Wherein said the first lead-in wire comprises the first grid lead-in wire that forms with layer with the grid line of described viewing area and first data cable lead wire that forms with layer with the data line of described viewing area, described first grid lead-in wire and described the first data cable lead wire top are formed with the first via hole and the second via hole, and described first grid lead-in wire and described the first data cable lead wire are by covering the first conductive layer conducting of described the first via hole and the second via hole; Second conductive layer that second data cable lead wire of described the second lead-in wire for forming with layer with the data line of described viewing area, described the second data cable lead wire top are provided with the 3rd via hole and cover described the 3rd via hole and form with layer with described the first conductive layer; Described driving circuit is bundled on first conductive layer and the second conductive layer above the second data cable lead wire of described the first data cable lead wire top.
Preferably, described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, described the first data cable lead wire and the second data cable lead wire below are respectively arranged with the first insulation course and active layer, and described the first data lead and the second data lead top are provided with the second insulation course.
Preferably, described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, obtain the first data cable lead wire and the second data cable lead wire below and be provided with the first insulation course, described the first data cable lead wire and the second data cable lead wire top are provided with the second insulation course.
Below in conjunction with the drawings and specific embodiments, the present invention will be described.
Embodiment 1
A kind of array base palte that the embodiment of the invention 1 provides, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises many data lines and many grid lines, described non-display area comprises to the data-signal input end of the data line input signal of described viewing area, herein can be equally with reference to shown in the accompanying drawing 1.
Below in conjunction with accompanying drawing the data-signal input end is elaborated.Referring to Fig. 4, described data-signal input end comprises many first lead-in wires the 200 and second lead-in wire 300 corresponding with described viewing area data line and that the interval arranges; Wherein said the first lead-in wire 200 comprises the first grid lead-in wire 211 that forms with layer with the grid line of described viewing area and first data cable lead wire 212 that forms with layer with the data line of described viewing area, described first grid lead-in wire 211 and described the first data cable lead wire 212 tops are formed with the first via hole 221 and the second via hole 222, and described first grid lead-in wire 211 and described the first data cable lead wire 212 are by covering the first conductive layer 231 conductings of described the first via hole 221 and the second via hole 222; Described the second lead-in wire 300 be second data cable lead wire 312 that forms with layer with the data line of described viewing area, described the second data cable lead wire top be provided with the 3rd via hole 321 and cover described the 3rd via hole and with second conductive layer 331 of described the first conductive layer with layer formation; Described driving circuit (not shown) is bundled on first conductive layer 231 and the second conductive layer 331 above the second data cable lead wire of described the first data cable lead wire top.
Further, for c-c ' among the figure and d-d ' position, its cross-section structure is with reference to shown in Figure 5, for the first via hole 221 position side in the first lead-in wire 200, array base palte comprises from bottom to up successively: glass substrate 100, the first insulation course 130, active layer 160 and the first data cable lead wire 212, the second insulation course 140, and the first via hole 221 that is arranged in the second insulation course 140 cover the first conductive layer 231 of the first via hole and the second insulation course; For the second via hole 222 position side in the first lead-in wire 200, array base palte comprises on lower successively: this glass substrate of glass substrate 100(is the substrate of whole array base palte), first grid lead-in wire 211, the first insulation course 130, the second insulation course 140, and etching the first insulation course and the second insulation course and the second via hole 222 of obtaining, cover the first conductive layer 231 of the second via hole and the second insulation course, wherein this first conductive layer covers the first via hole and the second via hole, and first data cable lead wire that will be positioned at simultaneously under the first via hole connects with first grid lead-in wire under being connected the second via hole.For the second lead-in wire 300, array base palte comprises on lower successively: glass substrate 100, the first insulation course 130, active layer 160, the second data cable lead wire 312, the second insulation course 140, the 3rd via hole 321 that obtains by etching the second insulation course 140, and the second conductive layer 331 that covers the 3rd via hole.Wherein, be positioned at the conductive layer 231 and driving circuit binding of the first via hole 221 tops of the first data cable lead wire top, be positioned at the conductive layer 331 and driving circuit binding of the 3rd via hole 321 tops of the second data cable lead wire top, as can be seen from Figure 5,4. 2. the conductive layer 231 of the first via hole 221 tops be 4-h2 with the conductive layer 331 of the 3rd via hole 321 tops apart from the height 24-at the bottom of the glass substrate apart from the height 24-at the bottom of the glass substrate and equate, 1. with near the conductive layer 331 on the second insulation course 140 of the 3rd via hole 321 3. equates apart from the height 24-at the bottom of the glass substrate apart from the height 24-at the bottom of the glass substrate near the conductive layer 231 on the second insulation course 140 of the first via hole 221 simultaneously.So, when binding with driving circuit, the height in data-signal input end binding district is consistent in the time of can guaranteeing to bind to the data-signal input end of viewing area data line input data signal, can not cause that demonstration that cause is bad because the height in binding district is inhomogeneous.
The array base palte that the embodiment of the invention 1 provides, by the preparation of 4 composition techniques, referring to Fig. 6 (a) to 6(e), this preparation method comprises:
On glass substrate, form grid line and each first grid lead-in wire 211 by metal deposition, exposure, development and etching, shown in Fig. 6 (a);
Forming substrate deposition first insulation course 130 of above-mentioned pattern, material is silicon nitride normally, also can use monox and silicon oxynitride etc.;
Forming substrate deposition active layer 160 and the data line layer of above-mentioned pattern, data line layer comprises data line and the first data cable lead wire 212 and the second data cable lead wire 312.And then by exposure, development and etching, form data line layer and active layer figure; Herein, the active layer that is positioned at below the data line layer of non-display area is retained, and other place is etched away, shown in Fig. 6 (b); Be positioned at the pattern of viewing area, then comprised the pattern (not shown) of data line and tft array;
Forming substrate deposition second insulation course 140 of data line layer and active layer figure, material is silicon nitride or transparent organic resin material normally, shown in Fig. 6 (c);
On the substrate that forms the second insulation course 140, form a plurality of via holes by exposure and etching again, wherein the second insulation course of the second via hole 222 and the first insulation course are by whole etchings, second insulation course at the first via hole 221 and the 3rd via hole 321 places is etched, shown in Fig. 6 (d);
Depositing conducting layer on the substrate that forms a plurality of via holes, material is ITO, and then forms the first conductive layer 231 and the second conductive layer 331ITO pattern by exposure, development and etching, shown in Fig. 6 (e).
Through above-mentioned technique, can obtain to realize the array base palte of the object of the invention.
Embodiment 2
A kind of array base palte that the embodiment of the invention 2 provides, the array base palte difference that provides with embodiment 1 is, present embodiment 2 described array base paltes are to make by 5 composition techniques, as shown in Figure 7, between the first insulation course 130 and the first data cable lead wire 212, between the first insulation course 130 and the second data cable lead wire 312, do not have active layer.But identical with embodiment is, with the first conductive layer and second conductive layer of driving circuit binding be to make with layer, and highly be 5-h2, therefore to distinguish the demonstration that difference in height causes bad because of binding having avoided equally.
Concrete, to Fig. 8 (e), its preparation method comprises referring to Fig. 8 (a):
On glass substrate, form the pattern that comprises grid line and each first grid lead-in wire 211 by metal deposition, exposure, development and etching, shown in Fig. 8 (a);
Forming substrate deposition first insulation course 130 of above-mentioned pattern;
Deposit active layer at the substrate that forms the first insulation course 130, by exposure, development and etching, so that the active layer that is positioned at below the data line layer of non-display area all is etched away herein;
Next form the data line pattern at substrate by metal deposition, exposure, development and etching, comprise the data line that is positioned at the viewing area and the first data cable lead wire 212 and second data cable lead wire 312 of non-display area, shown in Fig. 8 (b);
Forming substrate deposition second insulation course 140 of above-mentioned pattern, shown in Fig. 8 (c);
On the substrate that forms the second insulation course 140, form a plurality of via holes by exposure and etching again, wherein with second insulation course at the second via hole place 222 and the first insulation course by whole etchings, second insulation course at the first via hole and the 3rd via hole place is etched, shown in Fig. 8 (d);
Forming depositing conducting layer on the substrate of a plurality of via holes, for example material is transparent conductive oxide film ITO, and then forms the pattern of the first conductive layer 231 and the second conductive layer 331ITO by exposure, development and etching, shown in Fig. 8 (e).
Preferably, adopt the structure of array base palte provided by the invention, in the driving process, the data-signal that is sent by integrated circuit is transferred on the panel by the first conductive layer and the second conductive layer, then data-signal transfers to each data line of viewing area along corresponding cabling connected mode, thereby the control according to sweep signal shows.Particularly, data signal data is exported from integrated circuit, at the first lead-in wire place, is received by the first conductive layer 231 that is positioned at the first via hole 221 tops, is transferred to the first data cable lead wire 212 by the first via hole 221, enters the viewing area; At the second lead-in wire place, the second conductive layer 331 receives the second data cable lead wire 312 that is transferred to its below by the 3rd via hole 321, enters the viewing area.
In sum, the array base palte that the embodiment of the invention provides, conductive layer with the driving circuit binding in the data-signal input end in non-display area is identical apart from the height of glass substrate, thereby can not cause the difference that produces crimped status between line when being connected with integrated circuit, avoid because of the bad problem of the binding poor demonstration that produces of homogeneity.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (4)
1. array base palte, comprise viewing area, non-display area and driving circuit, wherein said viewing area comprises many data lines and many grid lines, described non-display area comprises to the data-signal input end of the data line input signal of described viewing area, it is characterized in that: described data-signal input end comprises that many first of and interval setting corresponding with described viewing area data line go between and the second lead-in wire; Wherein said the first lead-in wire comprises the first grid lead-in wire that forms with layer with the grid line of described viewing area and first data cable lead wire that forms with layer with the data line of described viewing area, described first grid lead-in wire and described the first data cable lead wire top are formed with the first via hole and the second via hole, and described first grid lead-in wire and described the first data cable lead wire are by covering the first conductive layer conducting of described the first via hole and the second via hole; Second conductive layer that second data cable lead wire of described the second lead-in wire for forming with layer with the data line of described viewing area, described the second data cable lead wire top are provided with the 3rd via hole and cover described the 3rd via hole and form with layer with described the first conductive layer; Described driving circuit is bundled on first conductive layer and the second conductive layer above the second data cable lead wire of described the first data cable lead wire top.
2. array base palte according to claim 1, it is characterized in that: described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, described the first data cable lead wire and the second data cable lead wire below are respectively arranged with the first insulation course and active layer, and described the first data lead and the second data lead top are provided with the second insulation course.
3. array base palte according to claim 1, it is characterized in that: described first grid lead-in wire top is provided with the first insulation course and the second insulation course successively, described the first data cable lead wire and the second data cable lead wire below are provided with the first insulation course, and described the first data cable lead wire and the second data cable lead wire top are provided with the second insulation course.
4. a display panel is characterized in that, comprises such as the described array base palte of the arbitrary claim of claim 1 ~ 3.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310004002.3A CN103064223B (en) | 2013-01-07 | 2013-01-07 | Array substrate and display panel |
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| CN201310004002.3A CN103064223B (en) | 2013-01-07 | 2013-01-07 | Array substrate and display panel |
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| CN103064223B CN103064223B (en) | 2015-02-11 |
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| CN103680317A (en) * | 2013-12-20 | 2014-03-26 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and displaying device |
| WO2017036110A1 (en) * | 2015-09-01 | 2017-03-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display device |
| CN108231692A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN108493194A (en) * | 2018-03-28 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel |
| CN108663865A (en) * | 2018-07-24 | 2018-10-16 | 武汉华星光电技术有限公司 | Tft array substrate and its manufacturing method and flexible liquid crystal panel |
| CN110133929A (en) * | 2019-06-28 | 2019-08-16 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display module |
| CN111999947A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113316851A (en) * | 2019-11-15 | 2021-08-27 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| WO2022100335A1 (en) * | 2020-11-10 | 2022-05-19 | 京东方科技集团股份有限公司 | Display screen and electronic device |
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| CN103680317A (en) * | 2013-12-20 | 2014-03-26 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method thereof and displaying device |
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| CN113316851B (en) * | 2019-11-15 | 2024-08-27 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN113516910A (en) * | 2020-04-09 | 2021-10-19 | 上海和辉光电有限公司 | Display panel and binding region planarization method thereof |
| CN113516910B (en) * | 2020-04-09 | 2022-09-23 | 上海和辉光电股份有限公司 | Display panel and binding region planarization method thereof |
| CN111999947A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2022100335A1 (en) * | 2020-11-10 | 2022-05-19 | 京东方科技集团股份有限公司 | Display screen and electronic device |
| US11774818B2 (en) | 2020-11-10 | 2023-10-03 | Hefei Boe Optoelectronics Technology Co., Ltd. | Display panel and electronic apparatus |
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| CN103064223B (en) | 2015-02-11 |
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