CN103051487B

CN103051487B - Electrically-based industry network measure and the method for testing of control system clock synchronization protocol

Info

Publication number: CN103051487B
Application number: CN201110310098.7A
Authority: CN
Inventors: 周健; 赵海生; 杨帆; 高彦杰
Original assignee: East China Power Test and Research Institute Co Ltd; Shanghai Minghua Electric Power Technology and Engineering Co Ltd
Current assignee: East China Power Test and Research Institute Co Ltd; Shanghai Minghua Electric Power Technology and Engineering Co Ltd
Priority date: 2011-10-14
Filing date: 2011-10-14
Publication date: 2016-10-05
Anticipated expiration: 2031-10-14
Also published as: CN103051487A

Abstract

The present invention relates to a kind of electrically-based industry network measure and the method for testing of control system clock synchronization protocol, it comprises the following steps: IEEE1588 testing protocol consistency, the test of IEEE1588 protocol hardware markers accuracy and the test of IEEE1588 protocol time synchronous accuracy.IEEE1588 testing protocol consistency includes the test of PTP default property value, the test of path delay mechanism, the test of BMC algorithm data collection comparison algorithm and Determines test of heuristics.The test of path delay mechanism includes test and the test of equity delay strategy ignoring other delay strategy messages.The test of IEEE1588 protocol hardware markers accuracy includes that master clock is measured with transparent clock transmission delay and transparent clock is measured with from clock transmission delay.In the present inventive method, it is possible to resolve the interoperability issue of devices from different manufacturers during power system application IEEE1588 agreement, the actual parameter of available equipment key function, the performance for valuator device provides foundation.

Description

Electrically-based industry network measure and the method for testing of control system clock synchronization protocol

Technical field

The invention belongs to the IEEE1588 protocol test technology of power system, power system various kinds of equipment can be passed through IEEE1588 protocol realization device network time synchronized, by surveying based on IEEE1588 protocol configuration collection (IEEE PC37.238) The IEEE1588 protocol test that method for testing is carried out, energy specification IEEE1588 agreement is in the application of power system.The present invention especially relates to And a kind of electrically-based industry network measure and the method for testing of control system clock synchronization protocol.

Background technology

The full name of IEEEl588 agreement is " the precision interval clock synchronous protocol standard of network measure and control system " (Precision Time Protocol, PTP), Primary Reference Ethernet is worked out, and purpose is for enabling distributed communication network Having strict Timing Synchronization, the typical field of application of IEEE 1588 is that laboratory or product are measured and control system, industry Automatization, power system or telecommunication system and comprise the distribution of multiple sensor, executor, instrument and meter and controller Formula kinetic control system.IEEE 1588 v2 standard was announced in June, 2008, add PTP telecommunications, network, aviation and Application in power system.

IEEE1588 agreement is at config set IEEE PC37.238 for power system defined in second edition standard. IEEE C37.238 standard elaborates, in protecting electrical power system, control, automatization and data transmission applications, to utilize ether Netcom Letter framework, uses the common configuration collection of IEEE 1588-2008 Precision Time Protocol (PTP).Config set describes IEEE in detail 1588-2008 mechanism and the complete subset arranged, its target is to ensure that the interchangeability of device, reply network failure robust respond, And the deterministic control of the temporal quality of transmission, the physical layer (Ethernet) of first-selection is described in detail, and relevant PTP message is handed over Change and parameter higher protocol layer is set with PTP protocol, focus in transformer station, between transformer station and transformer station, and extensively Geographical coverage area in ensure concordance and the reliability of time tranfer.The purpose of this config set is to aid in IEEE1588- 2008 standards are used in power system precise synchronization is applied.

Traditional power system time synchronization test technology is by by the output signal 1PPS(second arteries and veins of time synchronism apparatus Punching), the punching of 1PPM(sectors), IRIG-B(B code) signal such as signal carries out together through 1PPS, 1PPM etc. of oscillograph Yu standard time clock The phase bit comparison in one moment, as shown in Figure 1.

PTP protocol has submicrosecond level synchronization accuracy, and the application in power system is concentrated mainly on digital transformer substation mistake Journey layer equipment combining unit (MU), synchronous phasor measuring device (PMU) etc. require high equipment to time synchronized, are opening at present Exhibition is applied to the research of bay device.

The equipment based on time synchronizing signal sampling principle such as MU, PMU stability, accuracy and reliability to PTP There are the highest requirement, the fluctuation of PTP protocol generation or deviation can cause malfunction and the PMU device of the protection device relevant to MU Sampling deviation, bring impact to power system stability.

The current detection method to PTP protocol is again referring to traditional detection method, as shown in Figure 2.PTP protocol is exported The 1PPS signal of the 1PPS signal of device (master clock) and PTP protocol receiving device (MU or from clock) and standard time clock 1PPS signal carries out phase bit comparison, the 1PPS of PTP protocol receiving device be device clock unit through PTP protocol synchronize after defeated Go out.

Above-mentioned detection method can detect the time synchronized accuracy of PTP protocol the most intuitively, but has following major defect:

For utilizing MU and the PMU device of sampling principle based on pulse per second (PPS), the stability of pulse per second (PPS) is most important, mesh Front method of testing utilizes the output of standard time clock as reference signal, and the problem itself also having shake, so cannot comment well The stability of valency PTP protocol.

Applying of IEEE1588 power system config set IEEE PC37.238 is still in the starting stage in power system, right The difference of this config set understandability determines the difference of device performance, and current method of testing can only be indirect by 1PPS pulse The time synchronized accuracy of ground detection protocol, the details of agreement has no way of holding.

The feature of PTP protocol maximum is to demarcate markers by the markers maker of physical layer, it is achieved merit that hardware " beats markers " Can, eliminate the ms level time delay such as protocol stack and operating system, improve time precision, as it is shown on figure 3, be also based on this, When hardware is beaten, target function determines the performance of PTP protocol, and this function cannot be evaluated by current method of testing.

In view of this, seek a kind of power system IEEE1588 protocol testing method and become the pursuit of this skilled person Target.

Summary of the invention

The task of the present invention is to provide a kind of electrically-based industry network measure and the test of control system clock synchronization protocol Method, by Conventional temporal synchronous detecting method and the improvement of IEEE1588 protocol testing method, it is achieved to meeting electric power Consistency detection and the IEEE1588 agreement of the IEEE1588 protocol configuration collection (IEEE PC37.238) that system application requires are hard The detection of part markers calibration accuracy, IEEE1588 protocol capabilities, the evaluation of function, specification power system are applied by final realization IEEE1588 agreement.

The technical solution of the present invention is as follows:

A kind of electrically-based industry network measure and the method for testing of control system clock synchronization protocol, it includes following step Rapid: IEEE1588 testing protocol consistency, the test of IEEE1588 protocol hardware markers accuracy and IEEE1588 protocol time Synchronous accuracy is tested；

Described IEEE1588 testing protocol consistency include the test of PTP default property value, path delay mechanism test, BMC algorithm-data set comparison algorithm test and Determines test of heuristics；The test of described path delay mechanism includes ignoring it The test of his delay strategy message and the test of equity delay strategy；

The test of described IEEE1588 protocol hardware markers accuracy include master clock and transparent clock transmission delay measure and Transparent clock is measured with from clock transmission delay.

The test of described PTP default property value include portDS.logAnnounceInterval property value test, The test of portDS.logSyncInterval property value, the test of portDS.announceReceiptTimeout property value, The test of τ initial value, the test of portDS.logMinPdelayReqInterval property value, defaultDS.priority1 The test of property value, the test of defaultDS.priority2 property value, the test of defaultDS.slaveOnly property value, The test of defaultDS.domainNumber property value and transparentClockdefaultDS.primaryDomain The test of property value.

Described BMC algorithm-data set comparison algorithm test includes DSC algorithm based on Grandmaster Priority1 Test, DSC test of heuristics based on grandmasterClockQuality.clockClass, based on The DSC test of heuristics of grandmasterQuality.clockAccuracy, based on The DSC test of heuristics of grandmasterCloclQuality.offsetScaledLogVariance, based on Grandmaster The DSC test of heuristics of Priority2 and DSC test of heuristics based on Grandmaster Identity.

Described BMC algorithm-data set comparison algorithm test also includes that test test broadcasting packet is the most qualified, tests data When collection comparison algorithm DSC-II, DUT clock grade are more than or equal to state decision-making SD test of heuristics, a step clock and two steps of 128 MAC Address test in the test of clock pattern, multicast communication mode, support PTP time scale test, clockIdentity form TLVs is specified in test and IEEE 1588 and config set.

When described Determines test of heuristics includes the state decision making algorithm test less than 128 of the DUT clock grade and DUT The clock grade state decision-making SD test of heuristics more than or equal to 128.

Described IEEE1588 testing protocol consistency also includes that dependence test, described dependence test include: MIB test, IEEE Std. 802.1Q and configurable priority and VLAN ID test, a step clock and two step clock modules test, multicast MAC Address test, support PTP time scale test, the test of clockIdentity form and IEEE in communication pattern 1588 and config set appointment TLVs.

Described IEEE1588 protocol hardware markers accuracy method of testing, the P2P transparent clock in PTP protocol synchronizes mould Under formula, have employed sync message Sync altogether, follow message Follow_Up, level latency request message PDelay_Req, level time delay rings Answering message PDelay_Resp, level time delay to follow message PDelay_Resp_Follow_Up accordingly, synchronizing process is as follows:

(1) master clock periodically sends a Sync message to from clock, and this message comprises the time of master clock plan transmission Information, but the deviation between the time sent due to plan and the actual time sending message, the actual transmission time can not be with Sync message sends together, and this sync message is stamped reception markers T2 at receiving terminal from clock；

(2) master clock sends a Follow_Up message to from clock, and this message comprises previous Sync message and sends out accurately Send time T1；

(3) Sync message and Follow_Up message prolong according to level through level-level transparent clock, respective correction territory CF Time request message PDelay_Req, level time delay response message PDelay_Resp, level time delay response follow message PDelay_Resp_ Follow_Up and message pass through the delay that level-the residence time RT of level transparent clock needs calculates to be carried out the most more Newly, revise.

Described master clock is as follows with transparent clock transmission delay measurement method:

(1) port that accepts of level-level transparent clock sends between PDelay_Req message PDelay_Req message to master clock Every being independently arranged, typically should be spaced long by relatively sync message, this message contains the temporal information that transparent clock plan sends T1, is stamped the reception time t2 of this message accurately by master clock；

(2) master clock accepts port one PDelay_Resp message of return to transparent clock, and this message arrives transparent clock The time accepting port is t4；

(3) master clock accepts port one PDelay_Resp_Follow_Up message of transmission, this message to transparent clock again Comprise previous PDelay_Resp message and send time t3 accurately.

Described transparent clock is as follows with from clock transmission delay measurement method:

(1) sending PDelay_Req message from the transmission port of clockwise level-level transparent clock, this message contains from clock Temporal information t5 that plan sends, is stamped the reception time t6 of this message accurately by transmission port；

(2) accepting port and return a PDelay_Resp message to from clock, it is t8 that this message arrived from the time of clock；

(3) accepting port and send a PDelay_Resp_Follow_Up message to from clock again, this message comprises previously PDelay_Resp message send time t7 accurately.

Due to the fact that and have employed above technical scheme, be allowed to compared with prior art, by the electrically-based industry of the present invention Network measure and the method for testing of control system clock synchronization protocol, i.e. power system IEEE1588 protocol testing method, its bag Include three parts: IEEE1588 protocol conformance test method, IEEE1588 agreement " hardware markers " accuracy method of testing, IEEE1588 protocol time synchronous accuracy method of testing.Wherein, IEEE1588 protocol conformance test method achieve right The IEEE1588 power system config set conforming test of IEEE PC37.238, according to grammer, the structure of IEEE1588 agreement, The interoperability issue of devices from different manufacturers during power system application IEEE1588 agreement can be solved；IEEE1588 agreement " hardware Markers " accuracy method of testing achieves the test of IEEE1588 protocol core function, the reality of available equipment key function Parameter, the performance for valuator device provides foundation；IEEE1588 protocol time synchronous accuracy method of testing achieves The evaluation of IEEE1588 agreement application effect, can evaluate all kinds of time synchronized by the equipment of IEEE1588 protocol synchronization accurate Whether degree meets power system application requirement.

Accompanying drawing explanation

Fig. 1 is conventional electric power system time synchronization system test schematic diagram.

Fig. 2 is current PTP protocol test philosophy figure.

Fig. 3 is that PTP protocol markers is demarcated and the difference of agreement during other network pair.

Fig. 4 is PTP-P2P transparent clock synchronous working principle.

Fig. 5 is a kind of electrically-based industry network measure and the method for testing of control system clock synchronization protocol of the present invention Flow chart.

Detailed description of the invention

With embodiment, the present invention is elaborated below in conjunction with the accompanying drawings.

Referring to Fig. 5, the invention provides a kind of electrically-based industry network measure and the survey of control system clock synchronization protocol Method for testing, i.e. a kind of power system IEEE1588 protocol testing method, it comprises the following steps: IEEE1588 protocol conformance is surveyed Examination, the test of IEEE1588 protocol hardware markers accuracy and the test of IEEE1588 protocol time synchronous accuracy.

Described IEEE1588 testing protocol consistency include the test of PTP default property value, path delay mechanism test, BMC algorithm-data set comparison algorithm test and Determines test of heuristics.

The test of described path delay mechanism includes ignoring the test of other delay strategy messages and equity delay strategy Test.

The actually used mode of the present invention is as follows:

One, IEEE1588 protocol conformance test method

The test of PTP default property value

The test of son test 1:portDS.logAnnounceInterval property value

Test purpose: the logAnnounceInterval of checking DUT employs correct initial value.Acquiescence initial value is 0 [1]。

Method of testing:

1. initialize PC clock and DUT.

2. DUT is configured to master clock.

3. PC is configured to from clock.

4. between DUT and PC, set up PTP link.

5. the default value of portDS.logAnnounceInterval is obtained from DUT.

6. catch enough broadcasting packet message intervals to fall with the reliability of 90% 2portDS.logAnnouncelnterval ± 30% interval in.

The test of son test 2:portDS.logSyncInterval property value

Test purpose: checking DUT employs the correct initial value of logSyncInterval.Default value is 0 [1].

Method of testing:

1. initialize PC clock and DUT.

2. DUT is configured to main.

3. PC be configured to from.

4. between DUT and PC, set up PTP link.

5. the default value of portDS.logSyncInterval is obtained from DUT.

6. catch enough sync message message intervals to fall at 2portDS.logSyncInterval with the reliability of 90% ± 30% interval in.

The test of son test 3:portDS.announceReceiptTimeout property value

Test purpose: checking DUT employs correct initial value.Default value is 3 [1].

Method of testing:

1. initialize PC clock and DUT.

2. DUT port be configured to from.

3. the value of portDS.announceReceiptTimeout is obtained from DUT.

4. pc port is configured to main.

5. set up the PTP link between DUT and PC.

6. send broadcasting packet to DUT from PC.

7. confirm that DUT port is from state.

8. stop sending broadcasting packet to DUT.Record PC stops sending broadcasting packet to the time t1 of DUT.

9. observe and record DUT and start to send the time t2 of broadcasting packet.

The test of son test 4: τ initial value

Test purpose: checking DUT employs the correct initial value of τ.Acquiescence initial value is 1 second [1].

Method of testing:

1. DUT is connected with business generator, sets up PTP link, and DUT is set to main.

2. the output of 1PPS is connected to DSO.

3. measure the time between the peak value of 1PPS pulse.

4. for guaranteeing precision, the time between repeated measure pulse per second (PPS) peak value, and be averaged.

The test of son test 5:portDS.logMinPdelayReqInterval property value

Test purpose:

Whether checking level employs the correct initial value of portDS.logMinPdelayReqInterval to stage arrangement.Just Initial value is 0.

Method of testing:

1. initialize PC clock and DUT.

2. DUT port be configured to from.

3. from DUT, obtain the default value of portDS.logMinDelayReqInterval.

4. PC is configured to main.

5. set up the PTP link between DUT and PC.

6. capture enough PDelay_Req messages, with the equispaced between measured message.

The test of son test 6:defaultDS.priority1 property value

Test purpose:

Whether checking DUT employs the correct initial value of defaultDS.priority1.To possessing the highest master clock ability Device default value be 128, be 255 to SLAVE-ONLY device value.

Method of testing:

1. initialize PC clock and DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.priority1.

The test of son test 7:defaultDS.priority2 property value

Test purpose: whether checking DUT employs the correct initial value of defaultDS.priority2.The highest to possessing The device default value of master clock ability is 128, is 255 to SLAVE-ONLY device value.

Method of testing:

1. initialize PC clock and DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.priority2.

The test of son test 8:defaultDS.slaveOnly property value

Test purpose: whether checking DUT employs the correct initial value of defaultDS.slaveOnly. It is false that defaultDS.slaveOnly possesses the device default value of master clock ability, is true to SLAVE-ONLY device value.

Method of testing:

1. initialize DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.slaveOnly.

The test of son test 9:defaultDS.domainNumber property value

Test purpose: whether checking DUT employs the correct initial value of defaultDS.domainNumber.Default value is 0。

The test of son test 10:transparentClockdefaultDS.primaryDomain property value

Test purpose: whether checking DUT is just employing transparentClockdefaultDS.primaryDomain Really initial value.Default value is 0.

Method of testing:

1. initialize DUT.

2. link PC and DUT.

3. obtain the default value of transparentClockDefaultDS.primaryDomain.

Path delay mechanism is tested

Son test 1: ignore the test of other delay strategy messages

Test purpose: whether authenticating peer delay strategy is that the device of application configuration collection IEEE PC37.238 uses only One path delay mechanism [1], postpones request mechanism and is left in the basket.

Method of testing:

1. the default value of portDS.delayMechanism

1.1 initialize PC and DUT.

1.2 set up PTP link between PC and DUT.

1.3. the default value of portDS.delayMechanism is obtained.

1.4 initial values obtaining portDS.peerMeanPathDelay.

2. DUT negligible delay response mechanism

2.1 configuration PC are from clock, and DUT is master clock.

2.2 PC are configured to delayed response mechanism.

2.3 set up PTP link between PC and DUT.

2.4 catch all PTP bags on link.

2.5 values obtaining the portDS.peerMeanPathDelay on DUT.

Son test 2: the test of equity delay strategy

Test purpose: the reciprocity delay strategy used in checking network whether with defined in IEEE 1588-2008 Cause.Equity delay strategy is the exclusive path delay strategy [1] of the device use of application configuration collection IEEE PC37.238.

Method of testing:

Step 1:DUT is as postponing requesting party

1.1 initialize DUT.

1.2 DUT ports are set to major state.

1.3 pc ports are set to from state.

1.4 set up PTP link between PC and DUT.

1.5 PC send sync message to DUT.

The PTP message that 1.6 captures are enough.

1.7 observe and analyze PTP message.

1.8 peerMeanPathDelay obtaining DUT.

Step 2:DUT is as postponing responder

1.1 initialize DUT.

1.2 DUT ports are set to major state.

1.3 pc ports are set to from state.

1.4 set up PTP link between PC and DUT.

The PTP message that 1.5 captures are enough.

1.6 observe and analyze PTP message.

1.7 peerMeanPathDelay obtaining DUT.

BMC algorithm-data set compares (DSC) test of heuristics (part i)

Son test 1: DSC test of heuristics based on Grandmaster Priority1

Purpose: whether checking DUT value based on Grandmaster Priority1 field can select the highest correct master Clock.By the grandmasterPriority1 field in the broadcasting packet of external master clock and local clock DefaultDS.priority1 compares, and has lower value and obtains clock more excellent [1].

Method of testing:

Step 1:A priority < B priority

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical clockClass, clockAccuracy, offsetScaledLogVariance and priority2。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

1.4 configuration A priority < B priority.

1.5 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

Step 2:A priority > B priority

2.1 configuration A priority > B priority.

2.2 PC transmissions 2 or more than 2 broadcasting packets are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Son test 2: DSC test of heuristics based on grandmasterClockQuality.clockClass

Purpose: whether checking DUT can value based on grandmasterClockQuality.clockClass field choosing Select the highest correct master clock.The clock with smaller value is more excellent.

Method of testing:

1. configuration PC(device A) and DUT(device B) there is identical priority1, clockAccuracy, offsetScaledLogVariance and priority2。

2. between PC and DUT, set up PTP link, catch the message between PC and DUT.

3. compare the defaultDS.clockQuality.clockClass field value of A and B.

The clock grade defaultDS.clockQuality.clockClass of step 1:A be < B's defaultDS.clockQuality.clockClass

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical priority1, clockAccuracy, offsetScaledLogVariance and priority2。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

The clock grade defaultDS.clockQuality.clockClass of 1.4 configuration A be < B's defaultDS.clockQuality.clockClass。

1.5 PC transmissions 2 or more than 2 broadcasting packets are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

The clock grade defaultDS.clockQuality.clockClass's > B of step 2:A defaultDS.clockQuality.clockClass

The clock grade defaultDS.clockQuality.clockClass's > B of 2.1 configuration A defaultDS.clockQuality.clockClass。

2.2 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Son test 3: DSC test of heuristics based on grandmasterQuality.clockAccuracy

Purpose: whether checking DUT can value based on grandmasterQuality.clockAccuracy field select The highest correct master clock.Have that the clock of smaller value is more excellent or in topology more excellent [1].

Method of testing:

The clock accuracy defaultDS.clockQuality.clockAccuracy of step 1:A be < B's defaultDS.clockQuality.clockAccuracy

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical priority1, clockClass, offsetScaledLogVariance and priority2。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

The clock grade defaultDS.clockQuality.clockAccuracy of 1.4 configuration A be < B's defaultDS.clockQuality.clockAccuracy。

1.5 PC transmissions 2 or more than 2 broadcasting packets are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

The clock grade defaultDS.clockQuality.clockAccuracy of step 2:A be < B's defaultDS.clockQuality.clockAccuracy

The clock grade defaultDS.clockQuality.clockAccuracy of 2.1 configuration A be < B's defaultDS.clockQuality.clockAccuracy。

2.2 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Son test 4: DSC algorithm based on grandmasterCloclQuality.offsetScaledLogVariance Test

Purpose: whether checking DUT can value based on offsetScaledLogVariance field select correct the highest Master clock.There is the clock more excellent [1] of smaller value.

Method of testing:

The defaultDS.clockQuality.offsetScaledLogVariance of step 1:A be < B's defaultDS.clockQuality.offsetScaledLogVariance

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical priority1, clockClass, clockAccuracy and priority2。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

The defaultDS.clockQuality.offsetScaledLogVariance of 1.4 configuration A be < B's defaultDS.clockQuality.offsetScaledLogVariance。

1.5 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

The defaultDS.clockQuality.offsetScaledLogVariance's of step 2:A > B defaultDS.clockQuality.offsetScaledLogVariance

The defaultDS.clockQuality.offsetScaledLogVariance's > B of 2.1 configuration A defaultDS.clockQuality.offsetScaledLogVariance。

2.2 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Son test 5: DSC test of heuristics based on Grandmaster Priority2

Purpose: whether checking DUT value based on Grandmaster Priority2 field can select the highest correct master Clock.The relatively grandmasterPriority2 field in the broadcasting packet of external master clock and local clock DefaultDS.priority2, has the clock more excellent [1] of smaller value.

Method of testing:

The defaultDS. priority2 of the defaultDS. priority2 < B of step 1:A

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical priority1, clockClass, clockAccuracy, offsetScaledLogVariance。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

The defaultDS. priority2 of the defaultDS. priority2 < B of 1.4 configuration A.

1.5 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

The defaultDS. priority2 of the defaultDS. priority2 > B of step 2:A

The defaultDS. priority2 of the defaultDS. priority2 > B of 2.1 configuration A.

2.2 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Son test 6: DSC test of heuristics based on Grandmaster Identity

Purpose: checking DUT whether can value based on grandmasterIdentity field select correct the highest main time Clock.There is the clock more excellent [1] of smaller value.

Method of testing:

The defaultDS.clockIdentity of the defaultDS.clockIdentity < B of step 1:A

1.1 initialize PC and DUT.

1.2 configuration PC and DUT have identical priority1, clockClass, clockAccuracy, offsetScaledLogVariance, and priority2。

1.3 set up PTP link between PC and DUT, catch the message between PC and DUT.

The defaultDS.clockIdentity of the defaultDS.clockIdentity < B of 1.4 configuration A.

1.5 PC transmissions 2 or above broadcasting packet are to DUT.

Which device 1.6 observe is chosen as the highest master clock.

The defaultDS.clockIdentity of the defaultDS.clockIdentity of step 2:A > B

The defaultDS.clockIdentity of the defaultDS.clockIdentity > B of the A of 2.1 configuration A.

2.2 PC transmissions 2 or more than 2 broadcasting packets are to DUT.

Which device 2.3 observe is chosen as the highest master clock.

Data set comparison algorithm (DSC) test (part ii)

Son test 1: test broadcasting packet is the most qualified

Purpose: the broadcasting packet from external master clock that checking DUT receives is the most qualified.

Method of testing:

DUT is set the most as follows:

defaultDS.priority1 =187

The FOREIGN_MASTER_THRESHOLD=4 second

FOREIGN_MASTER_TIME_WINDOW=2 broadcasting packet time

PC is set the most as follows

defaultDS.priority1=6

PortDS.logAnnounceInterval=0 (1 second)

3. step 1: from the broadcasting packet of DUT port ' r '

1.1 initialize PC and DUT.

1.2 arrange DUT:defaultDS.priority1=187.

1.3 arrange PC:defaultDS.priority1=6 and portDS.logAnnounceInterval=0 (1 second).

1.4 arrange the local port sourcePortIdentity field of the PC port " r " equal to DUT portDS.portIdentity。

1.5 link PC and DUT.

1.6 transmissions 2 or more than 2 broadcasting packets are to DUT.

The state of 1.7 ports " r " observing DUT.

Step 2: the sequenceId field backward of broadcasting packet

2.1 PC clocks preparations 3 or above broadcasting packet are to DUT, and the sequenceId field of broadcasting packet is inverse Sequence.

2.2 link PC and DUT.

2.3 PC send ready broadcasting packet to DUT.

The state of 2.4 ports " r " observing DUT.

Step 3: broadcasting packet is very few in appointed interval

3.1 arrange PC clock, and portDS.logAnnounceInterval=3 (8 seconds).

3.2 transmissions 2 or more than 2 broadcasting packets are to DUT.

The state of 3.3 ports " r " observing DUT.

Step 4: the currentDS.stepRemoved=255 of broadcasting packet

4.1 arrange PC clock, currentDS.stepRemoved=255.

4.2 transmissions 2 or more than 2 broadcasting packets are to DUT.

The state of 4.3 ports " r " observing DUT.

Son test 2: test data set comparison algorithm DSC-II

Purpose: verify when Ebest and Erbest has identical grandmasterIdentity, data set comparison algorithm Whether obtain correct judgement.

Method of testing:

Step 1: test is set up

1.1 configuration PC1 and PC2 are master clock.

1.2 configuration boundary clock DUT are (by being set to defaultDS.priority1 than PC1's from clock The higher value of defaultDS.priority1).

The parentDS data set of 1.3 PC2 and the parentDS data set of PC1 have identical value.

1.4 set up PTP link between PC1 and DUT, set up PTP link, such as Fig. 2 between PC2 and DUT.

1.5 PC1 and PC2 send broadcasting packet A and B respectively to DUT.

The stepsRemoved difference more than 1 of step 2:A and B

2.1 configuration PC1 and PC2 so that the stepsRemoved+1 of the stepsRemoved of A > B, observation DUT port ' r' State.

2.2 configuration PC1 and PC2 so that the stepsRemoved of the stepsRemoved+1 < B of A, observation DUT port ' r' State.

Within the stepsRemoved difference 1 of step 3:A and B

3.1 configuration PC1 and PC2 so that the stepsRemoved of the stepsRemoved of A > B, stepsRemoved of A-stepsRemoved of B|≤1。

3.1.1 configure the sender (sourcePortIdentity of A) of A and B recipient (B's SourcePortIdentity) so that recipient < sender, observe DUT port ' the state of r'.

3.1.2 configure the sender (sourcePortIdentity of A) of A and B recipient (B's SourcePortIdentity) so that recipient > sender, observe DUT port ' the state of r'.

3.2 configuration PC1 and PC2 so that stepsRemoved, the stepsRemoved of of the stepsRemoved < B of A A-stepsRemoved of B|≤1。

3.2.1 configure the sender (sourcePortIdentity of A) of B and A recipient (B's SourcePortIdentity) so that sender < recipient, observe DUT port ' the state of r'.

3.2.2 configure the sender (sourcePortIdentity of A) of B and A recipient (B's SourcePortIdentity) so that sender > recipient, observe DUT port ' the state of r'.

The stepsRemoved of the stepsRemoved=B of step 4:A

The stepsRemoved of the stepsRemoved=B of 4.1 configuration PC1 and PC2, A.

The sender of 4.2 senders (sourcePortIdentity of PC2) configuring A and B be (PC1's SourcePortIdentity) so that the sender side of the A > sender of B, observe DUT port ' the state of r'.

The sender of 4.3 senders (sourcePortIdentity of PC2) configuring A and B be (PC1's SourcePortIdentity) so that the sender side of A < sender of B, observe DUT port ' the state of r'.

The sender of 4.4 senders (sourcePortIdentity of PC2) configuring A and B be (PC1's SourcePortIdentity) so that the sender of the sender=B of A.

Determines (SD) test of heuristics

The state decision making algorithm test less than 128 of the son test 1:DUT clock grade

Purpose: the clock grade of checking DUT is if less than 128, and D0 is better than or well Erbest in topology, then port ' R' is master clock state M1；Otherwise it is in passive PASSIVE state P1 [2].

Method of testing:

The D0 of step 1:DUT is not better than or well Erbest in topology

1.1 initialize DUT and PC.

1.2. the defaultDS.priority1 of the defaultDS.priority1 < DUT of PC is configured.

PTP link is set up between 1.3 DUT and PC.

1.4 PC transmissions 2 or more than 2 broadcasting packets are to DUT.

1.5 port status observing DUT.

The D0 of step 2:DUT is better than or well Erbest in topology

The defaultDS.priority1 of the defaultDS.priority1 > DUT of 2.1 configuration PC.

2.2 PC transmissions 2 or above broadcasting packet are to DUT.

2.3 observe the port status of DUT.

The son test 2:DUT clock grade state decision-making SD test of heuristics more than or equal to 128

Purpose: the clock grade of checking DUT is if greater than 127, and D0 is better than or well Erbest in topology, then port ' R' is master clock state.

Method of testing:

Step 1:Ebest is received from the port ' r ' of DUT

1.1 initialize DUT PC1 and PC2.

The clockClass of 1.2 configuration PC1 and PC2 >=128, such as 193.

1.3 configuration DUT priority1=10.

The priority1 of 1.4 configuration PC1 and PC2 is respectively 20,30.

PTP link is set up, such as Fig. 3-a between 1.5 DUT and PC.

1.6 PC1 and PC2 send broadcasting packets to the port ' r ' of DUT and ' k '.

1.7 port status observing DUT.

Step 2:Ebest is not from the port ' r ' of DUT

2.1 disconnect DUT and PC1, set up PTP link between PC2.

2.2 reinitialize DUT and PC1.

2.3 configuration DUT priority1=10.

The priority1 of 2.4 configuration PC1 is 20.

PTP link is set up, such as Fig. 3-b between 2.5 DUT and PC.

2.6 PC1 send broadcasting packet to the port ' r ' of DUT.

2.7 port status observing DUT.

Dependence test

Son test 1:MIB test

Purpose: the read-write property of checking MIB, and its content comprised is identical with IEEEC37.238 clause 5.5.1.

Method of testing:

1.1 initialize PC and DUT.

1.2 link PC and DUT.

1.3 as required send read or write order to SNMP.

The change of SNMP information contained after 1.4 results observing SNMP inquiry and write order.

Son test 2:IEEE Std. 802.1Q and configurable priority and VLAN ID test

Test purpose: the default value of the VLAN ID of checking (1) Priority field and 802.1Q encapsulation and configurable model Enclose.(2) all devices receive frame, encapsulate with or without 802.1Q.

Method of testing:

The default value of the VLAN ID of step 1:Priority field and 802.1Q encapsulation

1.1 initialize PC and DUT.

1.2 configuration PC are from clock, and DUT is master clock.

1.3 link PC and DUT.

1.4 capture DUT issue the broadcasting packet of PC.

The value of the 1.5 VLAN ID observing Priority field and 802.1Q encapsulation.

The minima of the VLAN ID of step 2:Priority field and 802.1Q encapsulation

2.1 initialize PC and DUT.

2.2 configuration PC are from clock, and DUT is master clock.

2.3 configuration DUT ports are minimum Priority field and VLAN ID.

2.4 capture DUT issue the broadcasting packet of PC.

The value of the 2.5 VLAN ID observing Priority field and 802.1Q encapsulation.

The maximum of the VLAN ID of step 3:Priority field and 802.1Q encapsulation

3.1 initialize PC and DUT.

3.2 configuration PC are from clock, and DUT is master clock.

3.3 configuration DUT ports are maximum Priority field and VLAN ID.

3.4 capture DUT issue the broadcasting packet of PC.

The value of the 3.5 VLAN ID observing Priority field and 802.1Q encapsulation.

Step 4: the PTP frame of different VID value encapsulation

4.1 initialize PC and DUT.

4.2 configuration PC are from clock, and DUT is master clock.

4.3 send the broadcasting packet of 802.1Q encapsulation to DUT.

4.4 port status observing DUT side

4.5 PC send the different broadcasting packet of 802.1Q value to DUT.

4.6 port status observing DUT side

Step 5: do not have the PTP frame that 802.1Q encapsulates

5.1 initialize PC and DUT.

5.2 configuration PC are from clock, and DUT is master clock.

5.3 send the broadcasting packet without 802.1Q encapsulation to DUT.

5.4 port status observing DUT side.

Son test 3: one step clocks and the test of two step clock modules

Test purpose: verify that the access port of whole device should support a step and two step operational modes simultaneously.All devices Exit can support one-step or two-step operational mode.

Method of testing:

Step 1: the input port of step DUT

1.1 initialize PC and DUT.

1.2 PC are configured to a step master clock, and DUT is that a step is from clock.

1.3 PC and DUT are configured to equity delay mechanism.

1.4 link PC and DUT, all PTP messages on acquisition link.

1.5 observe and analyze PTP message.

Step 2: the input port of two steps DUT

2.1 initialize PC and DUT.

2.2 PC are configured to two step master clocks, and DUT is that two steps are from clock.

2.2 PC and DUT are configured to equity delay mechanism.

2.3 link PC and DUT, all PTP messages on acquisition link.

2.4 observe and analyze PTP message.

Step 3: the output port of step DUT

3.1 initialize PC and DUT.

3.2 PC are configured to a step from clock, and DUT is a step master clock.

3.3 PC and DUT are configured to equity delay mechanism.

3.4 link PC and DUT, all PTP messages on acquisition link.

3.5 observe and analyze PTP message.

Step 4: the output port of two steps DUT

4.1 initialize PC and DUT.

4.2 PC are configured to two steps from clock, and DUT is two step master clocks.

4.3 PC and DUT are configured to equity delay mechanism.

4.4 link PC and DUT, all PTP messages on acquisition link.

4.5 observe and analyze PTP message.

Son test 4: the MAC Address test in multicast communication mode

Test purpose: whether authenticating peer delay mechanism message and other PTP operation employ correct MAC Address.

Method of testing:

Step 1: broadcast, the MAC Address of sync message and the MAC Address of the message relevant to equity delay mechanism

1.1 initialize PC and DUT.

1.2 PC are configured to from clock, and DUT is master clock.

1.3 PC and DUT are configured to equity delay mechanism.

1.4 link PC and DUT, all PTP messages on acquisition link.

1.5 observe and analyze the broadcast of capture, the MAC Address of sync message and with equity delay mechanism association message MAC Address.

Step 2: management message and the MAC Address of signaling message

2.1 send management message, and actionField field is GET.

2.2 observe PC send response messages MAC Address.

Son test 5: support the test of PTP time scale

Test purpose: verify whether the highest master clock supports PTP time scale, ordinary clock, boundary clock becomes and the highest Whether master clock is class 6.

Method of testing:

In step 1:timePropertiesDS, the PTPtimescale of acquiescence is arranged

1.1 initialize DUT.

1.2 configuration DUT are master clock.

1.3 PTPtimescale obtaining acquiescence.

1.4 observe default setting.

Step 2: the timePropertiesDS bit in broadcasting packet

2.1 configuration DUT are master clock, and PC is from clock.

PTP link is set up between 2.2 DUT and PC.

The broadcasting packet that 2.3 captures are abundant.

The 2.3 PTPtimescale bits observing the flagField field in broadcasting packet head.

Step 3: the clockClass of the highest master clock

3.1 configuration DUT are master clock.

3.2 clockClass obtaining acquiescence.

3.3 observe default setting.

Son test 6:clockIdentity form test

Test purpose: the value of checking clockIdentity should be based on the EUI-64 on EUI-48.

Method of testing:

1. initialize DUT.

2. link PC and DUT.

3. obtain the clockIdentity value of DUT.

4. observe and analyze 16 hex value of clockIdentity.

Son test 7:IEEE 1588 and config set specify TLVs

Test purpose: checking ORGANIZATION_EXTENSION__IEEE_C37_238 and ALTERNATE_TIME_ OFFSET_INDICATOR TLVs is properly configured and adds after broadcasting packet.

Method of testing:

Step 1: broadcasting packet is from DUT

1. initialize PC and DUT.

1.1 configuration DUT are master clock, and PC is from clock.

PTP link is set up between 1.2 DUT and PC.

1.3 capture abundant broadcasting packet.

1.4 observe broadcasting packet head.

Step 2:DUT receives broadcasting packet

Initialize PC and DUT

2.1 configuration PC make defaultDS.priority1=0.

Configuration DUT makes defaultDS.priority1=10.

PTP link is set up between 2.2 DUT and PC.

2.3 send broadcasting packet, do not have ORGANIZATION_EXTENSION__IEEE_C37_238, additional or the most attached Add ALTERNATE_TIME_OFFSET_INDICATOR TLVs.

2.4 DUT ports.

Two, IEEE1588 agreement " hardware markers " accuracy method of testing

IEEE1588 agreement demarcates markers by the markers maker of physical layer, it is achieved function that hardware " beats markers ", eliminates The ms level time delay such as protocol stack and operating system, compare general network to time agreement software " beat markers " for improve time Between precision, as shown in Figure 3.Evaluate the time precision that IEEE1588 agreement can realize, in fact evaluate IEEE1588 equipment Function that hardware " beats markers ".

As a example by P2P transparent clock synchronous mode in PTP protocol, introduce its synchronization principles, as shown in Figure 4.

In such a mode, have employed sync message (Sync) altogether, follow message (Follow_Up), level latency request message (PDelay_Req), message (PDelay_Resp_ is followed in level time delay response message (PDelay_Resp), level time delay accordingly Follow_Up) these a few class messages, synchronizing process is as follows:

(1) master clock periodically sends a Sync message to from clock, and this message comprises the time of master clock plan transmission Information, but the deviation between the time sent due to plan and the actual time sending message, the actual transmission time can not be with " synchronize " message to send together.This " synchronizes " message and is stamped reception markers T2 at receiving terminal from clock.

(2) master clock sends a Follow_Up message to from clock, and this message comprises previous Sync message and sends out accurately Send time T1.

(3) Sync message and Follow_Up message are through level-level transparent clock, and respective correction territory (CF) is according to level Latency request message (PDelay_Req), message is followed in level time delay response message (PDelay_Resp), level time delay response And the message residence time (RT) that passes through level-level transparent clock and need calculates (PDelay_Resp_Follow_Up) Postpone to update accordingly, revise.

Master clock is as follows with transparent clock transmission delay measurement method:

(1) level-level transparent clock accept port to master clock send PDelay_Req message (PDelay_Req message Interval is independently arranged, typically should relatively sync message interval long), this message contains the time letter that transparent clock plan sends Breath t1, is stamped the reception time t2 of this message accurately by master clock.

(2) master clock accepts port one PDelay_Resp message of return to transparent clock, and this message arrives transparent clock The time accepting port is t4.

Transparent clock is as follows with from clock transmission delay measurement method:

(1) sending PDelay_Req message from the transmission port of clockwise level-level transparent clock, this message contains from clock Temporal information t5 that plan sends, is stamped the reception time t6 of this message accurately by transmission port.

(2) accepting port and return a PDelay_Resp message to from clock, it is t8 that this message arrived from the time of clock.

Thus, obtaining the time deviation (Offset) from clock with master clock is:

Formula 1

Wherein, CFSync Yu CFFollowUp is entering transparent clock (CF ' Sync and CF ' FollowUp) and is going out transparent clock (CF " Sync and CF " FollowUp) is updated according to the transmission delay of master clock-port and port-between clock, and leads The transmission delay that clock accepts port with level-level transparent clock is:

Formula 2

Level-level transparent clock accepts port:

Formula 3

When clock is revised local according to the clock jitter calculated by formula (2) and formula (3) with network transmission delay Between, final realization and master clock.

Understanding from above synchronizing process, the core of IEEE1588 agreement is the mutual of the message containing temporal information, this A little messages mainly include sync message (Sync), follow message (Follow_Up), latency request message (Delay_Req), time delay Response message (PDelay_Resp), level latency request message (PDelay_Req), level time delay response message (PDelay_Resp), Message (PDelay_Resp_Follow_Up) etc. is followed in level time delay response.

The test of IEEE1588 agreement " hardware markers " accuracy is the test to IEEE1588 equipment " hardware markers " ability, This frame message is given in a network while i.e. realizing message analysis by the integration of message analysis software Yu high precision clock The generation time, by the comparison of temporal information contained by this time and this frame message, " during hardware of this IEEE1588 equipment can be detected Mark " function.

Three, IEEE1588 protocol time synchronous accuracy method of testing

Time synchronized accuracy test based on routine and IEEE1588 method of testing are as shown in Figure 1 and Figure 2.

The electrically-based industry network measure of the present invention and the method for testing of control system clock synchronization protocol include three parts: IEEE1588 protocol conformance test method, IEEE1588 agreement " hardware markers " accuracy method of testing, IEEE1588 agreement Time synchronized accuracy method of testing.Wherein, IEEE1588 protocol conformance test method achieves IEEE1588 power train The system config set conforming test of IEEE PC37.238, according to grammer, the structure of IEEE1588 agreement, it is possible to resolve power system The interoperability issue of devices from different manufacturers during application IEEE1588 agreement；IEEE1588 agreement " hardware markers " accuracy is tested Method achieves the test of IEEE1588 protocol core function, and the actual parameter of available equipment key function, for valuator device Performance provide foundation；IEEE1588 protocol time synchronous accuracy method of testing achieves IEEE1588 agreement application effect Evaluating, whether the time synchronized accuracy that can evaluate all kinds of equipment by IEEE1588 protocol synchronization meets power system application Requirement.

Certainly, those skilled in the art in the art are it should be appreciated that above-described embodiment is intended merely to this is described Bright, and be not used as limitation of the invention, as long as in the spirit of the present invention, to the change of above-described embodiment, Modification etc. all will fall within the scope of the claims.

Claims

1. an electrically-based industry network measure and the method for testing of control system clock synchronization protocol, it is characterised in that its bag Include following steps: IEEE1588 testing protocol consistency, IEEE1588 protocol hardware markers accuracy is tested and IEEE1588 Protocol time synchronous accuracy is tested；

Described IEEE1588 testing protocol consistency includes that the test of PTP default property value, the test of path delay mechanism, BMC calculate Method-data set comparison algorithm test and Determines test of heuristics；The test of described path delay mechanism includes that ignoring other prolongs Time mechanism message test and equity delay strategy test；

The test of described IEEE1588 protocol hardware markers accuracy includes that master clock is measured and transparent with transparent clock transmission delay Clock is measured with from clock transmission delay.

Electrically-based industry network measure the most as claimed in claim 1 and the method for testing of control system clock synchronization protocol, its Be characterised by: the test of described PTP default property value include the test of portDS.logAnnounceInterval property value, The test of portDS.logSyncInterval property value, the test of portDS.announceReceiptTimeout property value, The test of τ initial value, the test of portDS.logMinPdelayReqInterval property value, defaultDS.priority1 The test of property value, the test of defaultDS.priority2 property value, the test of defaultDS.slaveOnly property value, The test of defaultDS.domainNumber property value and transparentClockdefaultDS.primaryDomain The test of property value.

Electrically-based industry network measure the most as claimed in claim 1 and the method for testing of control system clock synchronization protocol, its It is characterised by: described BMC algorithm-data set comparison algorithm test includes DSC algorithm based on Grandmaster Priority1 Test, DSC test of heuristics based on grandmasterClockQuality.clockClass, based on The DSC test of heuristics of grandmasterQuality.clockAccuracy, based on The DSC test of heuristics of grandmasterCloclQuality.offsetScaledLogVariance, based on Grandmaster The DSC test of heuristics of Priority2 and DSC test of heuristics based on Grandmaster Identity.

Electrically-based industry network measure the most as claimed in claim 1 and the method for testing of control system clock synchronization protocol, its It is characterised by: described BMC algorithm-data set comparison algorithm test also includes that test test broadcasting packet is the most qualified, tests number According to collection comparison algorithm DSC-II, DUT clock grade state decision-making SD test of heuristics, a step clock and two steps more than or equal to 128 MAC Address test in clock module test, multicast communication mode, support PTP time scale test, clockIdentity lattice TLVs is specified in formula test and IEEE 1588 and config set.

Electrically-based industry network measure the most as claimed in claim 1 and the method for testing of control system clock synchronization protocol, its It is characterised by: described Determines test of heuristics includes the state decision making algorithm test less than 128 of the DUT clock grade and DUT The clock grade state decision-making SD test of heuristics more than or equal to 128.

Electrically-based industry network measure the most as claimed in claim 1 and the method for testing of control system clock synchronization protocol, its It is characterised by: described IEEE1588 testing protocol consistency also includes that dependence test, described dependence test include: MIB test, IEEE Std. 802.1Q and configurable priority and VLAN ID test, a step clock and two step clock modules test, multicast MAC Address test, support PTP time scale test, the test of clockIdentity form and IEEE in communication pattern 1588 and config set appointment TLVs.