CN103051487A

CN103051487A - Test method based on network measurement and control system time synchronous protocol in power industry

Info

Publication number: CN103051487A
Application number: CN2011103100987A
Authority: CN
Inventors: 周健; 赵海生; 杨帆; 高彦杰
Original assignee: East China Power Test and Research Institute Co Ltd; Shanghai Minghua Electric Power Technology and Engineering Co Ltd
Current assignee: East China Power Test and Research Institute Co Ltd; Shanghai Minghua Electric Power Technology and Engineering Co Ltd
Priority date: 2011-10-14
Filing date: 2011-10-14
Publication date: 2013-04-17
Anticipated expiration: 2031-10-14
Also published as: CN103051487B

Abstract

The invention relates to a test method based on network measurement and a control system time synchronous protocol in power industry. The method comprises the following steps of testing IEEE1588 (Institute of Electrical and Electronics Engineers 1588) protocol consistency, testing IEEE1588 protocol hardware time mark accuracy and testing IEEE1588 protocol time synchronization accuracy. The step of testing the IEEE1588 protocol consistency comprises the following steps of testing PTP (Precision Time Protocol) default attribute values, testing a route delay mechanism, testing BMC (best master clock) algorithm-data set comparison algorithm and testing state decision algorithm, wherein the step of testing the route delay mechanism comprises the following steps of testing a report ignoring other delay mechanisms and testing a peer to peer delay mechanism. The step of testing the IEEE1588 protocol hardware time mark accuracy comprises the following steps of measuring master clock and transparent clock transmission delay and measuring transparent clock and slave clock transmission delay. By the method, the problem on interoperability of equipment manufactured by different manufacturers when a power system applies an IEEE1588 protocol can be solved, the actual parameters of key functions of the equipment can be acquired, and basis for evaluating the performances of the equipment is provided.

Description

Method of testing based on electric power industry network measure and control system clock synchronization protocol

Technical field

The invention belongs to the IEEE1588 protocol test technology of electric power system, the electric power system various kinds of equipment can realize the device network time synchronized by the IEEE1588 agreement, by the IEEE1588 protocol test of carrying out based on IEEE1588 protocol configuration collection (IEEE PC37.238) method of testing, energy standard IEEE1588 agreement is in the application of electric power system.The invention particularly relates to a kind of method of testing based on electric power industry network measure and control system clock synchronization protocol.

Background technology

The full name of IEEEl588 agreement is " the precision interval clock synchronous protocol standard of network measure and control system " (Precision Time Protocol, PTP), the main reference Ethernet is worked out, purpose is to make distributed communication network can have strict Timing Synchronization, and the typical field of application of IEEE 1588 is laboratory or product measurement and control system, industrial automation, electric power system or telecommunication system and the Distributed Motion Control System that comprises a plurality of transducers, actuator, instrument and meter and controller.IEEE 1588 v2 standards were announced in June, 2008, had increased the application of PTP in telecommunications, network, aviation and electric power system.

The IEEE1588 agreement has defined the config set IEEE PC37.238 for electric power system in the second edition standard.IEEE C37.238 standard has been set forth in protecting electrical power system, control, automation and data transmission applications, utilizes the ethernet communication framework, uses the common configuration collection of IEEE 1588-2008 Precision Time Protocol (PTP).The complete subset that config set is described IEEE 1588-2008 mechanism in detail and arranged, its target is the interchangeability of assurance device, the response of reply network failure robust, and the certainty of the temporal quality of transmission control, describe first-selected physical layer (Ethernet) in detail, reach more upper-layer protocol layer of relevant PTP message switching and PTP agreement parameters, pay attention in transformer station especially, between transformer station and transformer station, and the consistency and the reliability that guarantee widely time tranfer in the scope of geographic area.The purpose of this config set is to help the IEEE1588-2008 standard to be adopted in the electric power system precise synchronization is used.

Traditional electric power system time synchronized measuring technology is by the output signal 1PPS(pulse per second (PPS) with time synchronism apparatus), 1PPM(divides pulse), the IRIG-B(B code) signal such as signal carries out the phase bit comparison of synchronization through oscilloscope and 1PPS, the 1PPM etc. of standard time clock, as shown in Figure 1.

The PTP agreement has submicrosecond level synchronization accuracy, application in electric power system mainly concentrates on process layer of digitalization transformer substation equipment merge cells (MU), synchronous phasor measuring device (PMU) etc. to the high equipment of time synchronized requirement, is carrying out the research that is applied to bay device at present.

The equipment of the time-based such as MU, PMU synchronizing signal sampling principle has very high requirement to stability, accuracy and the reliability of PTP; the malfunction that the fluctuation that the PTP agreement produces or deviation can cause the protective device relevant with MU and the sampling deviation of PMU device bring impact to power system stability.

At present to the detection method of PTP agreement still with reference to traditional detection method, as shown in Figure 2.The 1PPS signal of the 1PPS signal of the 1PPS signal of PTP agreement output device (master clock) and PTP agreement receiving device (MU or from clock) and standard time clock is carried out the phase bit comparison, and the 1PPS of PTP agreement receiving device is the output of clock unit after the PTP protocol synchronization of device.

Above-mentioned detection method can detect the time synchronized accuracy of PTP agreement comparatively intuitively, but following major defect is arranged:

For the MU and the PMU device that utilize based on the sampling principle of pulse per second (PPS), pulse per second (PPS) stable most important, the output that present method of testing is utilized standard time clock is as reference signal, and itself also has the problem of shake, so can't estimate well the stability of PTP agreement.

The electric power system that is applied in of IEEE1588 electric power system config set IEEE PC37.238 still is in the starting stage, the difference of this config set understandability has been determined the difference of device performance, present method of testing can only be by the time synchronized accuracy of the interpulse ground connection detection protocol of 1PPS, and the details of agreement has no way of holding.

The characteristics of PTP agreement maximum are to demarcate markers by the markers maker of physical layer, function that realization hardware " is beaten markers ", the ms level time-delays such as protocol stack and operating system have been eliminated, improved time precision, as shown in Figure 3, also just be based on this, the target function had determined the performance of PTP agreement when hardware was beaten, and present method of testing can't be estimated this function.

In view of this, seek a kind of electric power system IEEE1588 protocol testing method and become pursuing a goal of these those skilled in the art.

Summary of the invention

Task of the present invention provides a kind of method of testing based on electric power industry network measure and control system clock synchronization protocol, by the improvement to traditional time synchronized method of testing and IEEE1588 protocol testing method, realization is to the consistency detection of the IEEE1588 protocol configuration collection (IEEE PC37.238) that satisfies the electric power system application requirements and the detection of IEEE1588 agreement hardware markers calibration accuracy, the final evaluation that realizes IEEE1588 protocol capabilities, function, the IEEE1588 agreement is used in the standard electric power system.

Technical solution of the present invention is as follows:

A kind of method of testing based on electric power industry network measure and control system clock synchronization protocol, it may further comprise the steps: IEEE1588 testing protocol consistency, the test of IEEE1588 agreement hardware markers accuracy and the test of IEEE1588 agreement time synchronized accuracy;

Described IEEE1588 testing protocol consistency comprises test, the test of path delay mechanism, the BMC algorithm-test of data set comparison algorithm and the Determines test of heuristics of PTP default property value; The test of described path delay mechanism comprises the test of ignoring other delay strategy messages and the test of reciprocity delay strategy;

The test of described IEEE1588 agreement hardware markers accuracy comprises master clock and the measurement of transparent clock transmission delay and transparent clock and measures from the clock transmission delay.

The test of described PTP default property value comprises the test of portDS.logAnnounceInterval property value, the test of portDS.logSyncInterval property value, the test of portDS.announceReceiptTimeout property value, the test of τ initial value, the test of portDS.logMinPdelayReqInterval property value, the test of defaultDS.priority1 property value, the test of defaultDS.priority2 property value, the test of defaultDS.slaveOnly property value, the test of the test of defaultDS.domainNumber property value and transparentClockdefaultDS.primaryDomain property value.

Described BMC algorithm-data set comparison algorithm test comprises the DSC test of heuristics based on Grandmaster Priority1, DSC test of heuristics based on grandmasterClockQuality.clockClass, DSC test of heuristics based on grandmasterQuality.clockAccuracy, DSC test of heuristics based on grandmasterCloclQuality.offsetScaledLogVariance, based on the DSC test of heuristics of Grandmaster Priority2 and based on the DSC test of heuristics of Grandmaster Identity.

The test of described BMC algorithm-data set comparison algorithm comprises also whether test test broadcasting packet qualified, test data set comparison algorithm DSC-II, DUT clock grade more than or equal to 128 state decision-making SD test of heuristics, a step clock and the clock modules test of two steps, in the multi-casting communication pattern the MAC Address test, support the test of PTP time scale, the test of clockIdentity form and IEEE 1588 and config set to specify TLVs.

Described Determines test of heuristics comprise the DUT clock grade less than the test of 128 state decision making algorithm and DUT clock grade more than or equal to 128 state decision-making SD test of heuristics.

Described IEEE1588 testing protocol consistency also comprises dependence test, and described dependence test comprises: the MAC Address test in MIB test, IEEE Std. 802.1Q and configurable priority and VLAN ID test, a step clock and the clock modules test of two steps, the multi-casting communication pattern, support the test of PTP time scale, the test of clockIdentity form and IEEE 1588 and config set to specify TLVs.

Described IEEE1588 agreement hardware markers accuracy method of testing, under the P2P transparent clock synchronous mode in the PTP agreement, adopted altogether sync message Sync, follow message Follow_Up, level time-delay request message PDelay_Req, level time-delay response message PDelay_Resp, the corresponding message PDelay_Resp_Follow_Up that follows of level time-delay, synchronizing process is as follows:

(1) master clock is periodically to sending a Sync message from clock, this message comprises the information of the time of master clock plan transmission, but because the deviation between the time of the time that plan sends and actual transmission message, actual transmitting time can not send with synchronous message, and this sync message is stamped from clock at receiving terminal receives markers T2;

(2) master clock is to sending a Follow_Up message from clock, and this message comprises accurately transmitting time T1 of previous Sync message;

When (3) Sync message and Follow_Up message are through level-level transparent clock, correction territory CF separately is according to level time-delay request message PDelay_Req, and level time-delay response message PDelay_Resp, level time-delay response are followed the delay that residence time RT that message PDelay_Resp_Follow_Up and message pass through level-level transparent clock and need calculates and upgraded accordingly, revise.

Described master clock and transparent clock transmission delay measurement method are as follows:

(1) port of accepting of level-level transparent clock is independent the setting to the interval that master clock sends PDelay_Req message PDelay_Req message, generally should be long than the sync message interval, this message contains the temporal information t1 that the transparent clock plan sends, and stamps the accurately time of reception t2 of this message by master clock;

(2) master clock is accepted port to transparent clock and is returned a PDelay_Resp message, and the time that this message arrival transparent clock is accepted port is t4;

(3) master clock is accepted port to transparent clock again and is sent a PDelay_Resp_Follow_Up message, and this message comprises accurately transmitting time t3 of previous PDelay_Resp message.

Described transparent clock is with as follows from the clock transmission delay measurement method:

(1) transmit port from clockwise level-level transparent clock sends the PDelay_Req message, and this message contains the temporal information t5 that sends from the clock plan, stamps the accurately time of reception t6 of this message by transmit port;

(2) accept port to returning a PDelay_Resp message from clock, this message arrive from the time of clock be t8;

(3) accept port again to sending a PDelay_Resp_Follow_Up message from clock, this message comprises accurately transmitting time t7 of previous PDelay_Resp message.

The present invention is owing to having adopted above technical scheme, make it compared with prior art, by the method for testing based on electric power industry network measure and control system clock synchronization protocol of the present invention, be electric power system IEEE1588 protocol testing method, it comprises three parts: IEEE1588 protocol conformance test method, IEEE1588 agreement " hardware markers " accuracy method of testing, IEEE1588 agreement time synchronized accuracy method of testing.Wherein, the IEEE1588 protocol conformance test method has been realized the conforming test to IEEE1588 electric power system config set IEEE PC37.238, according to grammer, the structure of IEEE1588 agreement, the interoperability issue of devices from different manufacturers in the time of can solving electric power system application IEEE1588 agreement; IEEE1588 agreement " hardware markers " accuracy method of testing has realized the test of IEEE1588 protocol core function, can obtain the actual parameter of equipment key function, for the performance of valuator device provides foundation; IEEE1588 agreement time synchronized accuracy method of testing has realized the evaluation of IEEE1588 protocol application effect, and whether the time synchronized accuracy that can estimate all kinds of equipment by the IEEE1588 protocol synchronization satisfies the electric power system application requirements.

Description of drawings

Fig. 1 is conventional electric power system time synchro system test philosophy figure.

Fig. 2 is present PTP protocol test schematic diagram.

Fig. 3 be PTP agreement markers demarcate with other network to the time agreement difference.

Fig. 4 is PTP-P2P transparent clock synchronous working principle.

Fig. 5 is the flow chart of a kind of method of testing based on the network measure of electric power industry and control system clock synchronization protocol of the present invention.

Embodiment

Below in conjunction with drawings and Examples the present invention is elaborated.

Referring to Fig. 5, the invention provides a kind of method of testing based on electric power industry network measure and control system clock synchronization protocol, it is a kind of electric power system IEEE1588 protocol testing method, it may further comprise the steps: IEEE1588 testing protocol consistency, the test of IEEE1588 agreement hardware markers accuracy and the test of IEEE1588 agreement time synchronized accuracy.

Described IEEE1588 testing protocol consistency comprises test, the test of path delay mechanism, the BMC algorithm-test of data set comparison algorithm and the Determines test of heuristics of PTP default property value.

The test of described path delay mechanism comprises the test of ignoring other delay strategy messages and the test of reciprocity delay strategy.

Actual occupation mode of the present invention is as follows:

One, IEEE1588 protocol conformance test method

The test of PTP default property value

The test of son test 1:portDS.logAnnounceInterval property value

Test purpose: the logAnnounceInterval of checking DUT has used correct initial value.The acquiescence initial value is 0[1].

Method of testing:

1. initialization PC clock and DUT.

2. DUT is configured to master clock.

3. PC is configured to from clock.

4. between DUT and PC, set up the PTP link.

5. obtain the default value of portDS.logAnnounceInterval from DUT.

6. catch enough broadcasting packet message intervals with 90% reliability drop on 2portDS.logAnnouncelnterval ± 30% interval in.

The test of son test 2:portDS.logSyncInterval property value

Test purpose: checking DUT has used the correct initial value of logSyncInterval.Default value is 0[1].

Method of testing:

1. initialization PC clock and DUT.

2. DUT is configured to main.

PC be configured to from.

4. between DUT and PC, set up the PTP link.

5. obtain the default value of portDS.logSyncInterval from DUT.

6. catch enough sync message message intervals with 90% reliability drop on 2portDS.logSyncInterval ± 30% interval in.

The test of son test 3:portDS.announceReceiptTimeout property value

Test purpose: checking DUT has used correct initial value.Default value is 3[1].

Method of testing:

1. initialization PC clock and DUT.

The DUT port arrangement be from.

3. obtain the value of portDS.announceReceiptTimeout from DUT.

4. pc port is configured to main.

5. set up the PTP link between DUT and PC.

6. send broadcasting packet to DUT from PC.

7. confirm that the DUT port is from state.

8. stop to send broadcasting packet to DUT.Record PC stops to send broadcasting packet to the time t1 of DUT.

9. observe and record the time t2 that DUT begins to send broadcasting packet.

Son test 4: the test of τ initial value

Test purpose: checking DUT has used the correct initial value of τ.The acquiescence initial value is 1 second [1].

Method of testing:

1. DUT is linked to each other with professional generator, set up the PTP link, and DUT is set to the master.

2. the output with 1PPS is connected to DSO.

3. measure the time between the peak value of 1PPS pulse.

4. for guaranteeing precision, the time between duplicate measurements pulse per second (PPS) peak value, and average.

The test of son test 5:portDS.logMinPdelayReqInterval property value

Test purpose:

Whether the checking level has used the correct initial value of portDS.logMinPdelayReqInterval to stage arrangement.Initial value is 0.

Method of testing:

1. initialization PC clock and DUT.

The DUT port arrangement be from.

3. from DUT, obtain the default value of portDS.logMinDelayReqInterval.

4. PC is configured to main.

5. set up the PTP link between DUT and PC.

6. catch enough PDelay_Req messages, with the equispaced between measured message.

The test of son test 6:defaultDS.priority1 property value

Test purpose:

Whether checking DUT has used the correct initial value of defaultDS.priority1.Being 128 to the device default value that possesses the highest master clock ability, is 255 to SLAVE-ONLY device value.

Method of testing:

1. initialization PC clock and DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.priority1.

The test of son test 7:defaultDS.priority2 property value

Test purpose: whether checking DUT has used the correct initial value of defaultDS.priority2.Being 128 to the device default value that possesses the highest master clock ability, is 255 to SLAVE-ONLY device value.

Method of testing:

1. initialization PC clock and DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.priority2.

The test of son test 8:defaultDS.slaveOnly property value

Test purpose: whether checking DUT has used the correct initial value of defaultDS.slaveOnly.The device default value that defaultDS.slaveOnly possesses the master clock ability is false, is true to SLAVE-ONLY device value.

Method of testing:

1. initialization DUT.

2. link PC and DUT.

3. obtain the default value of defaultDS.slaveOnly.

The test of son test 9:defaultDS.domainNumber property value

Test purpose: whether checking DUT has used the correct initial value of defaultDS.domainNumber.Default value is 0.

The test of son test 10:transparentClockdefaultDS.primaryDomain property value

Test purpose: whether checking DUT has used the correct initial value of transparentClockdefaultDS.primaryDomain.Default value is 0.

Method of testing:

1. initialization DUT.

2. link PC and DUT.

3. obtain the default value of transparentClockDefaultDS.primaryDomain.

The test of path delay mechanism

Son test 1: ignore the test of other delay strategy messages

Test purpose: whether the authenticating peer delay strategy uses unique path delay mechanism [1] of the device use of config set IEEE PC37.238, postpones request mechanism and is left in the basket.

Method of testing:

1. the default value of portDS.delayMechanism

1.1 initialization PC and DUT.

1.2 between PC and DUT, set up the PTP link.

1.3. obtain the default value of portDS.delayMechanism.

1.4 obtain the initial value of portDS.peerMeanPathDelay.

2. DUT negligible delay response mechanism

2.1 configuration PC is from clock, DUT is master clock.

2.2 PC is configured to delayed response mechanism.

2.3 between PC and DUT, set up the PTP link.

2.4 all PTP bags on the seizure link.

2.5 obtain the value of the portDS.peerMeanPathDelay on the DUT.

Son test 2: the test of reciprocity delay strategy

Test purpose: the reciprocity delay strategy that checking is used in the network whether with IEEE 1588-2008 in define consistent.The equity delay strategy is unique path delay mechanism [1] of using the device use of config set IEEE PC37.238.

Method of testing:

Step 1:DUT is as postponing the requesting party

1.1 initialization DUT.

1.2 the DUT port is set to major state.

1.3 pc port is set to from state.

1.4 between PC and DUT, set up the PTP link.

1.5 PC sends sync message to DUT.

1.6 catch enough PTP messages.

1.7 observation and analysis PTP message.

1.8 obtain the peerMeanPathDelay of DUT.

Step 2:DUT is as delayed response side

1.1 initialization DUT.

1.2 the DUT port is set to major state.

1.3 pc port is set to from state.

1.4 between PC and DUT, set up the PTP link.

1.5 catch enough PTP messages.

1.6 observation and analysis PTP message.

1.7 obtain the peerMeanPathDelay of DUT.

BMC algorithm-data set is (DSC) test of heuristics (part i) relatively

Son test 1: based on the DSC test of heuristics of Grandmaster Priority1

Purpose: whether checking DUT can select the highest correct master clock based on the value of Grandmaster Priority1 field.The defaultDS.priority1 of the grandmasterPriority1 field in the broadcasting packet of outside master clock and local clock is compared, have lower value and get clock more excellent [1].

Method of testing:

Step 1:A priority＜B priority

1.1 initialization PC and DUT.

1.2 configuration PC has identical clockClass with DUT, clockAccuracy, offsetScaledLogVariance and priority2.

1.3 between PC and DUT, set up the PTP link, catch the message between PC and DUT.

1.4 configuration A priority＜B priority.

1.5 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

Step 2:A priority〉B priority

2.1 configuration A priority〉B priority.

2.2 2 of PC transmissions or 2 above broadcasting packets are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Son test 2: based on the DSC test of heuristics of grandmasterClockQuality.clockClass

Purpose: whether checking DUT can select the highest correct master clock based on the value of grandmasterClockQuality.clockClass field.Clock with smaller value is more excellent.

Method of testing:

1. configuration PC(device A) with DUT(device B) identical priority1 is arranged, clockAccuracy, offsetScaledLogVariance and priority2.

2. between PC and DUT, set up the PTP link, catch the message between PC and DUT.

3. the defaultDS.clockQuality.clockClass field value that compares A and B.

The defaultDS.clockQuality.clockClass of clock grade defaultDS.clockQuality.clockClass＜B of step 1:A

1.1 initialization PC and DUT.

1.2 configuration PC has identical priority1 with DUT, clockAccuracy, offsetScaledLogVariance and priority2.

1.4 the defaultDS.clockQuality.clockClass of clock grade defaultDS.clockQuality.clockClass＜B of configuration A.

1.5 2 of PC transmissions or 2 above broadcasting packets are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

The clock grade defaultDS.clockQuality.clockClass of step 2:A〉defaultDS.clockQuality.clockClass of B

2.1 the clock grade defaultDS.clockQuality.clockClass of configuration A〉defaultDS.clockQuality.clockClass of B.

2.2 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Son test 3: based on the DSC test of heuristics of grandmasterQuality.clockAccuracy

Purpose: whether checking DUT can select the highest correct master clock based on the value of grandmasterQuality.clockAccuracy field.Have the clock of smaller value more excellent or topological more excellent [1].

Method of testing:

The defaultDS.clockQuality.clockAccuracy of clock accuracy defaultDS.clockQuality.clockAccuracy＜B of step 1:A

1.1 initialization PC and DUT.

1.2 configuration PC has identical priority1 with DUT, clockClass, offsetScaledLogVariance and priority2.

1.4 the defaultDS.clockQuality.clockAccuracy of clock grade defaultDS.clockQuality.clockAccuracy＜B of configuration A.

1.5 2 of PC transmissions or 2 above broadcasting packets are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

The defaultDS.clockQuality.clockAccuracy of clock grade defaultDS.clockQuality.clockAccuracy＜B of step 2:A

2.1 the defaultDS.clockQuality.clockAccuracy of clock grade defaultDS.clockQuality.clockAccuracy＜B of configuration A.

2.2 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Son test 4: based on the DSC test of heuristics of grandmasterCloclQuality.offsetScaledLogVariance

Purpose: whether checking DUT can select the highest correct master clock based on the value of offsetScaledLogVariance field.Clock more excellent [1] with smaller value.

Method of testing:

The defaultDS.clockQuality.offsetScaledLogVariance of defaultDS.clockQuality.offsetScaledLogVariance＜B of step 1:A

1.1 initialization PC and DUT.

1.2 configuration PC has identical priority1 with DUT, clockClass, clockAccuracy and priority2.

1.4 the defaultDS.clockQuality.offsetScaledLogVariance of defaultDS.clockQuality.offsetScaledLogVariance＜B of configuration A.

1.5 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

The defaultDS.clockQuality.offsetScaledLogVariance of step 2:A〉defaultDS.clockQuality.offsetScaledLogVariance of B

2.1 the defaultDS.clockQuality.offsetScaledLogVariance of configuration A〉defaultDS.clockQuality.offsetScaledLogVariance of B.

2.2 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Son test 5: based on the DSC test of heuristics of Grandmaster Priority2

Purpose: whether checking DUT can select the highest correct master clock based on the value of Grandmaster Priority2 field.GrandmasterPriority2 field in the broadcasting packet of outside master clock and the defaultDS.priority2 of local clock have the clock more excellent [1] of smaller value.

Method of testing:

The defaultDS. priority2 of defaultDS. priority2＜B of step 1:A

1.1 initialization PC and DUT.

1.2 configuration PC has identical priority1, clockClass, clockAccuracy, offsetScaledLogVariance with DUT.

1.4 the defaultDS. priority2 of defaultDS. priority2＜B of configuration A.

1.5 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

The defaultDS. priority2 of step 2:A〉the defaultDS. priority2 of B

2.1 the defaultDS. priority2 of configuration A〉the defaultDS. priority2 of B.

2.2 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Son test 6: based on the DSC test of heuristics of Grandmaster Identity

Purpose: whether checking DUT can select the highest correct master clock based on the value of grandmasterIdentity field.Clock more excellent [1] with smaller value.

Method of testing:

The defaultDS.clockIdentity of defaultDS.clockIdentity＜B of step 1:A

1.1 initialization PC and DUT.

1.2 configuration PC has identical priority1 with DUT, clockClass, clockAccuracy, offsetScaledLogVariance, and priority2.

1.4 the defaultDS.clockIdentity of defaultDS.clockIdentity＜B of configuration A.

1.5 2 of PC transmissions or above broadcasting packet are to DUT.

Be chosen as the highest master clock 1.6 observe which device.

The defaultDS.clockIdentity of step 2:A〉defaultDS.clockIdentity of B

2.1 the defaultDS.clockIdentity of A of configuration A〉defaultDS.clockIdentity of B.

2.2 2 of PC transmissions or 2 above broadcasting packets are to DUT.

Be chosen as the highest master clock 2.3 observe which device.

Data set comparison algorithm (DSC) test (part ii)

Son test 1: whether the test broadcasting packet is qualified

Purpose: whether the broadcasting packet from outside master clock that checking DUT receives is qualified.

Method of testing:

1. the following DUT that arranges:

defaultDS.priority1?=187

FOREIGN_MASTER_THRESHOLD=4 second

FOREIGN_MASTER_TIME_WINDOW=2 broadcasting packet time

2. the following PC that arranges

defaultDS.priority1=6

PortDS.logAnnounceInterval=0 (1 second)

3. step 1: from the broadcasting packet of DUT port ' r '

1.1 initialization PC and DUT.

1.2 DUT:defaultDS.priority1=187 is set.

1.3 PC:defaultDS.priority1=6 and portDS.logAnnounceInterval=0 (1 second) are set.

1.4 the portDS.portIdentity that the local port sourcePortIdentity field of PC equals the port " r " of DUT is set.

1.5 link PC and DUT.

1.6 send 2 or 2 above broadcasting packets to DUT.

1.7 observe the state of the port " r " of DUT.

Step 2: the sequenceId field backward of broadcasting packet

2.1 3 of PC clock preparations or above broadcasting packet are to DUT, and the sequenceId field of broadcasting packet is backward.

2.2 link PC and DUT.

2.3 PC sends ready broadcasting packet to DUT.

2.4 observe the state of the port " r " of DUT.

Step 3: broadcasting packet is very few in appointed interval

3.1 the PC clock is set, and portDS.logAnnounceInterval=3 (8 seconds).

3.2 send 2 or 2 above broadcasting packets to DUT.

3.3 observe the state of the port " r " of DUT.

Step 4: the currentDS.stepRemoved=255 of broadcasting packet

4.1 the PC clock is set, currentDS.stepRemoved=255.

4.2 send 2 or 2 above broadcasting packets to DUT.

4.3 observe the state of the port " r " of DUT.

Son test 2: test data set comparison algorithm DSC-II

Purpose: checking is when Ebest and Erbest have identical grandmasterIdentity, and whether the data set comparison algorithm obtains correct judgement.

Method of testing:

Step 1: test is set up

1.1 configuration PC1 and PC2 are master clock.

1.2 configure boundaries clock DUT is from clock (being set to the value higher than the defaultDS.priority1 of PC1 by defaultDS.priority1).

1.3 the parentDS data set of PC2 and the parentDS data set of PC1 have identical value.

1.4 between PC1 and DUT, set up the PTP link, between PC2 and DUT, set up the PTP link, such as Fig. 2.

1.5 PC1 and PC2 send respectively broadcasting packet A and B to DUT.

The stepsRemoved of step 2:A and B differs more than 1

2.1 configuration PC1 and PC2 are so that the stepsRemoved of A〉stepsRemoved+1 of B, observe the DUT port ' the state of r'.

2.2 configuration PC1 and PC2 so that the stepsRemoved of stepsRemoved+1＜B of A, observe the DUT port ' the state of r'.

The stepsRemoved of step 3:A and B differs in 1

3.1 configuration PC1 and PC2 are so that the stepsRemoved of A〉stepsRemoved of B, stepsRemoved of A-stepsRemoved of B|≤1.

3.1.1 the configuration transmit leg (sourcePortIdentity of A) of A and the recipient (sourcePortIdentity of B) of B, so that recipient＜transmit leg, observation DUT port ' the state of r'.

3.1.2 the configuration transmit leg (sourcePortIdentity of A) of A and the recipient (sourcePortIdentity of B) of B are so that the recipient〉transmit leg, observation DUT port ' the state of r'.

3.2 configuration PC1 and PC2, so that the stepsRemoved of stepsRemoved＜B of A, stepsRemoved of A-stepsRemoved of B|≤1.

3.2.1 the configuration transmit leg (sourcePortIdentity of A) of B and the recipient (sourcePortIdentity of B) of A, so that transmit leg＜recipient, observation DUT port ' the state of r'.

3.2.2 the configuration transmit leg (sourcePortIdentity of A) of B and the recipient (sourcePortIdentity of B) of A are so that transmit leg〉recipient, observation DUT port ' the state of r'.

The stepsRemoved of the stepsRemoved=B of step 4:A

4.1 configuration PC1 and PC2, the stepsRemoved of the stepsRemoved=B of A.

4.2 the configuration transmit leg (sourcePortIdentity of PC2) of A and the transmit leg (sourcePortIdentity of PC1) of B are so that the transmit leg side of A〉transmit leg of B, observation DUT port ' the state of r'.

4.3 the configuration transmit leg (sourcePortIdentity of PC2) of A and the transmit leg (sourcePortIdentity of PC1) of B, so that the transmit leg of the transmit leg side of A＜B, observation DUT port ' the state of r'.

4.4 the transmit leg (sourcePortIdentity of PC2) of configuration A and the transmit leg (sourcePortIdentity of PC1) of B are so that the transmit leg of transmit leg=B of A.

Determines (SD) test of heuristics

Son test 1:DUT clock grade is tested less than 128 state decision making algorithm

Purpose: if the clock grade of checking DUT is better than less than 128, D0 or at the well Erbest of topology, then port ' r' is master clock state M1; Otherwise be in passive PASSIVE state P1[2].

Method of testing:

The D0 of step 1:DUT is not better than or at the well Erbest of topology

1.1 initialization DUT and PC.

1.2. the defaultDS.priority1 of defaultDS.priority1＜DUT of configuration PC.

1.3 set up the PTP link between DUT and the PC.

1.4 2 of PC transmissions or 2 above broadcasting packets are to DUT.

1.5 observe the port status of DUT.

The D0 of step 2:DUT is better than or at the well Erbest of topology

2.1 the defaultDS.priority1 of configuration PC〉defaultDS.priority1 of DUT.

2.2 2 of PC transmissions or above broadcasting packet are to DUT.

2.3 observe the port status of DUT.

Son test 2:DUT clock grade is more than or equal to 128 state decision-making SD test of heuristics

Purpose: if the clock grade of checking DUT is better than greater than 127, D0 or at the well Erbest of topology, then port ' r' is the master clock state.

Method of testing:

Step 1:Ebest is received from the port ' r ' of DUT

1.1 initialization DUT PC1 and PC2.

1.2 the clockClass of configuration PC1 and PC2 〉=128, such as 193.

1.3 configuration DUT priority1=10.

1.4 the priority1 of configuration PC1 and PC2 is respectively 20,30.

1.5 set up the PTP link between DUT and the PC, such as Fig. 3-a.

1.6 PC1 and PC2 send broadcasting packet to port ' r ' and ' k ' of DUT.

1.7 observe the port status of DUT.

Step 2:Ebest is not from the port ' r ' of DUT

2.1 disconnect DUT and PC1, set up the PTP link between the PC2.

2.2 reinitialize DUT and PC1.

2.3 configuration DUT priority1=10.

2.4 the priority1 of configuration PC1 is 20.

2.5 set up the PTP link between DUT and the PC, such as Fig. 3-b.

2.6 PC1 sends broadcasting packet to the port ' r ' of DUT.

2.7 observe the port status of DUT.

Dependence test

Son test 1:MIB test

Purpose: the read-write property of checking MIB, and its content that comprises is identical with IEEEC37.238 clause 5.5.1.

Method of testing:

1.1 initialization PC and DUT.

1.2 link PC and DUT.

1.3 send as required and read or write order to SNMP.

1.4 the variation of the contained information of SNMP behind the result of observation SNMP inquiry and the write order.

Son test 2:IEEE Std. 802.1Q and configurable priority and VLAN ID test

Test purpose: default value and the configurable range of the VLAN ID of checking (1) Priority field and 802.1Q encapsulation.(2) no matter whether all device received frames have the 802.1Q encapsulation.

Method of testing:

The default value of the VLAN ID of step 1:Priority field and 802.1Q encapsulation

1.1 initialization PC and DUT.

1.2 configuration PC is from clock, DUT is master clock.

1.3 link PC and DUT.

1.4 catch the broadcasting packet that DUT issues PC.

1.5 observe the value of the VLAN ID of Priority field and 802.1Q encapsulation.

The minimum value of the VLAN ID of step 2:Priority field and 802.1Q encapsulation

2.1 initialization PC and DUT.

2.2 configuration PC is from clock, DUT is master clock.

2.3 configuration DUT port is minimum Priority field and VLAN ID.

2.4 catch the broadcasting packet that DUT issues PC.

2.5 observe the value of the VLAN ID of Priority field and 802.1Q encapsulation.

The maximum of the VLAN ID of step 3:Priority field and 802.1Q encapsulation

3.1 initialization PC and DUT.

3.2 configuration PC is from clock, DUT is master clock.

3.3 configuration DUT port is maximum Priority field and VLAN ID.

3.4 catch the broadcasting packet that DUT issues PC.

3.5 observe the value of the VLAN ID of Priority field and 802.1Q encapsulation.

Step 4: the PTP frame of different VID value encapsulation

4.1 initialization PC and DUT.

4.2 configuration PC is from clock, DUT is master clock.

4.3 send the broadcasting packet of 802.1Q encapsulation to DUT.

4.4 observe the port status of DUT side

4.5 PC sends the different broadcasting packet of 802.1Q value to DUT.

4.6 observe the port status of DUT side

Step 5: the PTP frame that does not have the 802.1Q encapsulation

5.1 initialization PC and DUT.

5.2 configuration PC is from clock, DUT is master clock.

5.3 send broadcasting packet without the 802.1Q encapsulation to DUT.

5.4 observe the port status of DUT side.

Son test 3: one steps clock and the clock module test of two steps

Test purpose: the checking all access port of device should be supported a step and two step operational modes simultaneously.All a step or two step operational modes can be supported in the exit of device.

Method of testing:

Step 1: the input port of a step DUT

1.1 initialization PC and DUT.

1.2 PC is configured to a step master clock, DUT is that a step is from clock.

1.3 PC and DUT are configured to reciprocity delay mechanism.

1.4 link PC and DUT, all the PTP messages on the acquisition link.

1.5 observation and analysis PTP message.

Step 2: the input port of two step DUT

2.1 initialization PC and DUT.

2.2 PC is configured to two step master clocks, DUT is that two steps are from clock.

2.2 PC and DUT are configured to reciprocity delay mechanism.

2.3 link PC and DUT, all the PTP messages on the acquisition link.

2.4 observation and analysis PTP message.

Step 3: the output port of a step DUT

3.1 initialization PC and DUT.

3.2 PC is configured to a step from clock, DUT is a step master clock.

3.3 PC and DUT are configured to reciprocity delay mechanism.

3.4 link PC and DUT, all the PTP messages on the acquisition link.

3.5 observation and analysis PTP message.

Step 4: the output port of two step DUT

4.1 initialization PC and DUT.

4.2 PC was configured to for two steps from clock, DUT is two step master clocks.

4.3 PC and DUT are configured to reciprocity delay mechanism.

4.4 link PC and DUT, all the PTP messages on the acquisition link.

4.5 observation and analysis PTP message.

Son test 4: the MAC Address test in the multi-casting communication pattern

Test purpose: whether authenticating peer delay mechanism message and other PTP operation have used correct MAC Address.

Method of testing:

Step 1: broadcasting, the MAC Address of the MAC Address of sync message and the message relevant with reciprocity delay mechanism

1.1 initialization PC and DUT.

1.2 PC is configured to from clock, DUT is master clock.

1.3 PC and DUT are configured to reciprocity delay mechanism.

1.4 link PC and DUT, all the PTP messages on the acquisition link.

1.5 the broadcasting that observation and analysis is caught, the MAC Address of sync message and with the MAC Address of reciprocity delay mechanism association message.

Step 2: the MAC Address of administrative message and signaling message

2.1 transmission administrative message, actionField field are GET.

2.2 observe response message that PC sends MAC Address.

Son test 5: support the test of PTP time scale

Test purpose: whether the highest master clock of checking supports the PTP time scale, ordinary clock, and boundary clock becomes and whether the highest master clock is class 6.

Method of testing:

The PTPtimescale that gives tacit consent among the step 1:timePropertiesDS arranges

1.1 initialization DUT.

1.2 configuration DUT is master clock.

1.3 obtain the PTPtimescale of acquiescence.

1.4 observation default setting.

Step 2: the timePropertiesDS bit in the broadcasting packet

2.1 configuration DUT is master clock, PC is from clock.

2.2 set up the PTP link between DUT and the PC.

2.3 catch abundant broadcasting packet.

2.3 observe the PTPtimescale bit of the flagField field in the broadcasting packet head.

Step 3: the clockClass of high master clock

3.1 configuration DUT is master clock.

3.2 obtain the clockClass of acquiescence.

3.3 observation default setting.

The test of son test 6:clockIdentity form

Test purpose: the value of checking clockIdentity should be based on the EUI-64 on the EUI-48.

Method of testing:

1. initialization DUT.

2. link PC and DUT.

3. obtain the clockIdentity value of DUT.

4. 16 hex value of observation and analysis clockIdentity.

Son test 7:IEEE 1588 and config set are specified TLVs

Test purpose: checking ORGANIZATION_EXTENSION__IEEE_C37_238 and ALTERNATE_TIME_OFFSET_INDICATOR TLVs is correctly configured and is appended after broadcasting packet.

Method of testing:

Step 1: broadcasting packet is from DUT

1. initialization PC and DUT.

1.1 configuration DUT is master clock, PC is from clock.

1.2 set up the PTP link between DUT and the PC.

1.3 catch abundant broadcasting packet.

1.4 observe the broadcasting packet head.

Step 2:DUT receives broadcasting packet

Initialization PC and DUT

2.1 PC is so that defaultDS.priority1=0 in configuration.

DUT is so that defaultDS.priority1=10 in configuration.

2.2 set up the PTP link between DUT and the PC.

2.3 the transmission broadcasting packet does not have ORGANIZATION_EXTENSION__IEEE_C37_238, additional or not additional ALTERNATE_TIME_OFFSET_INDICATOR TLVs.

2.4 DUT port.

Two, IEEE1588 agreement " hardware markers " accuracy method of testing

The IEEE1588 agreement is demarcated markers by the markers maker of physical layer, function that realization hardware " is beaten markers ", eliminated the time-delay of the ms levels such as protocol stack and operating system, compare general network for the time agreement software " beat markers " and improved time precision, as shown in Figure 3.Estimating the time precision that the IEEE1588 agreement can realize, is exactly the hardware of the estimating IEEE1588 equipment function of " beating markers " in fact.

P2P transparent clock synchronous mode in the PTP agreement is introduced its synchronization principles, as shown in Figure 4 as example.

Under this pattern, adopted altogether sync message (Sync), follow message (Follow_Up), level time-delay request message (PDelay_Req), level time-delay response message (PDelay_Resp), corresponding these a few class messages of message (PDelay_Resp_Follow_Up) of following of level time-delay, synchronizing process is as follows:

(1) master clock is periodically to sending a Sync message from clock, this message comprises the information of the time of master clock plan transmission, but because the deviation between the time of the time that plan sends and actual transmission message, actual transmitting time can not send with " synchronously " message.This " synchronously " message is stamped from clock at receiving terminal receives markers T2.

(2) master clock is to sending a Follow_Up message from clock, and this message comprises accurately transmitting time T1 of previous Sync message.

When (3) Sync message and Follow_Up message are through level-level transparent clock, correction territory (CF) separately is according to level time-delay request message (PDelay_Req), and level time-delay response message (PDelay_Resp), level time-delay response are followed the delay that residence time (RT) that message (PDelay_Resp_Follow_Up) and message pass through level-level transparent clock and need calculates and upgraded accordingly, revise.

Master clock and transparent clock transmission delay measurement method are as follows:

(1) (interval of PDelay_Req message is independent the setting to the port of accepting of level-level transparent clock to master clock transmission PDelay_Req message, generally should be long than the sync message interval), this message contains the temporal information t1 that the transparent clock plan sends, and stamps the accurately time of reception t2 of this message by master clock.

(2) master clock is accepted port to transparent clock and is returned a PDelay_Resp message, and the time that this message arrival transparent clock is accepted port is t4.

Transparent clock is with as follows from the clock transmission delay measurement method:

(1) transmit port from clockwise level-level transparent clock sends the PDelay_Req message, and this message contains the temporal information t5 that sends from the clock plan, stamps the accurately time of reception t6 of this message by transmit port.

(2) accept port to returning a PDelay_Resp message from clock, this message arrive from the time of clock be t8.

Thus, obtain from the time deviation (Offset) of clock and master clock be:

Formula 1

Wherein, CFSync and CFFollowUp are advancing transparent clock (CF ' Sync and CF ' FollowUp) and are going out transparent clock (CF " Sync and CF " FollowUp) according to master clock-port and port-upgrade from the transmission delay between the clock, and the transmission delay that master clock and level-level transparent clock are accepted port is:

Formula 2

Level-level transparent clock is accepted port and from the transmission delay of clock is:

Formula 3

Revise local zone time from clock according to the clock jitter that is calculated by formula (2) and formula (3) and Internet Transmission time-delay, final realization is synchronous with master clock.

From above synchronizing process as can be known, the core of IEEE1588 agreement is message mutual that contains temporal information, and these messages mainly comprise sync message (Sync), follow message (Follow_Up), time-delay request message (Delay_Req), time-delay response message (PDelay_Resp), level time-delay request message (PDelay_Req), level time-delay response message (PDelay_Resp), level time-delay response are followed message (PDelay_Resp_Follow_Up) etc.

The test of IEEE1588 agreement " hardware markers " accuracy is the test to IEEE1588 equipment " hardware markers " ability, give the rise time of this frame message in network when namely the integration by message analysis software and high precision clock realizes message analysis, by comparing of this time and the contained temporal information of this frame message, can detect " hardware markers " function of this IEEE1588 equipment.

Three, IEEE1588 agreement time synchronized accuracy method of testing

Based on the test of the time synchronized accuracy of routine and IEEE1588 method of testing as shown in Figure 1 and Figure 2.

Method of testing based on electric power industry network measure and control system clock synchronization protocol of the present invention comprises three parts: IEEE1588 protocol conformance test method, IEEE1588 agreement " hardware markers " accuracy method of testing, IEEE1588 agreement time synchronized accuracy method of testing.Wherein, the IEEE1588 protocol conformance test method has been realized the conforming test to IEEE1588 electric power system config set IEEE PC37.238, according to grammer, the structure of IEEE1588 agreement, the interoperability issue of devices from different manufacturers in the time of can solving electric power system application IEEE1588 agreement; IEEE1588 agreement " hardware markers " accuracy method of testing has realized the test of IEEE1588 protocol core function, can obtain the actual parameter of equipment key function, for the performance of valuator device provides foundation; IEEE1588 agreement time synchronized accuracy method of testing has realized the evaluation of IEEE1588 protocol application effect, and whether the time synchronized accuracy that can estimate all kinds of equipment by the IEEE1588 protocol synchronization satisfies the electric power system application requirements.

Certainly, those skilled in the art in the art will be appreciated that, above-described embodiment only is that the present invention is described, and be not as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claim of the present invention the variation of above-described embodiment, modification etc.

Claims

1. method of testing based on the network measure of electric power industry and control system clock synchronization protocol, it is characterized in that, it may further comprise the steps: IEEE1588 testing protocol consistency, the test of IEEE1588 agreement hardware markers accuracy and the test of IEEE1588 agreement time synchronized accuracy;

2. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: the test of described PTP default property value comprises the test of portDS.logAnnounceInterval property value, the test of portDS.logSyncInterval property value, the test of portDS.announceReceiptTimeout property value, the test of τ initial value, the test of portDS.logMinPdelayReqInterval property value, the test of defaultDS.priority1 property value, the test of defaultDS.priority2 property value, the test of defaultDS.slaveOnly property value, the test of the test of defaultDS.domainNumber property value and transparentClockdefaultDS.primaryDomain property value.

3. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: described BMC algorithm-data set comparison algorithm test comprises the DSC test of heuristics based on Grandmaster Priority1, DSC test of heuristics based on grandmasterClockQuality.clockClass, DSC test of heuristics based on grandmasterQuality.clockAccuracy, DSC test of heuristics based on grandmasterCloclQuality.offsetScaledLogVariance, based on the DSC test of heuristics of Grandmaster Priority2 and based on the DSC test of heuristics of Grandmaster Identity.

4. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1 is characterized in that: described BMC algorithm-data set comparison algorithm test comprises also whether test test broadcasting packet qualified, test data set comparison algorithm DSC-II, DUT clock grade more than or equal to 128 state decision-making SD test of heuristics, a step clock and the clock modules test of two steps, in the multi-casting communication pattern the MAC Address test, support the test of PTP time scale, the test of clockIdentity form and IEEE 1588 and config set to specify TLVs.

5. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1 is characterized in that: described Determines test of heuristics comprise the DUT clock grade less than 128 state decision making algorithm test and DUT clock grade more than or equal to 128 state decision-making SD test of heuristics.

6. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: described IEEE1588 testing protocol consistency also comprises dependence test, and described dependence test comprises: the MAC Address test in MIB test, IEEE Std. 802.1Q and configurable priority and VLAN ID test, a step clock and the clock modules test of two steps, the multi-casting communication pattern, support the test of PTP time scale, the test of clockIdentity form and IEEE 1588 and config set to specify TLVs.

7. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: described IEEE1588 agreement hardware markers accuracy method of testing, under the P2P transparent clock synchronous mode in the PTP agreement, adopted altogether sync message Sync, follow message Follow_Up, level time-delay request message PDelay_Req, level time-delay response message PDelay_Resp, the corresponding message PDelay_Resp_Follow_Up that follows of level time-delay, synchronizing process is as follows:

8. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: described master clock and transparent clock transmission delay measurement method are as follows:

9. the method for testing based on the network measure of electric power industry and control system clock synchronization protocol as claimed in claim 1, it is characterized in that: described transparent clock is with as follows from the clock transmission delay measurement method: