CN103051312A - 低阻抗栅极控制方法和设备 - Google Patents
低阻抗栅极控制方法和设备 Download PDFInfo
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- CN103051312A CN103051312A CN2012103869823A CN201210386982A CN103051312A CN 103051312 A CN103051312 A CN 103051312A CN 2012103869823 A CN2012103869823 A CN 2012103869823A CN 201210386982 A CN201210386982 A CN 201210386982A CN 103051312 A CN103051312 A CN 103051312A
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Abstract
本发明涉及低阻抗栅极控制方法和设备。根据本发明模块的一个实施方式,该模块包括:多个栅极驱动器芯片,并联耦接并具有共用栅极输入端、共用电源电压和共用输出端。所述芯片彼此隔开并具有在第一外部芯片边缘和第二外部芯片相对边缘之间延伸的组合宽度。所述模块进一步包括多个电容器,并联耦接在地和所述共用电源电压之间,以及横向电磁(TEM)传输线介质,其耦接至所述芯片的共用输出端且电流方向垂直于所述芯片的组合宽度。
Description
技术领域
本申请涉及功率晶体管,具体涉及具有低栅极电路电感的功率晶体管。
背景技术
在功率电子电路中,例如反相器、转换器等中,通过诸如MOSFET的栅电极、IGBT的栅电极、(双极晶体管的基极电流电极)等来控制诸如MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅极双极晶体管)和JFET(面结型场效应晶体管)的功率半导体开关。控制功率半导体开关的导通(turn-on)、断开(turn-off)、阻断(blocking)和导电状态的命令在控制器中生成,并通过每个功率开关的栅极驱动器被传送至控制端。栅极驱动器从控制器输入电压移动命令信号(如,经由变压器、光耦合器、电平位移器等),并对用于预期的开关转变(倾斜、上升和下降时间、延迟时间等)的驱动信号进行整形。
上述功率半导体器件也可用于例如通过检测负载的短路来管理故障条件。负载短路可发生在两相之间,所有三相之间或一相或多相与地之间。在这样的短路条件下,使用功率半导体的输出特性。例如,漏极(集电极)电流,即功率半导体器件的功率端子之间的电流,以额定电流的4到10倍饱和,而饱和水平由栅极电压量和器件的传送特性确定。功率半导体可以以高压抵抗这样的高电流条件仅几个微秒。驱动器或控制器快速感测这样的条件并断开功率半导体器件。不同类型的短路条件都可产生。在每种情况下,功率电路的特征di/dt响应引起栅极过电压条件,其出现是由于在器件的栅极输入端看去的杂散电感引起的。该杂散电感在本文中通常称为栅极电路电感,包括与栅极驱动器板(板布局)上的布线,从栅极驱动器到功率模块控制端的布线,以及功率模块内对功率晶体管栅极的端子、布线和导线路径相关联的电感。栅极过电压的高度部分取决于栅极电路电感。换句话说,栅极处电荷可流入器件的电压源的速度不仅受栅极电路的阻抗的限制,而且受电感的限制。栅极电路电感限制栅极电流可变化的速度。因此,对于典型的栅极电路,栅极过压可超过20V,这通常为最大额定值。
同样,在并联在一起的用于较高功率芯片的模块中,共用栅极要求更高的功率栅极驱动器。在栅极驱动器内,这通常通过利用具有较高电流额定值和较低栅极电阻的晶体管来实现。栅极驱动器(板布局)的板上布线、从栅极驱动器到功率模块控制端的布线、以及功率模块内的对并联器件栅极的端子、布线和导线路径与单个晶体管的情况相似。这产生基本上与单个晶体管情况中相同的栅极电路电感。流出共用栅极的电流随并联器件的数目而按比例提高。栅极电流的di/dt也相应按比例提高。栅极电路电感为驱动器电路中的几何构型和对功率晶体管模块的连接的函数。较低的栅极电路电感改善短路响应,这有助于快速将栅极电压限制到由驱动器设定的值,并从而限制负载处的短路电流之后短路的快速断开(栅极电路中高电感的主要问题在于短路条件下的栅极电压的增加)。较低的栅极电路电感也改善功率晶体管器件的导通和断开响应,提供了更快的器件响应时间。栅极电路电感通常被忽略,而偏向于电阻性阻抗。栅极电路电感已经通过直接将栅极驱动器板组装到功率模块端子上解决,而在其间无需布线。栅极驱动器板上和功率模块或封装内的电感通常没有解决。
发明内容
功率半导体器件的栅极电路电感通过利用一个以上横向电磁波(TEM)传输线介质将栅极驱动器电路的输出端连接至功率半导体电路的栅极输入端而减小。这些电路可集成在同一模块中,或包含在不同模块中。在任一情况下,栅极驱动器电路包括多个并联耦接的栅极驱动器芯片,且功率半导体电路类似地包括多个并联耦接的功率晶体管芯片。功率晶体管芯片彼此隔开,且具有在最外功率晶体管芯片的相对边缘之间延伸的宽度。栅极驱动器芯片可具有类似的横向隔开的结构。用于将功率晶体管芯片的共用栅极输入端耦接至栅极驱动器芯片的共用输出端的TEM传输线介质的每一个的电流方向垂直于功率晶体管芯片的组合宽度(和栅极驱动器芯片的组合宽度)。
根据模块的一个实施方式,所述模块包括多个栅极驱动器芯片,多个电容器和横向电磁(TEM)传输线介质。多个栅极驱动器芯片并联耦接并具有共用栅极输入端、共用电源电压和共用输出端。多个芯片彼此隔开,并具有在第一外部芯片的边缘和第二外部芯片的相对边缘之间延伸的组合宽度。多个电容器并联耦接在地和共用电源电压之间。TEM传输线介质耦接至多个芯片的共用输出端,且电流方向垂直于多个芯片的组合宽度。
根据模块的另一个实施方式,所述模块包括多个功率晶体管芯片、多个电容器和TEM传输线介质。多个功率晶体管芯片并联耦接并具有共用栅极输入端、共用电源电压和共用输出端。多个芯片彼此隔开,并具有在第一外部芯片的边缘和第二外部芯片的相对边缘之间延伸的组合宽度。多个电容器并联耦接在地和共用电源电压之间。TEM传输线介质耦接至多个芯片的共用栅极输入端,且电流方向垂直于多个芯片的组合宽度。
根据功率晶体管系统的实施方式,所述系统包括多个栅极驱动器芯片、第一多个电容器、多个功率晶体管芯片、第二多个电容器和至少一个TEM传输线介质。多个栅极驱动器芯片并联耦接并具有共用栅极输入端、共用电源电压和共用输出端。第一多个电容器并联耦接在地和多个栅极驱动器芯片的共用电源电压之间。多个功率晶体管芯片并联耦接并具有共用栅极输入端、共用电源电压和共用输出端。多个功率晶体管芯片彼此隔开并具有在第一外部功率晶体管芯片的边缘和第二外部功率晶体管芯片相对边缘之间延伸的组合宽度。第二多个电容器并联耦接在地和多个功率晶体管芯片的共用电源电压之间。至少一个TEM传输线介质将多个功率晶体管芯片的共用栅极输入端耦接至多个栅极驱动器芯片的共用输出端,且电流方向垂直于多个功率晶体管芯片的组合宽度。
本领域技术人员将通过阅读下面的详细说明并参照附图认识到另外特征和优点。
附图说明
图中元素不必彼此相对按比例绘制。相似的标识号表示相应的类似部件。各种示出的实施方式的特征可组合,除非它们彼此排斥。实施方式在附图中示出并在下面的说明中详细描述。
图1A和图1B示出功率晶体管系统的实施方式的框图。
图2示出图1的功率晶体管系统的示意图。
图3A和图3B示出图1的功率晶体管系统的实施方式的平面图。
图4示出图1的功率晶体管系统的侧面透视图。
图5至图9示出根据不同实施方式横向电磁(TEM)传输线介质对功率晶体管芯片的连接的平面图。
图10至图12示出根据不同实施方式的横向电磁(TEM)传输线介质对功率晶体管芯片的连接的侧面透视图。
图13A示出具有集成TEM传输线介质的功率晶体管模块的平面图。
图13B示出图13A中功率晶体管模块沿线A-A’的截面透视图。
图14至图16示出根据不同实施方式,近似于功率晶体管应用中带状线(strip line)性能的TEM传输线介质的透视图。
具体实施方式
图1A和图1B示出功率晶体管系统的实施方式。图1A示出高端(high-side)元件和连接的混合块图/电路示意图,图1B示出对应的低端(low-side)元件和连接的混合块图/电路示意图。图2示出图1的功率系统的等效电路图,其实施为示例性半桥设计。通常,功率晶体管系统可包括任何类型的半桥、H-桥、全桥或任何其他类型的功率晶体管电路和相应的栅极驱动器。图3A示出栅极驱动器模块100的顶面侧的平面图,而图3B示出栅极驱动器模块100的相对的底面侧的平面图。
栅极驱动器模块100包括多个并联耦接并具有共用栅极输入端104、共用电源电压(VDD)和共用输出端106的高端栅极驱动器芯片102。高端栅极驱动器芯片102在图1A中示意性地示为多个npn晶体管,而在图2中示意性地示为单个npn晶体管。栅极驱动器模块100也包括多个并联耦接并具有共用栅极输入端110、共用电源电压(VSS)和共用输出端112的低端栅极驱动器芯片108。低端栅极驱动器芯片108在图1A中示意性地示为多个pnp晶体管,而在图2中示意性地示为单个pnp晶体管。任何类型的晶体管都可用于栅极驱动器模块100的输出级。例如,可使用推挽式双极晶体管、MOSFET、JFET、单极或双极栅极驱动器(即,单(+)电源电压或+/-电源电压)。
高端电源电压VDD为正电压(如+15V),而低端电源电压VSS为接地或负电压(如-15V)。对于功率半导体器件,接地意味着器件栅极信号的参考点。同样的控制信号输入(“驱动信号)可施加于高端和低端的共用栅极输入端104、110,而高端和低端共用输出端106、112被耦接在一起并提供栅极驱动器模块100的输出114。高端电源电压VDD和高端栅极驱动器芯片102的集电极之间的连接具有相应的电感(LHS),而低端电源电压VSS和低端栅极驱动器芯片108的集电极之间的连接类似地具有相应的电感(LLS)。
第一组电容器(CHS)并联耦接在地和高端电源电压VDD之间。第二组电容器(CLS)并联耦接在地和低端电源电压VSS之间。电容器可以是驱动器板的集成部分,其中绝缘材料至少局部用作高介电材料存储电荷。可选地,电容器也可以是离散元件,如图3A和3B所示。在任一情况下,高端栅极驱动器芯片102的发射极和高端共用输出端106之间的连接具有相应的电感(LHS_OUT),而低端栅极驱动器芯片108的发射极和低端共用输出端112之间的连接具有相应的电感(LO2)。栅极驱动器模块100经由一个以上横向电磁(TEM)传输线介质130、140耦接至功率晶体管系统的功率晶体管模块120。如这里所用的,术语“横向电磁”或缩写“TEM”指的是电场和磁场线被限制在与电流方向垂直(横向)的方向上的传播模式。
如图3A所示,高端栅极驱动器芯片102例如在连接至高端电源电压VDD的导电平面116上彼此隔开,并具有在最外高端栅极驱动器芯片102的相对边缘101、103之间延伸的组合宽度(WHS_GD)。图3B示出例如在连接至低端电源电压VSS的另一个导电平面118上彼此隔开的低端栅极驱动器芯片108,并具有在最外低端栅极驱动器芯片108的相对边缘105和107之间延伸的组合宽度(WLS_GD)。高端和低端导电平面116、118可设置在印刷电路板(PCB)119的相对侧,如图3A和3B所示。同样设置在PCB119每一侧的为耦接至各高端和低端电容器(CHS、CLS)的一个端子的接地平面(ground plane)115。各电容器的其他端耦接至相应的导电平面116、118。上级驱动器可具有达林顿(Darlington)输出级,如图3A和3B所示,其中至少最后输出级具有低电感设计。
至少一个TEM传输线介质将栅极驱动器模块100的输出端114耦接至功率晶体管模块120的输入端。例如在图1A和图1B中,栅极驱动器模块100包括耦接至高端和低端栅极驱动器芯片102、108的发射极的TEM传输线介质150。根据一个实施方式,TEM传输线介质150为带状线,所述带状线具有耦接至高端和低端栅极驱动器芯片102、108的发射极的第一导电层和与第一导电层绝缘并耦接到地的第二导电层。如上所述,栅极驱动器模块的晶体管102、108是并联的,因此在栅极驱动器模块100内的TEM传输线介质150的宽度上分布驱动器电流。电容器(CHS和CLS)也由几个并联电容器构成从而在带状线宽度上分布电容器电流。此外,电容器和晶体管行在彼此后面集成到带状线中,从而实现电流垂直于并联电容器或晶体管行102、108流动的规则。仅TEM传输线介质150的第一导电层(耦接至发射极)在图1A和图1B中示出。另一导电层(耦接至地)看不到。在操作过程中,电流在TEM传输线介质150中前后流动,这导致抵消了减小与栅极驱动器模块100相关联的部分栅极电路电感(如从功率晶体管模块120向栅极驱动模块100看去)的磁场。栅极电路电感LG被限制到LG*Achip≤30nH*1cm2,其中,Achip为功率模块120内的功率芯片面积,这多少确定了芯片122的寄生电感和相关栅极电流。因此栅极电路电感与芯片面积成比例。
第二TEM传输线介质130可耦接到栅极驱动器模块100的第一TEM传输线介质150。第二TEM传输线介质130可具有与第一TEM传输线介质150相同的结构,例如,第二TEM传输线介质130可以为带状线,所述带状线具有耦接到第一带状线150的导电层(其耦接至栅极驱动器共用输出端106、108)的第一导电层和与第一导电层绝缘并耦接到地的第二导电层。作为功率晶体管模块120的部件或在功率晶体管模块120的外部,可提供另一个TEM传输线介质140用来将第二TEM传输线介质130耦接到功率晶体管模块120的输入端。
功率晶体管模块120包括多个并联耦接并具有共用栅极输入端123、共用电源电压(VS)和共用输出端124的功率晶体管芯片122。在图1和图2中功率晶体管芯片122示意性地示为多个IGBT。任何类型的功率晶体管可用于功率晶体管模块120中。例如,可使用IGBT、MOSFET、JFET或任何其他电压驱动的器件(常开或常闭型)。电源电压VS和功率晶体管芯片122的集电极之间的连接具有相应电感(LOUT)。多个DC阻塞电容器(CDC)126并联耦接在地和电源电压VS之间。在输入端123,功率晶体管芯片122的栅极连接到TEM传输线介质140。该TEM传输线介质140可以在于功率晶体管模块120的外部或集成在功率模块120内。
在任一情况下,功率晶体管芯片122例如在连接至功率晶体管芯片122的发射极的导电平面上彼此隔开,并具有在最外功率晶体管芯片122的相对边缘之间延伸的组合宽度(在图1A和图1B中作为WPT示意性地示出)。在图1A和图1B中,功率晶体管芯片122仅示意性地示出(为IGBT),但可以相对栅极驱动器芯片102、108被物理地以行设置,如图3A和图3B所示。同样地,功率晶体管芯片122的组合宽度对应于芯片122的各宽度加上相邻芯片之间的间隔(例如,如果芯片彼此偏移设置,则减去任何交叠)。
如上所述,一端连接到功率晶体管芯片122的栅极输入端123的TEM传输线介质140具有例如经由一个或多个另外的TEM传输线戒指130耦接到栅极驱动器模块100的输出端114的相对端。对于带状线,每个带状线的一个导电平面将栅极驱动器模块100的输出端114耦接到功率晶体管模块120的栅极输入端123,而另一个导电平面耦接到地,从而使得最终的磁场彼此抵消,这减小了在功率晶体管模块120的栅极输入端123处看去的栅极电路电感。在图2中,栅极电路电感对应于向栅极驱动器模块100的输出端114看去的电感(LG1),TEM传输线介质130或连接到栅极驱动器模块输出端114的集电极的电感(LG2)和连接到功率晶体管模块120的栅极输入端123的TEM传输线介质140的电感(LG3)。第三电感LG3根据栅极输入连接如何设置可在功率晶体管模块120的外部或内部,如上所述。与传统功率晶体管输入端互连相比,通过使用一个以上TEM传输线介质130、140、150,栅极电路电感(LG1+LG2+LG3)显著减小。功率晶体管模块120的输出端124还可耦接到TEM传输线介质160,从而减小功率晶体管模块120的输出电感。
图4示出了图1的功率晶体管系统实施方式的示意截面图。多个高端和低端电源电容器(CHS、CLS)设置在栅极驱动器模块100的相对侧,且多个高端和低端栅极驱动器晶体管102、108也设置在栅极驱动器模块100的相对侧。包括在栅极驱动器模块100内的TEM传输线介质150具有第一金属化层200,其与第二金属化层202被诸如PCB或陶瓷基板的绝缘体204隔开。第一金属化层200连接到高端栅极驱动器晶体管102的共用输出端106,而第二金属化层202连接到地。与第一金属化层200设置在绝缘体204同一侧上的第三和第四金属化层206、208形成图2中示出的高端电容器连接。对高端电容器CHS的接地连接通过导电通孔210来设置,所述导电通孔从接地平面金属化层202穿过绝缘体204延伸至相应的金属化层208。第二绝缘体212设置在第二金属化层202下面,而三个另外的金属化层214、216、218设置在第二绝缘体212的相对侧,从而提供对图2示出的低端电容器CLS和低端栅极驱动器晶体管208的电连接。例如,对低端电容器CLS的接地连接是由导电通孔220来设置,所述导电通孔从接地平面金属化层202穿过第二(下部)绝缘体212延伸至相应的金属化层214。还提供导电通孔222来将低端栅极驱动器晶体管208的输出端连接到栅极驱动器模块TEM传输线介质150的上部金属化层200。这样,该TEM传输线介质150的上部导电层200被耦接到高端和低端栅极驱动器晶体管102、108的共用输出端106、112,而TEM传输线介质150的下部导电层耦接到地。
从外部将栅极驱动器模块100连接到功率晶体管模块120的TEM传输线介质130具有类似的结构。即,上部金属化层230承载栅极驱动器输出信号,而下部金属化层232耦接到地。绝缘体234位于两个导电层230、232之间。可以采用接合线或其他连接器240作出对栅极驱动器模块100的适当的电连接。在功率晶体管模块120的栅极输入端处的TEM传输线介质140同样具有承载栅极驱动器输出信号的上部金属化层250和耦接到地的下部金属化层252,绝缘体254位于两个导电层250、252之间。可以使用接合线或其他连接器260来作出对功率晶体管模块120的输入侧的适当的电连接。例如,承载栅极驱动器输出信号的导电层250耦接到功率晶体管122的栅极,而接地的导电层252连接到功率晶体管122的辅助发射极。辅助发射极连接未上电并被耦接到功率晶体管122的发射极。为主(上电的)发射极连接提供的独立的端子。功率晶体管芯片122附接至功率模块120内的下部金属化层270。下部金属化层270提供功率晶体管模块120的输出连接。通过在输出金属化层270和接地的另外的金属化层274之间提供绝缘体层272,输出连接也可以是TEM传输线介质160。
图5至图7示出了对单一的一个功率晶体管芯片122的连接的实施方式的各种俯视图。在图5中,从主(上电的)发射极端302到功率晶体管芯片122的发射极304设置了大量导线接合连接300。从输入TEM传输线介质140的接地的金属化层252到功率晶体管芯片122的辅助(未上电的)发射极304设置了两个导线接合连接306、308。从承载栅极驱动器输出信号的输入TEM传输线介质140的金属化层250到功率晶体管芯片122的单个栅极垫312提供了单个导线接合连接310。绝缘体254位于TEM传输线介质140的两个金属化层250、252之间,如前面所述。图6类似于图5,但设置了单个辅助发射极连接320和两个栅极连接322、324。图7类似于图5和图6,但设置了两个辅助发射极连接330、332和两个栅极连接334、336。在每种情况下,在典型导线直径为0.4mm至0.6mm时,用于连接到功率晶体管芯片122的栅极和辅助发射极的导线的长度优选限制为最大10cm每个芯片,且距离优选限制为最大3mm每个芯片,这涉及13nH至11nH的栅极电路电感LG。
图8示出去除了外壳和盖子的功率晶体管模块120的俯视平面图。为了易于图示,仅示出了输入TEM传输线介质140和功率晶体管芯片122之间的电连接。本领域技术人员易于认识到如何作出剩余连接。功率晶体管芯片122设置在诸如PCB或陶瓷基板的基板400上。高端电容器(CPT_HS)和功率晶体管122位于一个输出端402上,而低端电容器(CPT_LS)和功率晶体管122位于另一个输出端404上。还设置了各栅极输入端406、408和各电源端410、412。所有端子402、404、406、408、410、412都设置在基板400上。
在每个输出端402、404上的功率晶体管芯片122都彼此隔开,并具有在最外功率晶体管芯片122的相对边缘414、416之间延伸的组合宽度(WPT)。第一输入TEM传输线介质420来自模块120的一侧并具有承载栅极驱动器输出信号的第一金属化层422并连接到模块120的高端栅极端子408。几个连接424从第一金属化层422到高端栅极端子408形成,且从高端栅极端子408至高端功率晶体管芯片122的栅极输入端作出了几个另外的连接426,如前面所述。第一输入TEM传输线介质420还具有通过绝缘体430与第一金属化层422分开的第二(接地的)金属化层428,并例如经由导线接合或其他类型的连接432被连接到高端功率晶体管芯片122的辅助(未上电的)发射极,如前面所述。第二输入TEM传输线介质440来自模块120的另一侧,并类似地连接到低端功率晶体管芯片122的栅极和辅助发射极输入端。
图9示出去除了外壳或盖子的功率晶体管模块120的另一个实施方式。该实施方式类似于图8中示出的实施方式,但栅极驱动器电路集成在功率晶体管模块120中。根据该实施方式,高端栅极驱动器芯片102设置在TEM传输线介质500的上部金属层502上。该金属化层502承载高端栅极驱动器晶体管102的栅极驱动器输出信号,并经由几个连接504直接连接到高端功率晶体管芯片122的栅极输入端。第一TEM传输线介质500的相应的(接地的)下部金属化层506与上部金属化层502由绝缘体508分开,并经由几个连接510连接到高端功率晶体管122的辅助的(未加电的)发射极。低端栅极驱动器芯片108设置在第二TEM传输线介质520上,所述第二TEM传输线介质类似地连接到低端功率晶体管芯片122的栅极和辅助发射极输入端。根据该集成实施方式,消除了栅极驱动器输出端和功率晶体管输入端之间的另外连接。
图10至图12示出了TEM传输线介质600和功率晶体管芯片122之间的不同的连接实施方式。根据这些实施方式,TEM传输线介质600为带状线,所述带状线具有通过绝缘体606与第二(下部)导电层604分开的第一(上部)导电层602。上部导电层602承载来自栅极驱动器电路的输出信号,而下部导电层604耦接到地。在图10中,带状线600功率晶体管模块外部向下或来自模块的端子,并一直延伸直到芯片水平,这里带状线600由线接合608、610直接连接到功率晶体管芯片122。可以在接合点从底部支撑导线接合。为了在接合工艺中将带状线保持在原位,带状线600可以被向下胶粘到基板612上(其可具有上部图案化金属化层614和下部金属化层616),或导线可已经在带状线600的第一端(看不到)的外部接合,而带状线600的第二端然后在第二步中接合到芯片122。在每种情况下,上部导电层602连接到功率晶体管芯片122的栅极输入端,而下部导电层604连接到芯片122的辅助(未上电的)发射极。
在图11中,带状线600从模块外部向下,或来自模块端子并一直延伸到芯片水平,这里带状线600例如通过超声焊、激光焊、胶粘、焊接、扩散焊接或烧结直接结合到功率晶体管芯片122。每个功率晶体管芯片122可以具有厚度高于或等于10μm的主要由铜形成的金属化层618。
在图12中,带状线600通过作为端子(平行引脚未示出)的几个平行引脚620接近,由从引脚着脚点624到功率晶体管芯片122结合的导线或条带(ribbon)622持续,如前面所述。引脚620可被超声焊接、激光焊接、胶粘、焊接、扩散焊接或烧结。销铆钉组件也可用于引脚620。
图13A示出功率晶体管模块120的实施方式的俯视平面图。图13B是图13A中沿线A-A’的模块的截面图。根据该实施方式,功率晶体管模块120具有在基板702上的多层结构700,其中功率晶体管芯片122设置在基板上。通过嵌入、层压、金属化和/或其他结构化处理,带状线被集成到多层结构700中,并延伸到外部驱动器或带状线,并被结合至包括基板702的多层结构700。例如,基板702为诸如具有图案化的顶部金属化层704和底部金属化层706的陶瓷基板的绝缘体。功率晶体管芯片122附接至顶部图案化金属化层704的一个区域,而绝缘体708设置在基板702和芯片122上。多层结构700的一部分包括金属化层710,其连接到功率晶体管芯片122的栅极输入端。多层结构700的该部分710连接到承载栅极驱动器输出信号的线712。多层结构700的第二部分714与第一部分710分开并连接到功率晶体管芯片122的辅助(未上电的)发射极。多层结构700的第二部分714延伸穿过模块绝缘体708到达基板702上的顶部图案化金属化层704。该部分顶部图案化金属化层704连接到线716。
用于将功率晶体管芯片122的共用栅极输入端耦接至栅极驱动器芯片102、108的共用输出端的TEM传输线介质不必仅是带状线。TEM传输线介质可接近带状线,以为功率晶体管模块120提供低的栅极电路电感。
图14示出实施为带状线的TEM传输线介质800的实施方式,所述带状线具有上部和下部隔开的导电层802、804。一个导电层802将栅极驱动器输出端耦接至功率晶体管栅极输入端(并因此标记为“G”)。导电层804承载栅极驱动器输出信号。导电层804接地并耦接到功率晶体管122的辅助(未上电的)发射极(并因此标记为“E”)。
图15示出实施为设置在两个不同的分开层812、814中的多个独立导线的TEM传输线介质810的实施方式,其整体接近带状线的性能。例如,上部布线层812将栅极驱动器输出端耦接到功率晶体管栅极输入端(并因此标记为“G”)。该层812的导线整体承载栅极驱动器输出信号。下部布线层814接地并耦接到功率晶体管122的辅助(未上电的)发射极(并因此标记为“E”)。电流在两个布线层412、414相对方向上流动。为了限制故障条件中电阻性过压,降低栅极电阻器(RG)。由于栅极电阻器(RG)通常用于设定功率开关122的开关速度,所以栅极驱动器100可选地具有能够减少栅极电阻器的倾斜控制特性。每功率芯片的RG可以是10欧姆,<5欧姆,<1欧姆,<0.4欧姆,或LG*Achip≤10(5,1)欧姆*1cm2,其中,Achip是功率模块120中的功率芯片面积。
图16示出实施为设置在同一布线层826中的多个独立导线822、824的TEM传输线介质820的实施方式。与图15中示出的TEM结构相对,图16中示出的TEM结构仅具有导线822、824的单层826。为了接近带状线的性能,导线822、824彼此介电绝缘。每个其他导线824将栅极驱动器输出端耦接到功率晶体管栅极输入端(并因此标记为“G”)。这些导线824承载栅极驱动器输出信号。剩余导线822接地并耦接到功率晶体管122的辅助(未上电的)发射极(且因此标记为“E”)。在图15和图16的实施方式中,每个导线的电感都大于每层中所有导线的组合电感。对于较大距离的平行芯片和源自不对称功率连接的共模问题,平行芯片组可具有达到驱动器板(这里可以过来共模漂移)的分开的低电感栅极电路。
为描述方便,使用空间上的相对术语,如“在…下面”、“在…下方”、“下部”、“在…上方”、“上部”等来说明解释一个元件相对第二元件的配置。这些术语意在包括除了与图中示出那些不同的定向之外的期间的不同定向。进一步,诸如“第一”、“第二”等的术语也用于描述不同元件、区域、部件等,其意并不在用于限制。整个说明书中,相似的术语表示相似的元件。
如本文中所使用的,术语“具有”、“含有”、“包括”、“包含”等是开放性术语,其表示存在所述元件或特征,但不排除另外的元件或特征。冠词“一个”、“所述”是为了包括复数和单数,除非说明书中明确指示。
应该理解,这里所述的不同实施方式的特征可彼此组合,除非另外指出。
尽管本文已经使出和描述了特定的实施方式,但本领域技术人员可理解的是,在不脱离本发明的精神的范围内,多种替换和/或等效实施可替代本文示出和描述的特定的实施方式。本申请涵盖本文所讨论的特定实施方式的任何修改或变形。因此,本发明仅由权利要求及其等同替换限制。
Claims (21)
1.一种模块,包括:
多个栅极驱动器芯片,并联耦接并具有共用栅极输入端、共用电源电压和共用输出端,所述多个芯片彼此隔开并具有在第一外部芯片的边缘和第二外部芯片的相对边缘之间延伸的组合宽度;
多个电容器,并联耦接在地和所述共用电源电压之间;以及
横向电磁(TEM)传输线介质,耦接至所述多个芯片的共用输出端且电流方向垂直于所述多个芯片的所述组合宽度。
2.根据权利要求1所述的模块,其中,所述TEM传输线介质为包括第一导电带和第二导电带的带状线,所述第一导电带与所述第二导电带介电绝缘,所述第一导电带耦接至所述多个芯片的所述共用输出端,所述第二导电带耦接至地。
3.根据权利要求1所述的模块,其中,所述TEM传输线介质包括多个彼此介电绝缘的导线,且其中,每个导线的电感大于所有导线的组合电感。
4.根据权利要求1所述的模块,其中,所述TEM传输线介质包括多个彼此介电绝缘的导线,且其中,每个其他的导线耦接至所述多个芯片的所述共用输出端,而剩余的导线耦接至地。
5.根据权利要求1所述的模块,其中,所述TEM传输线介质经由多个接合线耦接至所述多个芯片的所述共用输出端。
6.根据权利要求1所述的模块,其中,所述TEM传输线介质直接连接至每个芯片的输出端。
7.根据权利要求1所述的模块,其中,所述多个芯片设置在绝缘体上,且其中,所述TEM传输线介质包括设置在所述绝缘体第一侧上并连接至所述多个芯片的所述共用输出端的第一金属化层和设置在所述绝缘体的相对的第二侧上并连接至地的第二金属化层。
8.根据权利要求1所述的模块,进一步包括多个功率晶体管芯片,所述多个功率晶体管芯片与所述多个栅极驱动器芯片集成在同一模块中并具有经由所述TEM传输线介质耦接至所述多个栅极驱动器芯片的所述共用输出端的共用栅极输入端。
9.根据权利要求8所述的模块,其中,所述多个功率晶体管芯片具有经由所述TEM传输线介质耦接至地的共用未上电发射极输入端。
10.一种模块,包括:
多个功率晶体管芯片,并联耦接并具有共用栅极输入端、共用电源电压和共用输出端,所述多个芯片彼此隔开并具有在第一外部芯片的边缘和第二外部芯片的相对边缘之间延伸的组合宽度;
多个电容器,并联耦接在地和所述共用电源电压之间;以及
横向电磁(TEM)传输线介质,耦接至所述多个芯片的共用栅极输入端且电流方向垂直于所述多个芯片的所述组合宽度。
11.根据权利要求10所述的模块,其中,所述TEM传输线介质为包括第一导电带和第二导电带的带状线,所述第一导电带与所述第二导电带介电绝缘,所述第一导电带耦接至所述多个芯片的所述共用栅极,且所述第二导电带耦接至地。
12.根据权利要求10所述的模块,其中,所述TEM传输线介质包括多个彼此介电绝缘的导线,且其中,每个导线的电感大于所有导线的组合电感。
13.根据权利要求10所述的模块,其中,所述TEM传输线介质包括多个彼此介电绝缘的导线,且其中,每个其他导线耦接至所述多个芯片的所述共用栅极输入端,而剩余导线耦接至地。
14.根据权利要求10所述的模块,其中,所述TEM传输线介质经由多个接合线耦接至所述多个芯片的所述共用栅极输入端。
15.根据权利要求10所述的模块,其中,所述TEM传输线介质直接连接至每个芯片的栅极输入端。
16.根据权利要求10所述的模块,其中,所述多个芯片设置在绝缘体上,且其中,所述TEM传输线介质包括设置在所述绝缘体第一侧上并连接至所述多个芯片的所述共用栅极输入端的第一金属化层和设置在所述绝缘体相对的第二侧上并连接至地的第二金属化层。
17.根据权利要求10所述的模块,进一步包括与多个栅极驱动器芯片,所述多个栅极驱动器芯片与所述多个功率晶体管芯片集成在同一模块中,所述多个栅极驱动器芯片具有经由所述TEM传输线介质耦接至所述多个功率晶体管芯片的所述共用栅极输入端的共用输出端。
18.根据权利要求10所述的模块,其中,所述多个功率晶体管芯片具有共用未上电发射极输入端,且其中,所述TEM传输线介质包括耦接至所述多个功率晶体管芯片的所述共用栅极输入端的第一导线和耦接至所述多个功率晶体管芯片的所述共用未上电发射极输入端的第二导线,所述第一导线和所述第二导线彼此绝缘。
19.一种功率晶体管系统,包括:
多个栅极驱动器芯片,并联耦接并具有共用栅极输入端、共用电源电压和共用输出端;
第一多个电容器,并联耦接在地和所述多个栅极驱动器芯片的所述共用电源电压之间;
多个功率晶体管芯片,并联耦接并具有共用栅极输入端、共用电源电压和共用输出端,所述多个功率晶体管芯片彼此隔开并具有在第一外部功率晶体管芯片的边缘和第二外部功率晶体管芯片的相对边缘之间延伸的组合宽度;
第二多个电容器,并联耦接在地和所述多个功率晶体管芯片的所述共用电源电压之间;以及
至少一个横向电磁(TEM)传输线介质,将所述多个功率晶体管芯片的共用栅极输入端耦接至所述多个栅极驱动器芯片的共用输出端,且其电流方向垂直于所述多个功率晶体管芯片的所述组合宽度。
20.根据权利要求19所述的功率晶体管系统,其中,所述多个栅极驱动器芯片彼此分开,并具有在第一外部栅极驱动器芯片的边缘和第二外部栅极驱动器芯片的相对边缘之间延伸的组合宽度,且其中,至少一个TEM传输线介质包括将所述多个功率晶体管芯片的所述共用栅极输入端耦接至所述多个栅极驱动器芯片的所述共用输出端的第一TEM传输线介质和第二TEM传输线介质,所述第一TEM传输线介质的电流方向垂直于所述多个功率晶体管芯片的组合宽度,所述第二TEM传输线介质的电流方向垂直于所述多个栅极驱动器芯片的组合宽度。
21.根据权利要求19所述的功率晶体管系统,进一步包括第三TEM传输线介质,将所述第一TEM传输线介质耦接至所述第二TEM传输线介质。
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