CN103050441B - Oxide thin film transistor preparation method - Google Patents
Oxide thin film transistor preparation method Download PDFInfo
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- CN103050441B CN103050441B CN201210528281.9A CN201210528281A CN103050441B CN 103050441 B CN103050441 B CN 103050441B CN 201210528281 A CN201210528281 A CN 201210528281A CN 103050441 B CN103050441 B CN 103050441B
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Abstract
The invention provides an oxide thin film transistor preparation method which comprises the steps of: sequentially forming a grid electrode, a semi-conductor insulating layer and a metal oxide layer on a substrate; then, forming a first patterned photo-resisting layer on the metal oxide layer through a gray scale photomask and using the first patterned photo-resisting layer as a mask screen to form a patterned metal oxide layer; removing part of the first patterned photo-resisting layer to form a second patterned photo-resisting layer; then, sequentially forming a metal layer and a third patterned photo-resisting layer and using the third patterned photo-resisting layer as the mask screen to etch the metal layer to form a source electrode region and a drain electrode region and expose the second patterned photo-resisting layer; and removing the third patterned photo-resisting layer and part of the second patterned photo-resisting layer to form a fourth patterned photo-resisting layer.
Description
Technical field
The invention relates to a kind of transistor fabrication process, relate to especially a kind of manufacture method of oxide thin film transistor.
Background technology
In recent years, the development of flat-panel screens is more and more rapider, has replaced gradually traditional cathode-ray tube display.Flat-panel screens now mainly contains following several: organic light emitting diode display (Organic Light-Emitting Diodes Display, OLED), plasma display panel (PlasmaDisplay Panel, PDP), liquid crystal display (Liquid Crystal Display, and Field Emission Display (Field Emission Display, FED) etc. LCD).The thin-film transistor (Thin Film Transistor, TFT) of wherein controlling the open and close of each pixel in these flat-panel screens, is one of quite critical assembly in these flat-panel screens.
Fig. 1 illustrates the generalized section of known metal oxide thin-film transistor structure.As shown in Figure 1, known metal oxide thin-film transistor structure 10 comprises that a substrate 101, a grid 102 are arranged on substrate 101, semiconductor insulating barrier 103 is arranged on substrate 101 and grid 102, a metal oxide layer 104 is arranged on semiconducting insulation layer 103, one source pole 105 is arranged at respectively on metal oxide layer 104 with a drain electrode 106, and source electrode 105 106 is to form via etching one metal level with draining.But known metal oxide thin-film transistor 10 is in the time carrying out the etch process of source electrode 105 and drain electrode 106, the often meeting of metal oxide layer 104 that is positioned at source electrode 105 and drain electrode 106 belows cause the situation of broken string because being subject to the erosion of metal etch liquid.
Therefore, how effectively to avoid metal oxide layer at source electrode with drain electrode when etching, not corroded by etching solution or the destruction of other successive process, become the target of pursuit to promote the quality of oxide thin film transistor and process rate.
Summary of the invention
In view of this; the invention provides a kind of oxide thin film transistor manufacturing method thereof; on metal oxide layer, retain photoresist layer by a gray-level mask; protect metal oxide layer can not suffer the destruction of etching solution and hydrogen doping, and then promote quality and the process rate of oxide thin film transistor.
An aspect of the present invention is to provide a kind of method of making oxide thin film transistor, comprises: a substrate is provided; Form a grid on substrate; Form semiconductor insulating barrier on grid; Form a metal oxide layer on semiconducting insulation layer; Form one first patterning photoresist layer on metal oxide layer, for example, utilize a gray-level mask to form this first patterning photoresist layer; Then, the first patterning photoresist layer carrys out etching metal oxide skin(coating) as cover curtain and forms a patterning metal oxide layer; Remove part the first patterning photoresist layer and form one second patterning photoresist layer; Form a metal level on semiconducting insulation layer, patterning metal oxide layer and the second patterning photoresist layer; Form one the 3rd patterning photoresist layer on metal level; With this 3rd patterning photoresist layer cover curtain, metal level is etched with and forms one source pole district and a drain region, and expose the second patterning photoresist layer; And remove the 3rd patterning photoresist layer and part this second patterning photoresist layer form one the 4th patterning photoresist layer.
In one embodiment, make the method for oxide thin film transistor and also comprise: form a contact hole layer on metal level and the 4th patterning photoresist layer, and form nurse difficult to understand in source area and drain region and contact.
In one embodiment, the first patterning photoresist layer has one first thickness and one second thickness, and wherein the first thickness is greater than this second thickness.And the position of corresponding this first thickness of metal oxide layer is as a channel region, and the position of corresponding this second thickness of metal oxide layer is as source area and drain region.
In one embodiment, remove part the first patterning photoresist layer and form one second patterning photoresist layer, also comprise this first patterning photoresistance is removed to the second thickness, there is the second patterning photoresist layer of one the 3rd thickness, wherein the 3rd thickness is greater than the second thickness, and the position of corresponding this 3rd thickness of metal oxide layer is as this channel region.Wherein, the first thickness, has the thickness ratio of 3:1:2 between the second thickness and the 3rd thickness.
In one embodiment, the 4th patterning photoresist layer has one the 4th thickness, and the position of corresponding this 4th thickness of metal oxide layer is as channel region.
In one embodiment, use a wet etching to carry out etching to this metal level.
According to this; the present invention utilizes a gray-level mask on metal oxide layer, to form the photoresist layer of different-thickness; use protection metal oxide layer in the time carrying out the wet etch process of metal level; can not suffer the erosion of etching solution; and deposit while contacting hole layer; can not suffer the destruction of hydrogen doping, and then promote quality and the process rate of oxide thin film transistor.
Brief description of the drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended graphic being described as follows:
Fig. 1 illustrates the generalized section of known metal oxide thin-film transistor structure.
Fig. 2 to Figure 13 illustrates the manufacture method schematic diagram of the metal oxide thin-film transistor of a preferred embodiment of the present invention.
[primary clustering symbol description]
10 metal oxide thin-film transistor structures
101 substrates
102 grids
103 semiconducting insulation layers
104 metal oxide layers
105 source electrodes
106 drain electrodes
20 oxide thin film transistor structures
200 substrates
201 grids
202 semiconducting insulation layers
203,208 metal oxide layers
204,210,2071,2072 photoresist layers
207 first patterning photoresist layers
2073 second patterning photoresist layers
211 the 3rd patterning photoresist layers
2074 the 4th patterning photoresist layers
205 gray-level masks
2051,2052,2053 light shield regions
206 light sources
209 metal levels
2091 source areas
2092 drain regions
2093 channel region
2095,2096 nurse contacts difficult to understand
212 contact hole layers
213 transparent metal layers
H1 the first thickness
H2 the second thickness
H3 the 3rd thickness
H4 the 4th thickness
Embodiment
Below described in detail with appended diagram for preferred embodiment of the present invention, following explanation and icon use identical reference number to represent identical or similar assembly, and in the time being repeated in this description identical or similar assembly, give omission.
Please refer to Figure 13, Figure 13 illustrates the generalized section of the oxide thin film transistor structure of a preferred embodiment of the present invention.As shown in figure 13, the oxide thin film transistor structure 20 of the present embodiment comprises a substrate 200; One grid 201 is arranged on substrate 200; Semiconductor insulating barrier 202 is arranged on substrate 200 and grid 201; One metal oxide layer 208 is arranged on semiconducting insulation layer 202; One photoresist layer 2074, one source pole district 2091 and a drain region 2092 are arranged on metal oxide layer 208, and be positioned at the both sides of photoresist layer 2074, in metal oxide layer 208, the position of corresponding photoresist layer 2074 is as channel region, and wherein source area 2091 and drain region 2092 are made up of metal level 209; One contact hole layer 212 is arranged on metal level 209 and photoresist layer 2074, and exposes source area 2091 and drain region 2092, and contact hole layer 212 is as protective layer used, is generally to use chemical vapour deposition technique deposition one deck silicon nitride (SiNx) layer; One transparent metal layer 213 is arranged on contact hole layer 212, can form by a micro image etching procedure pixel electrode of display.In the present embodiment, metal oxide layer 208 is a for example indium oxide gallium zinc layer (Indium Gallium Zinc Oxide, IGZO), but not as limit.For example, metal oxide layer 208 also can be other oxide that comprises indium, zinc, tin, gallium, lead, germanium, cadmium or above-mentioned element combinations, for example indium zinc oxide, zinc-tin oxide, but not as limit.
Please refer to Fig. 2 to Figure 13, Fig. 2 to Figure 13 illustrates the manufacture method schematic diagram of the metal oxide thin-film transistor of a preferred embodiment of the present invention.As shown in Figure 2, first, provide a substrate 200.Subsequently, on substrate 200, form a metal level, a for example micro image etching procedure of recycling, but not as limit, this metal level is carried out etching and forms a grid 201.
Then, as shown in Figure 3, form semiconductor insulating barrier 202 on grid 201 and substrate 200.Then, form a metal oxide layer 203 on semiconducting insulation layer 202.In one embodiment, metal oxide layer 203 utilizes vacuum splashing coating process on semiconducting insulation layer 202, to deposit an indium oxide gallium zinc layer, but not as limit.For example, metal oxide layer 203 also can be other oxide that comprises indium, zinc, tin, gallium, lead, germanium, cadmium or above-mentioned element combinations, for example indium zinc oxide, zinc-tin oxide, but not as limit.In addition, in the present embodiment, metal oxide layer 203 utilizes a vacuum coating processing procedure and is deposited on semiconducting insulation layer 202, but not as limit, for example also can use a solution film forming processing procedure film forming on semiconducting insulation layer 202, or utilize other processing procedure to be formed.
Afterwards, as shown in Figure 4, form a photoresist layer 204 on metal oxide layer 203, in the present embodiment, photoresist layer 204 is by resin, emulsion and solvent composition.Then, utilize 205 pairs of photoresist layers 204 of a light source 206 and a gray-level mask (Gray Level Mask) to carry out an exposure manufacture process.In the present embodiment, gray-level mask 205 is to be placed between light source 206 and photoresist layer 204, and the present embodiment light source 206, for example, be uniform ultraviolet light source (ultraviolet ray, UV ray).Wherein, gray-level mask 205 is differences of utilizing regional penetrance on light shield, while making to expose, different to the depth of exposure of photoresist layer 204, therefore will produce through post-develop resistance layer 204 surfaces the variation that height rises and falls.In the present embodiment; for fear of follow-up while carrying out source area and drain region etch process; be positioned at below is also subject to metal etch liquid erosion as the metal oxide layer of channel region; therefore the photoresist layer 204 in respective channels district and the photoresist layer 204 of corresponding source area and drain region; after developing, to there is different thickness, use guard channel district.Therefore, the gray-level mask 205 of this case has three light shield regions 2051 that penetrance is different, 2052 and 2053, in one embodiment, the penetrance the best in light shield region 2053, take second place in light shield region 2052, light shield region 2051 is minimum, therefore, after developing, after the photoresist layer 204 at 2053 places, corresponding light shield region removes completely, the photoresist layer in corresponding light shield region 2051 and light shield region 2052 can remain on metal oxide layer 203, and can there is different thickness, and form the first patterning photoresist layer 207 as shown in Figure 5.Because the penetrance in light shield region 2052 is higher than light shield region 2053, therefore the first patterning photoresist layer 207 after developing will have two different-thickness, the first thickness H1 and the second thickness H2, wherein the photoresist layer 2071 in respective channels district has the first thickness H1, the photoresist layer 2072 of corresponding source area and drain region has the second thickness H2, and the first thickness H1 is three times of the second thickness H2.That is to say, the ratio of photoresist layer 2071 thickness and photoresist layer 2072 thickness is about 3:1, that is the ratio of the first thickness H1 and the second thickness H2 is about 3:1.
Then, as shown in Figure 6, taking the first patterning photoresist layer 207 as cover curtain, metal oxide layer 203 is carried out to etching, to form patterning metal oxide layer 208.Then, as shown in Figure 7, after finishing, etching carries out the ashing processing procedure of the first patterning photoresist layer 207, until remove photoresist layer 2072, expose the surface of partially patterned metal oxide layer 208, in one embodiment, because photoresist layer 2071 thickness are three times of photoresist layer 2072 thickness, therefore remove after photoresist layer 2072 in ashing processing procedure, still possess the photoresist layer not being ashed as the second patterning photoresist layer 2073, wherein, the second patterning photoresist layer 2073 has one the 3rd thickness H3, the 3rd thickness H3 is about 2/3 of script photoresist layer 2071 thickness, therefore the ratio of photoresist layer 2071 thickness and photoresist layer 2072 thickness and the second patterning photoresist layer 2073 thickness is about 3:1:2, that is the first thickness H1, the ratio of the second thickness H2 and the 3rd thickness H3 is about 3:1:2.
Subsequently, as shown in Figure 8, form a metal level 209 on patterning metal oxide layer 208, the second patterning photoresist layer 2073 and semiconducting insulation layer 202.Then, form a photoresist layer 210 on metal level 209, in one embodiment, the thickness of photoresist layer 210 is less than the second patterning photoresist layer 2073.Wherein, in the present embodiment, the metal level and the metal level 209 that form grid 201 can be respectively a single metal level, the for example alloy of aluminium, molybdenum, titanium, chromium, copper, above-mentioned metal or its compound, or a complex metal layer, for example comprise in the alloy of aluminium, molybdenum, titanium, chromium, copper, above-mentioned metal or its compound at least both composition metals.
Then, as shown in Figure 9, photoresist layer 210 is exposed, then the photoresist layer 210 after exposure is developed, form the 3rd patterning photoresist layer 211, define source area 2091, drain region 2092 and channel region 2093.Then, as shown in figure 10, taking the 3rd patterning photoresist layer 211 as cover curtain, metal level 209 is carried out to etching, for example, utilize a wet etch process to remove except the part metals layer 209 not covered by the 3rd patterning photoresist layer 211, to define source area 2091 in metal level 209 places, the position of drain region 2092 and channel region 2093.When wherein the second patterning photoresist layer 2073 is as wet etch process, the protection of the metal oxide layer 208 as channel region 2093 is used.Then, as shown in figure 11, carry out the ashing processing procedure of the 3rd patterning photoresist layer 211, now the second patterning photoresist layer 2073 of part also can be removed, but because the thickness of photoresist layer 210 is less than the second patterning photoresist layer 2073, that is the thickness of the 3rd patterning photoresist layer 211 is less than the second patterning photoresist layer 2073, therefore after photoresistance ashing processing procedure finishes, still possess the photoresist layer not being ashed and form the 4th patterning photoresist layer 2074, wherein the 4th patterning photoresist layer 2074 has one the 4th thickness H4, in one embodiment, the thickness of the 4th patterning photoresist layer 2074 is about the half of the second patterning photoresist layer 2073 thickness originally, that is the 4th thickness H4 be about the half of the 3rd thickness H3.Therefore, the thickness ratio of photoresist layer 2071, the second patterning photoresist layer 2073 and the 4th patterning photoresist layer 2074 is 3:2:1, that is the ratio of the first thickness H1, the 3rd thickness H3 and the 4th thickness H4 is about 3:2:1.In another embodiment, also can adopt the photoresistance liquid of different developing powders to form respectively photoresist layer 210 and the second patterning photoresist layer 2073, now, the thickness that does not limit photoresist layer 210 is less than the second patterning photoresist layer 2073.
Then, as shown in figure 12, on photoresist layer 2074 and metal level 209, form a contact hole (contact hole, CH) layer 212 and the nurse difficult to understand that carries out source area 2091 and drain region 2092 contacts (ohmic contact) 2095 and 2096 making, wherein contacting hole layer is as protective layer used, generally to use chemical vapour deposition technique deposition one deck silicon nitride (SiNx) layer as contact hole layer 212, owing to can involve hydrogen doping (H-doping) in the process that contacts hole layer 212 and nurse contact for producing difficult to understand, be covered on the metal oxide layer 208 as channel region 2074 by photoresist layer 2074, can avoid the metal oxide layer 208 of this part to change conductor into because of hydrogen doping, and destroy transistorized electrical.Then, as shown in figure 13, this contact hole layer 212 of patterning is to expose source area 2091 and 2092 regions, drain region, and deposit a transparent metal layer 213 as pixel electrode and conductive electrode, the material of this metal level, it is for example the transparent conductive film of Zinc oxide doped indium (Indium Zinc Oxide, IZO) or indium tin oxide (Indium TinOxide, ITO).Finally, patternable metal level 213 completes the making of follow-up conductor connecting structure and pixel electrode.
Comprehensive above-mentioned saying, the present invention utilizes a gray-level mask on metal oxide layer, to form the photoresist layer of variable thickness, wherein on the metal oxide layer as channel region, there is the thickest photoresist layer, use in the time carrying out metal level wet etch process thereafter as protective layer, to avoid the metal oxide layer of channel region etched and cause broken string problem; And on metal oxide layer when the layer of deposition contact hole as stop-layer, avoid the hydrogen doping using in deposition process to cause the metal oxide layer of channel region to change conductor into, and then promote quality and the process rate of oxide thin film transistor.
Although the present invention with execution mode openly as above; so it is not in order to limit the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the aforesaid claim person of defining.
Claims (8)
1. a method of making oxide thin film transistor, is characterized in that, comprises:
One substrate is provided;
Form a grid on this substrate;
Form semiconductor insulating barrier on this grid;
Form a metal oxide layer on this semiconducting insulation layer;
Forming one first patterning photoresist layer on this metal oxide layer, is wherein to utilize a gray-level mask to form this first patterning photoresist layer;
Utilize this first patterning photoresist layer to form a patterning metal oxide layer for covering this metal oxide layer of curtain etching;
Remove this first patterning photoresist layer of part and form one second patterning photoresist layer;
Form a metal level on this semiconducting insulation layer, this patterning metal oxide layer and this second patterning photoresist layer;
Form one the 3rd patterning photoresist layer on this metal level;
Taking the 3rd patterning photoresist layer as cover curtain, this metal level is etched with and forms one source pole district and a drain region, and expose this second patterning photoresist layer;
Remove the 3rd patterning photoresist layer and part this second patterning photoresist layer form one the 4th patterning photoresist layer; And
Form a contact hole layer on this metal level and the 4th patterning photoresist layer, and form a nurse contact difficult to understand in He Gai drain region, this source area.
2. the method for making oxide thin film transistor as claimed in claim 1, is characterized in that, this first patterning photoresist layer has one first thickness and one second thickness, and wherein this first thickness is greater than this second thickness.
3. the method for making oxide thin film transistor as claimed in claim 2, it is characterized in that, this metal oxide layer to position that should the first thickness as a channel region, this metal oxide layer to position that should the second thickness as Yu Gai drain region, this source area.
4. the method for making oxide thin film transistor as claimed in claim 3, it is characterized in that, remove this first patterning photoresist layer of part and form this second patterning photoresist layer, also comprise this first patterning photoresistance is removed to this second thickness, there is this second patterning photoresist layer of one the 3rd thickness, wherein the 3rd thickness is greater than this second thickness, this metal oxide layer to position that should the 3rd thickness as a channel region.
5. the method for making oxide thin film transistor as claimed in claim 4, is characterized in that, has the thickness ratio of 3:1:2 between this first thickness, this second thickness and the 3rd thickness.
6. the method for making oxide thin film transistor as claimed in claim 5, is characterized in that, the 4th patterning photoresist layer has one the 4th thickness, this metal oxide layer to position that should the 4th thickness as a channel region.
7. the method for making oxide thin film transistor as claimed in claim 6, is characterized in that, the ratio of this first thickness, the 3rd thickness and the 4th thickness is about 3:2:1.
8. the method for making oxide thin film transistor as claimed in claim 1, is characterized in that, it is to use a wet etching to carry out etching to this metal level that this metal level is carried out to etching.
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| CN103681487A (en) * | 2013-12-13 | 2014-03-26 | 华映视讯（吴江）有限公司 | Thin film transistor substrate and manufacturing method thereof |
| CN107086181B (en) * | 2017-04-18 | 2021-08-13 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display |
| CN109638034B (en) * | 2018-11-06 | 2021-04-27 | 深圳市华星光电半导体显示技术有限公司 | Method for manufacturing display panel |
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| CN100530606C (en) * | 2007-12-05 | 2009-08-19 | 上海广电光电子有限公司 | Thin-film transistor array substrates and manufacturing method therefor |
| JP4752927B2 (en) * | 2009-02-09 | 2011-08-17 | ソニー株式会社 | Thin film transistor and display device |
| CN101572274A (en) * | 2009-05-26 | 2009-11-04 | 友达光电股份有限公司 | Sull transistor with etching barrier layer and preparation method thereof |
| KR101578694B1 (en) * | 2009-06-02 | 2015-12-21 | 엘지디스플레이 주식회사 | Method of fabricating oxide thin film transistor |
| TWI416736B (en) * | 2010-11-19 | 2013-11-21 | Au Optronics Corp | Thin film transistor and method for fabricating the same |
| CN102157565A (en) * | 2011-01-18 | 2011-08-17 | 北京大学深圳研究生院 | Manufacturing method of thin-film transistor |
| CN102157563B (en) * | 2011-01-18 | 2012-09-19 | 上海交通大学 | Method for manufacturing metal oxide thin film transistor |
| CN102163625A (en) * | 2011-03-17 | 2011-08-24 | 复旦大学 | Semiconductor layer material-indium zinc titanium oxide for oxide thin film transistor |
| CN102646699B (en) * | 2012-01-13 | 2014-12-10 | 京东方科技集团股份有限公司 | Oxide TFT (thin film transistor) and manufacturing method thereof |
| CN102709239B (en) * | 2012-04-20 | 2014-12-03 | 京东方科技集团股份有限公司 | Display device, array substrate and production method of array substrate |
| CN102723279A (en) * | 2012-06-12 | 2012-10-10 | 华南理工大学 | Manufacturing method for metal oxide thin film transistor |
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