CN103048839A - Pixel driving circuit and driving method thereof - Google Patents
Pixel driving circuit and driving method thereof Download PDFInfo
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- CN103048839A CN103048839A CN 201310021404 CN201310021404A CN103048839A CN 103048839 A CN103048839 A CN 103048839A CN 201310021404 CN201310021404 CN 201310021404 CN 201310021404 A CN201310021404 A CN 201310021404A CN 103048839 A CN103048839 A CN 103048839A
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- 239000004973 liquid crystal related substance Substances 0.000 abstract description 40
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Abstract
The invention discloses a pixel driving circuit and a driving method thereof, wherein the pixel driving circuit is electrically coupled between a first data line and a second data line and between a first scanning line and a second scanning line, and comprises a first switch, a second switch, a third switch, a fourth switch, a first sub-capacitor, a second sub-capacitor, a fifth switch, a sixth switch, a first capacitor and a second capacitor. The first capacitor is coupled between the second end of the fifth switch and the reference voltage end; the second capacitor is coupled between the second terminal of the sixth switch and the reference voltage terminal for redistributing the stored charges. By adopting the technical scheme of the embodiment of the application, the liquid crystal molecules are driven by a stronger electric field and have larger inclination angle, and further have better penetration performance so as to improve the problems of side-looking color cast and the like.
Description
Technical field
The present invention relates to a kind of pixel-driving circuit, particularly a kind of pixel-driving circuit that promotes the pixel penetrance.
Background technology
Along with liquid crystal indicator constantly develops towards large-sized demonstration specification, in order to overcome the visual angle problem under the large scale demonstration, the wide viewing angle technology of display panels also must ceaselessly improve and break through.The technology that can reach at present the wide viewing angle requirement for example includes multi-zone vertical alignment nematic (MVA), multiple domain horizontal direction matching (MHA), twisted nematic and adds the visual angle and enlarge film (TN+film) and transverse electric field form (In Plane Switching, IPS).
Can reach the purpose of wide viewing angle by the liquid crystal display of above-mentioned listed technology, but the problem that has colour cast (color washout) occurs.Generally speaking, so-called colour cast refer to when the user with the different angles of viewing and admiring when watching the shown image frame of liquid crystal display, the user can see the image frame of different GTGs.For instance, if the user stands in the angle of deflection comparatively (for example 60 degree) when watching the shown image frame of liquid crystal display, the color contrast of the image frame that the user sees can be brighter in the color contrast that stands in the image frame that the angle faced sees.
In order to solve liquid crystal display colour cast problem with great visual angle, but proposed each pixel in the display panels is divided at present the pixel of two drive, one of them can show the color (bright attitude) of higher gray scale, and another can show the color (dark attitude) of low GTG.Thus, after being mixed into the color of GTG in the middle of with the color of the color of higher gray scale and low GTG, though can cause the user from face or with the angle that tilts when watching the shown image frame of liquid crystal display, all can watch the image frame of close color contrast.
At present, for the liquid crystalline type of liquid crystal display with conplane electrode collocation vertical orientation, all be the type of drive of using the same plane electrode.Wherein, the degree of toppling over of liquid crystal molecule depends on and the electric field intensity of experiencing (E) that electric field intensity (E) then is to be decided by electrode separation (d) and driving voltage (V), and this relational expression can represent with E=V/d.Therefore can know that electric field intensity is the impact that is subject to electrode separation and driving voltage.
In order to improve the problem of colour cast, usually can design the electrode separation (multi-pitches) of many groups, so that its pixel shows the performance of wide viewing angle.If reach best side-looking colour cast solution of problem scheme, in the design part of electrode separation, can wish that the shared elemental area ratio of the shared elemental area of wider electrode separation and narrower electrode separation is about 7:3.
Yet wider electrode separation needs higher data (data) driving voltage to produce enough electric fields, so that liquid crystal molecule has larger angle of inclination, and then sufficient penetrance is arranged.For instance, greater than the electrode separation of 16um, want at least the voltage of 16V to drive just to level off to reluctantly degree of saturation.Voltage is the highest to be only had to 16V and existing general integrated circuit is exported, the poor electrode separation that is not enough to drive greater than 16um of voltage folder that liquid crystal is experienced, so that performing poor of the penetrance of wider electrode separation can't use wider electrode separation further to improve the problem of side-looking colour cast.
Summary of the invention
In view of this, the problem that exists in order to overcome prior art, according to the disclosed a kind of pixel-driving circuit of the embodiment of the invention, it is electrically coupled between the first data line and the second data line and between the first sweep trace and the second sweep trace, pixel-driving circuit includes the first switch, second switch, the 3rd switch, the 4th switch, the first sub-electric capacity, the second sub-electric capacity, the 5th switch, the 6th switch, the first electric capacity and the second electric capacity.Wherein the first switch has a first end, one second end and a control end, the first end of the first switch is electrically connected to the first data line, the second end of the first switch is electrically connected to one first pixel electrode, and the control end of the first switch is electrically connected to the first sweep trace; Second switch has a first end, one second end and a control end, and the first end of second switch is electrically connected to the second data line, and the second end of second switch is electrically connected to one second pixel electrode, and the control end of second switch is electrically connected to the first sweep trace; The 3rd switch has a first end, one second end and a control end, and the first end of the 3rd switch is electrically connected to the first data line, and the control end of the 3rd switch is electrically connected to the first sweep trace; The 4th switch has a first end, one second end and a control end, and the first end of the 4th switch is electrically connected to the second data line, and the control end of the 4th switch is electrically connected to the first sweep trace; The first sub-electric capacity is electrically connected between second end and a reference voltage end of the 3rd switch; The second sub-electric capacity is electrically connected between second end and reference voltage end of the 4th switch; The 5th switch has a first end, one second end and a control end, and the first end of the 5th switch is electrically connected to the second end of the 3rd switch, and the control end of the 5th switch is electrically connected to the second sweep trace; The 6th switch has a first end, one second end and a control end, and the first end of the 6th switch is electrically connected at the second end of the 4th switch, and the control end of the 6th switch is electrically connected to the second sweep trace; The first electric capacity is coupled between second end and reference voltage end of the 5th switch; The second electric capacity is coupled between second end and reference voltage end of the 6th switch.
According to driving circuit of the present invention, it shares the mode of (Charge sharing) by electric charge, type of drive in conjunction with two data lines (data line), so that higher liquid crystal cross-pressure to be provided in the liquid crystal capacitance two ends, so that liquid crystal molecule is subject to stronger electric field driven and larger dump angle is arranged, and then the performance of better penetrance arranged, to improve the problem such as side-looking colour cast.
More than about the explanation of the explanation of content of the present invention and following embodiment be in order to demonstration with explain spirit of the present invention and principle, and provide patent claim of the present invention further to explain.
Description of drawings
Fig. 1 is the synoptic diagram of picture element matrix disclosed in this invention.
Fig. 2 A is the circuit diagram of pixel-driving circuit disclosed in this invention.
Fig. 2 B is the circuit diagram of pixel-driving circuit disclosed in this invention.
Fig. 3 is the pixel array circuit schematic layout pattern of pixel-driving circuit disclosed in this invention.
Fig. 4 is the analog waveform figure of pixel-driving circuit disclosed in this invention.
Fig. 5 is the circuit diagram of pixel-driving circuit disclosed in this invention.
Fig. 6 is the pixel array circuit schematic layout pattern of pixel-driving circuit disclosed in this invention.
Fig. 7 is the pixel array circuit layout sectional view of pixel-driving circuit disclosed in this invention.
Fig. 8 is the analog waveform figure of pixel-driving circuit disclosed in this invention.
[main description of reference numerals]
100 picture element matrixs
G
1G
2Sweep trace
D
11The first data line
D
21The second data line
P
11Pixel
200 pixel-driving circuits
201 first switches
202 second switches
203 the 3rd switches
204 the 4th switches
205 the 5th switches
206 the 6th switches
300 pixel array circuit layouts
500 pixel-driving circuits
600 pixel array circuit layouts
The CLC liquid crystal capacitance
C
Sub1The first sub-electric capacity
C
Sub2The second sub-electric capacity
Cst1 the first memory capacitance
Cst2 the second memory capacitance
CS1 the first partial pressure unit
CS2 the second partial pressure unit
C1 the first electric capacity
C2 the second electric capacity
C3 the 3rd electric capacity
C4 the 4th electric capacity
V (D1) the first data voltage
V (D2) the second data voltage
V (P1) P1 voltage
V (P2) P2 voltage
V (S1) S1 voltage
V (S2) S2 voltage
CLC2 the second liquid crystal capacitance
P1 the first pixel electrode
P2 the second pixel electrode
S1 the 3rd pixel electrode
S2 the 4th pixel electrode
V (COM) common electrode
V (CS1) current potential
V (CS2) current potential
Embodiment
Below in embodiment, be described in detail detailed features of the present invention and advantage, its content is enough to make anyly to be familiar with this area those skilled in the pertinent art and to understand technology contents of the present invention and implement according to this, and according to the disclosed content of this instructions, claim scope and accompanying drawing, anyly be familiar with this area those skilled in the pertinent art and can understand easily purpose and the advantage that the present invention is correlated with.Following embodiment further describes viewpoint of the present invention, but is not to limit anyways category of the present invention.
Please refer to Fig. 1, be a kind of circuit framework synoptic diagram of picture element matrix 100.Picture element matrix 100 comprises multi-strip scanning line G
1, G
2G
N-1, G
n, many first data line D
11, D
12D
1 M-1, D
1 mWith many second data line D
21, D
22D
2 M-1, D
2 m, and a plurality of pixel P
1,1, P
1,2P
N, mThe connected mode of picture element matrix, for instance, pixel P
1,1Be electrically connected to corresponding sweep trace G
1With sweep trace G
2, and the first pixel P
11Be electrically connected to the first corresponding data line D
11And the second corresponding data line D
21The first pixel P in the picture element matrix 100
11Be a pixel-driving circuit 200, as described below.
Please refer to Fig. 2 A, be the circuit diagram of pixel-driving circuit 200, mainly is with the first pixel P among Fig. 1
1,1As an illustration.Pixel-driving circuit 200 is electrically coupled to the first data line D
11With the second data line D
21Between, and be electrically coupled to sweep trace G
1With sweep trace G
2Between.Pixel-driving circuit 200 includes the first switch 201, second switch 202, the 3rd switch 203, the 4th switch 204, the first pixel electrode P1, the second pixel electrode P2, the first sub-capacitor C
Sub1, the second sub-capacitor C
Sub2, the 5th switch 205 and the 6th switch 206, the first partial pressure unit CS1 and the second partial pressure unit CS2, wherein the first partial pressure unit CS1 and the second partial pressure unit CS2 comprise respectively the first capacitor C 1, the second capacitor C 2.
The first switch 201 is transistor, has first end, and the second end, and control end, the first end of the first switch 201 are electrically connected to the first data line D
11, the second end of the first switch 201 is electrically connected on the first pixel electrode P1, and the control end of the first switch 201 is electrically connected to sweep trace G
1Second switch 202 is transistor, has first end, and the second end, and control end, the first end of second switch 202 are electrically connected to the second data line D
21, the second end of second switch 202 is electrically connected on the second pixel electrode P2, and the control end of second switch 202 is electrically connected to sweep trace G
1The 3rd switch 203 is transistor, has first end, and the second end, and control end, the first end of the 3rd switch 203 are electrically connected to the first data line D
11, the control end of the 3rd switch 203 is electrically connected to sweep trace G
1The 4th switch 204 is transistor, has first end, and the second end, and control end, the first end of the 4th switch 204 are electrically connected to the second data line D
21, the control end of the 4th switch 204 is electrically connected to sweep trace G
1Have liquid crystal pressure reduction between the gap (split) of the first pixel electrode P1 and the second pixel electrode P2 and form liquid crystal capacitance CLC.The first sub-capacitor C
Sub1Have first end and the second end, be electrically connected between second end and reference voltage end of the 3rd switch 203; The second sub-capacitor C
Sub2Have first end and the second end, be electrically connected between second end and reference voltage end of the 4th switch 204.The first capacitor C 1 has first end and the second end, is coupled between the first pixel electrode P1 and the reference voltage end; The 5th switch 205 is transistor, has first end, and the second end, and control end, the first end of the 5th switch 205 are electrically connected to the second end of the 3rd switch 203, the control end of the 5th switch 205 is electrically connected to sweep trace G
2, and the second end of the 5th switch 205 be electrically connected at the first end of the first capacitor C 1; The 6th switch 206 is transistor, has first end, the second end, and control end, the first end that the control end that the second end of the 6th switch 206 is electrically connected at the first end of the second capacitor C 2, the 6th switch 206 is electrically connected to sweep trace G2 and the 6th switch 206 is electrically connected to the second end of the 4th switch 204.
Please refer to Fig. 2 B, pixel-driving circuit 200 of the present invention also can comprise the first memory capacitance Cst1, the second memory capacitance Cst2, and the first partial pressure unit CS1 can also comprise the 3rd capacitor C 3, and the second partial pressure unit CS2 can also comprise the 4th capacitor C 4.The first memory capacitance Cst1 has first end and the second end, and the first end of the first memory capacitance Cst1 is electrically connected to the second end of the first switch 201 and the second end of the first memory capacitance Cst1 is electrically connected to reference voltage end; The second memory capacitance Cst2 has first end and the second end, and the first end of the second memory capacitance Cst2 is electrically connected to the second end of second switch 202 and the second end of the second memory capacitance Cst2 is electrically connected to reference voltage end; The 3rd capacitor C 3 has first end and the second end, is electrically connected between the first capacitor C 1 and the first pixel electrode P1; The 4th capacitor C 4 has first end and the second end, is electrically connected between the second capacitor C 2 and the second pixel electrode P2.
Please refer to Fig. 3, it is the synoptic diagram of the pixel array circuit layout 300 of pixel-driving circuit 200 of the present invention.For corresponding with aforesaid embodiment, therefore identical element adopts same label.Pixel array circuit layout 300 comprises the first switch 201, second switch 202, the 3rd switch 203, the 4th switch 204, the 5th switch 205, the 6th switch 206, the first sub-capacitor C
Sub1, the second sub-capacitor C
Sub2, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3 and the 4th capacitor C 4, sweep trace G
1, G
2And the first data line D
11With the second data line D
21Sweep trace G wherein
1With sweep trace G
2With the first data line D
11With the second data line D
21Intersect vertically in fact, each switch is connected in sweep trace and data line.The first switch 201 and sweep trace G
1And the first data line D
11Be electrically connected; Second switch 202 and sweep trace G
1And the second data line D
21Be electrically connected; The 3rd switch 203 and sweep trace G
1And the first data line D
11Be electrically connected; The 4th switch 204 and sweep trace G
1And the second data line D
21Be electrically connected.The 5th switch 205 and the 6th switch 206 and sweep trace G
2Be electrically connected.The 3rd switch 203 and sweep trace G
1And 205 electric connections of the 5th switch, the 3rd switch 203 and the 5th switch 205 are electrically connected to the first sub-capacitor C
Sub1, adjacent the first capacitor C 1 and the 3rd capacitor C 3.In addition, the 4th switch 204 and sweep trace G
1And 206 electric connections of the 6th switch, the second sub-capacitor C
Sub2Adjacent the second capacitor C 2 and the 4th capacitor C 4.The first pixel electrode P1 is finger electrode, and it is electrically connected at the first switch 201 and the 3rd capacitor C 3, and the second pixel electrode P2 is finger electrode, and it is electrically connected at second switch 202 and the 4th capacitor C 4.And has common electrode V (COM) in the first data line D
11With the second data line D
21Between.
Please refer to Fig. 4, it is the analog waveform figure of the pixel-driving circuit 200 of Fig. 2 A of the present invention.And driving method of the present invention and operation be described simultaneously.Wherein when the first data voltage was positive potential, the second data voltage was negative potential.In the very first time of one-period sweep trace G
1Enable, conducting the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204 provide the first data voltage via this first data line D
11To the first sub-capacitor C
Sub1And forming the first memory capacitance Cst1, the first partial pressure unit CS1 then keeps the current potential of one-period; And provide the second data voltage that polarity is different from the first data voltage via the second data line D
21To the second sub-capacitor C
Sub2And form the second memory capacitance Cst2, and the second partial pressure unit CS2 then keeps the current potential of one-period, and the current potential of the first pixel electrode P1, the second pixel electrode P2 and node S1, node S2 is charged to corresponding data voltage.
Then, in the second time scan line G
1Close, and sweep trace G
2When opening, conducting the 5th switch 205 and the 6th switch 206, and again memory allocated in the first sub-capacitor C
Sub1Reach the first data voltage of the first partial pressure unit CS1 and redistribute and be stored in the second sub-capacitor C
Sub2And the second data voltage of the second partial pressure unit CS2.The original first sub-capacitor C
Sub1With the second sub-capacitor C
Sub2The electric charge that keeps can be via the first capacitor C 1 and the second capacitor C 2 and is redistributed electric charge, share electric charge to the first partial pressure unit CS1 by node S1, and the second partial pressure unit CS2 shares electric charge to node S2, so that node S1 current potential equates with the first partial pressure unit CS1 current potential, and node S2 current potential equates with the second partial pressure unit CS2 current potential.
Please refer to Fig. 4, be the analog waveform figure of Fig. 2 B pixel-driving circuit 200 of the present invention.Fig. 2 A pixel-driving circuit 200 similar haply to Fig. 2 B pixel-driving circuit 200, different is that the first partial pressure unit CS1 comprises in addition the 3rd capacitor C 3 and the second partial pressure unit CS2 comprises the 4th capacitor C 4 in addition.Wherein when the first data voltage was positive potential, the second data voltage was negative potential.In the very first time of one-period sweep trace G
1Enable, conducting the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204 provide the first data voltage via this first data line D
11To the first sub-capacitor C
Sub1And form the first memory capacitance Cst1, and the current potential V (CS1) of the first partial pressure unit CS1 also can be induced to by the current potential in a upper cycle high potential; And provide the second data voltage that polarity is different from the first data voltage via the second data line D
21To the second sub-capacitor C
Sub2And form the second memory capacitance Cst2, and the second partial pressure unit CS2 current potential V (CS2) also can be induced to than electronegative potential, the current potential of the first pixel electrode P1, the second pixel electrode P2 and node S1, node S2 is charged to corresponding data voltage.
Then, in the second time scan line G
1Close, and sweep trace G
2When opening, conducting the 5th switch 205 and the 6th switch 206, and again memory allocated in the first sub-capacitor C
Sub1Reach the first data voltage V (D1) of the first partial pressure unit CS1 and redistribute and be stored in the second sub-capacitor C
Sub2And the second data voltage V (D2) of the second partial pressure unit CS2.The original first sub-capacitor C
Sub1With the second sub-capacitor C
Sub2The electric charge that keeps can be via the first capacitor C 1 and the second capacitor C 2 and is redistributed electric charge, share electric charge to the first partial pressure unit CS1 by node S1, and the second partial pressure unit CS2 shares electric charge to node S2, so that node S1 current potential equates with the first partial pressure unit CS1 current potential, and node S2 current potential equates with the second partial pressure unit CS2 current potential, and the current potential V (P1) of the first pixel electrode P1 is induced to high potential and the current potential V (P2) of the second pixel electrode P2 is induced to than electronegative potential simultaneously.And then improve the liquid crystal cross-pressure V (P1) between the first pixel electrode P1, the second pixel electrode P2-V (P2) in the pixel-driving circuit 200, make its value be higher than the driving scope of data voltage.
Enable scans line G when the very first time
1The time, conducting the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204, and the first data voltage V (D1) is provided, the first pixel electrode P1 voltage V (P1) and node S1 voltage V (S1) also rise along with the first data voltage V (D1).Provide in addition polarity to be different from the second data voltage V (D2) of the first data voltage V (D1), the second pixel electrode P2 voltage V (P2) and node S2 voltage V (S2) also descend along with the second data voltage V (D2).At this moment, the first pixel electrode P1 and node S1 are by the first data line D
11Full charging is to positive voltage, and the second pixel electrode P2 and node S2 are by the second data line D
21Full charging is to negative voltage.
Then, close sweep trace G in the second time
1And enable scans line G
2The time, the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204 are closed, and the 5th switch 205 and the 6th switch 206 are switched on respectively.This moment the first sub-capacitor C
Sub1The electric charge that keeps can be redistributed via the first capacitor C 1, and node S1 voltage V (S1) descended so that the first pixel electrode P1 voltage V (P1) current potential rises after electric charge was shared.Simultaneously, the second sub-capacitor C
Sub2The electric charge that keeps can be redistributed via the second capacitor C 2, and the second pixel electrode P2 voltage V (P2) current potential descends and node S2 voltage V (S2) rising, and the liquid crystal cross-pressure between the first pixel electrode P1 like this, the second pixel electrode P2 will be raised.
Please refer to Fig. 5, be the circuit diagram of another embodiment of the present invention pixel-driving circuit 500.Present embodiment is identical haply with pixel-driving circuit 200, in addition, other comprises the 3rd pixel electrode S1 and the 4th pixel electrode S2, and the gap of the 3rd pixel electrode S1 and the 4th pixel electrode S2 also has the liquid crystal cross-pressure and forms the second liquid crystal capacitance CLC2, and the first pixel electrode P1 and the second pixel electrode P2 and the 3rd pixel electrode S1 and the 4th pixel electrode S2 have respectively wider electrode separation design and narrower electrode separation design.So design can make the second liquid crystal capacitance CLC2 have the first sub-capacitor C
Sub1With the second sub-capacitor C
Sub2Function, reduce whereby the first sub-capacitor C
Sub1With the second sub-capacitor C
Sub2Shared layout area not only can improve aperture opening ratio, increases the cross-pressure between the pixel electrode, more can further improve the problem of looking colour cast of surveying.On the other hand, the second liquid crystal capacitance CLC2 that forms because of the liquid crystal cross-pressure of the 3rd pixel electrode S1 and the 4th pixel electrode S2 gap itself does not need too high liquid crystal cross-pressure, electric charge can be shared to the liquid crystal capacitance CLC that forms between the first pixel electrode P1, the second pixel electrode P2, so as to improving the liquid crystal cross-pressure of liquid crystal capacitance CLC.The 3rd pixel electrode S1 and the 4th pixel electrode S2 will illustrate with node S1 and node S2 on circuit diagram.
Pixel-driving circuit 500 is electrically coupled to the first data line D
11With the second data line D
21Between, and be electrically coupled to sweep trace G
1With sweep trace G
2Between.Pixel-driving circuit 200 includes the first switch 201, second switch 202, the 3rd switch 203, the 4th switch 204, the first pixel electrode P1, the second pixel electrode P2, the 3rd pixel electrode S1, the 4th pixel electrode S2, liquid crystal capacitance CLC, the second liquid crystal capacitance CLC2, the first memory capacitance Cst1, the second memory capacitance Cst2, the first sub-capacitor C
Sub1, the second sub-capacitor C
Sub2, the first partial pressure unit CS1 and the second partial pressure unit CS2.
Wherein the first switch 201 is transistor, has first end, the second end and control end, and the first end of the first switch 201 is electrically connected to the first data line D
11, the second end of the first switch 201 is electrically connected on the first pixel electrode P1, and the control end of the first switch 201 is electrically connected to sweep trace G
1Second switch 202 is transistor, has first end, the second end and control end, and the first end of second switch 202 is electrically connected to the second data line D
21, the second end of second switch 202 is electrically connected on the second pixel electrode P2, and the control end of second switch 202 is electrically connected to sweep trace G
1The 3rd switch 203 is transistor, has first end, the second end and control end, and the first end of the 3rd switch 203 is electrically connected to the first data line D
11, the second end of the 3rd switch 203 is electrically connected on the 3rd pixel electrode S1, and the control end of the 3rd switch 203 is electrically connected to sweep trace G
1The 4th switch 204 is transistor, has first end, the second end and control end, and the first end of the 4th switch 204 is electrically connected to the second data line D
21, the second end of the 4th switch 204 is electrically connected on the 4th pixel electrode S2, and the control end of the 4th switch 204 is electrically connected to sweep trace G
1
The first memory capacitance Cst1 has first end and the second end, and the first end of the first memory capacitance Cst1 is electrically connected to the second end of the first switch 201 and the second end of the first memory capacitance Cst1 is electrically connected to reference voltage end; The second memory capacitance Cst2 has first end and the second end, and the first end of the second memory capacitance Cst2 is electrically connected to the second end of second switch 202 and the second end of the second memory capacitance Cst2 is electrically connected to reference voltage end; The first sub-capacitor C
Sub1Be electrically connected between second end and reference voltage end of the 3rd switch 203; The second sub-capacitor C
Sub2Be electrically connected between second end and reference voltage end of the 4th switch 204.
The 5th switch 205 is transistor, has first end, and the second end, and control end, the first end of the 5th switch 205 are electrically connected to the second end of the 3rd switch 203, the control end of the 5th switch 205 is electrically connected to sweep trace G
2, and the second end of the 5th switch 205 be electrically connected at the first partial pressure unit CS1, be stored in the first sub-capacitor C in order to redistribute
Sub1, the electric charge between the first memory capacitance Cst1 and the first partial pressure unit CS1; The 6th switch 206 is transistor, has first end, the second end, and control end, the second end that the control end that the first end of the 6th switch 206 is electrically connected to the second end, the 6th switch 206 of the 4th switch 204 is electrically connected to sweep trace G2 and the 6th switch 206 is electrically connected at the second partial pressure unit CS2, is stored in the second sub-capacitor C in order to redistribute
Sub2, the electric charge of the second memory capacitance Cst2 and the electric charge between the second partial pressure unit CS2.
The first partial pressure unit CS1 includes the first capacitor C 1, have first end and the second end, the first end of the first capacitor C 1 is electrically connected on the second end of the 5th switch 205, the second end of the first capacitor C 1 is electrically connected at reference voltage end, the second partial pressure unit CS2 includes the second capacitor C 2, have first end and the second end, the first end of the second capacitor C 2 is electrically connected on the second end of the 6th switch 206, and the second end of the second capacitor C 2 is electrically connected at reference voltage end.
In another embodiment of the present invention, the first partial pressure unit CS1 includes the first capacitor C 1 and the 3rd capacitor C 3 of mutual series connection in addition, have respectively first end and the second end, be electrically connected between second end and reference voltage end of the first switch 201, the second end of the first end of the first capacitor C 1 and the 3rd capacitor C 3 is electrically connected on the second end of the 5th switch 205, the first end of the 3rd capacitor C 3 is electrically connected at the second end of the first switch 201, and the second end of the first capacitor C 1 is electrically connected on reference voltage end; The second partial pressure unit CS2 also includes the second capacitor C 2 and the 4th capacitor C 4 of mutual series connection, have respectively first end and the second end, be electrically connected between second end and reference voltage end of second switch 202, the second end of the first end of the second capacitor C 2 and the 4th capacitor C 4 is electrically connected on the second end of the 6th switch 206, the first end of the 4th capacitor C 4 is electrically connected at the second end of second switch 202, and the second end of the second capacitor C 2 is electrically connected on reference voltage end.
Please refer to Fig. 6, it is the synoptic diagram of the pixel array circuit layout 600 of another embodiment of the present invention.Here for corresponding with aforesaid embodiment, therefore same element adopts same label.Pixel array circuit layout 600 comprises the first switch 201, second switch 202, the 3rd switch 203, the 4th switch 204, the 5th switch 205, the 6th switch 206, the first sub-capacitor C
Sub1, the second sub-capacitor C
Sub2, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3 and the 4th capacitor C 4, sweep trace G
1With sweep trace G
2And the first data line D
11With the second data line D
21Sweep trace G wherein
1With sweep trace G
2With the first data line D
11With the second data line D
21Intersect setting, each switch is connected in sweep trace and data line.The first switch 201 and sweep trace G
1And the first data line D
11Be electrically connected; Second switch 202 and sweep trace G
1And the second data line D
21Be electrically connected; The 3rd switch 203 and sweep trace G
1And the first data line D
11Be electrically connected; The 4th switch 204 and sweep trace G
1And the second data line D
21Be electrically connected.The 5th switch 205 and the 6th switch 206 and sweep trace G
2Be electrically connected.The 3rd switch 203 and sweep trace G
1And 205 electric connections of the 5th switch, the 3rd switch 203 and the 5th switch 205 are electrically connected to the first sub-capacitor C
Sub1, adjacent the first capacitor C 1 and the 3rd capacitor C 3.In addition, the 4th switch 204 and sweep trace G
1And 206 electric connections of the 6th switch, the second sub-capacitor C
Sub2Adjacent the second capacitor C 2 and the 4th capacitor C 4; The first pixel electrode P1 is finger electrode, be electrically connected at the first switch 201 and the 3rd capacitor C 3, and the second pixel electrode P2 is finger electrode, is electrically connected at second switch 202 and the 4th capacitor C 4; The 3rd pixel electrode S1 is finger electrode, is electrically connected at the 5th switch 205 and the first sub-capacitor C
Sub1, and the 4th pixel electrode S2 is finger electrode, is electrically connected at the 6th switch 206 and the second sub-capacitor C
Sub2And has a common electrode V (COM) in the first data line D
11With the second data line D
21Between.
Please refer to Fig. 7, it is the sectional view of the pixel array circuit layout 600 of another embodiment of the present invention.The diagram midship section structure is square section in the pixel array circuit layout 600.As shown in Figure 7, the gap between the first pixel electrode P1 and the second pixel electrode P2 is greater than the gap between the 3rd pixel electrode S1 and the 4th pixel electrode S2.
Please refer to Fig. 8, be the analog waveform figure of pixel-driving circuit 500.And demonstration example driving method and an operation of the present invention be described simultaneously.Wherein when the first data voltage was positive potential, the second data voltage was negative potential.In very first time conducting the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204, and during enable scans line G1, provide the first data voltage via this first data line D
11To the first sub-capacitor C
Sub1And the first memory capacitance Cst1, and the current potential V (CS1) of the first partial pressure unit CS1 also can be induced to by the current potential in a upper cycle high potential; And provide the second data voltage that polarity is different from the first data voltage via the second data line D
21To the second sub-capacitor C
Sub2And the second memory capacitance Cst2, and the second partial pressure unit CS2 current potential V (CS2) also can be induced to than electronegative potential, and the first pixel electrode P1, the second pixel electrode P2, the 3rd pixel electrode S1 and the 4th pixel electrode S2 are charged to respectively corresponding data voltage.
Then, in the second time conducting the first partial pressure unit CS1 and the second partial pressure unit CS2, and again memory allocated in the first sub-capacitor C
Sub1And the first data voltage of the first partial pressure unit CS1, and redistribute and be stored in the second sub-capacitor C
Sub2And the second data voltage of the second partial pressure unit CS2.Sweep trace G
1Close, and sweep trace G
2When opening, the original first sub-capacitor C
Sub1The electric charge that keeps can be redistributed electric charge in the pixel via the first capacitor C 1 and the 3rd capacitor C 3, shares electric charge to the first partial pressure unit CS1 by node S1, and the second sub-capacitor C
Sub2The electric charge that keeps can be via the second capacitor C 2 and the 4th capacitor C 4 and is redistributed electric charge in the pixel, and the second partial pressure unit CS2 shares electric charge to node S2, so that node S1 current potential equates with the first partial pressure unit CS1 current potential, and node S2 current potential equates with the second partial pressure unit CS2 current potential, and the current potential V (P1) of the first pixel electrode P1 is induced to high potential and the current potential V (P2) of the second pixel electrode P2 is induced to than electronegative potential simultaneously.And then improve the liquid crystal capacitance CLC cross-pressure V (P1) that forms between the first pixel electrode P1 and the second pixel electrode P2-V (P2), make the liquid crystal cross-pressure be higher than the driving scope of data voltage.The the second liquid crystal capacitance CLC2 that forms between the 3rd pixel electrode S1 and the 4th pixel electrode S2 then experiences the first sub-capacitor C
Sub1And the second sub-capacitor C
Sub2Between change in voltage, its both sides cross-pressure is less.
Enable scans line G when the very first time
1The time, conducting the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204, and the first data voltage V (D1) is provided, the first pixel electrode P1 voltage V (P1) and the 3rd pixel electrode S1 voltage V (S1) also rise along with the first data voltage V (D1).The the second data voltage V (D2) that provides in addition polarity to be different from the first data voltage V (D1), the second pixel electrode P2 voltage V (P2) and the 4th pixel electrode S2 voltage V (S2) also descend along with the second data voltage V (D2).At this moment, the first pixel electrode P1 and the 3rd pixel electrode S1 are by the first data line D
11Full charging is to positive electrode, and the second pixel electrode P2 and the 4th pixel electrode S2 are by the second data line D
21Full charging is to negative electrode.
Then, close sweep trace G in the second time
1And enable scans line G
2The time, the first switch 201, second switch 202, the 3rd switch 203 and the 4th switch 204 are closed, and the 5th switch 205 and 206 conductings of the 6th switch.This moment the original first sub-capacitor C
Sub1The first partial pressure unit CS1 that the electric charge that keeps can form via the first capacitor C 1 and the 3rd capacitor C 3 and redistributing, the 3rd pixel electrode S1 voltage V (S1) descended so that the first pixel electrode P1 voltage V (P1) current potential rises after electric charge was shared.The same time, the second sub-capacitor C
Sub2The electric charge that keeps can be via the second capacitor C 2 and the 4th capacitor C 4 and is redistributed electric charge in the pixel, the second pixel electrode P2 voltage V (P2) current potential descends and the 4th pixel electrode S2 current potential V (S2) rising, so, the cross-pressure V (P1) of liquid crystal capacitance CLC-V (P2) significantly is raised and far above drive voltage range.And the variation V (S1) between the 3rd pixel electrode current potential V (S1) and the 4th pixel electrode S2 voltage V (S2)-V (S2), its both sides cross-pressure is less.Present embodiment had for two stages, and V (P1)-V (P2) is used for driving the large liquid crystal cross-pressure of spacing, and V (S1)-V (S2) is used for driving closely spaced liquid crystal cross-pressure, is used for solving small voltage spacing demand.Right the present invention is as limit, when the gap between the 3rd pixel electrode S1 and the 4th pixel electrode S2 greater than the gap between the first pixel electrode P1 and the second pixel electrode P2, also can operate.
According to pixel-driving circuit of the present invention, it is by the shared type of drive in conjunction with two data lines of electric charge, so that higher liquid crystal cross-pressure to be provided in the liquid crystal capacitance two ends, so that liquid crystal molecule is subject to stronger electric field driven and larger dump angle is arranged, and then the performance of better penetrance arranged, to improve the problem such as side-looking colour cast.
Although the present invention with aforesaid embodiment openly as above, so it is not to limit the present invention.Without departing from the spirit and scope of the present invention, the change of doing and retouching all belong to scope of patent protection of the present invention.The protection domain that defines about the present invention please refer to appending claims.
Claims (9)
1. a pixel-driving circuit is electrically coupled between one first data line and one second data line, and is electrically coupled between one first sweep trace and one second sweep trace, and this pixel-driving circuit comprises:
One first switch, have a first end, one second end and a control end, this first end of this first switch is electrically connected to this first data line, and this second end of this first switch is electrically connected to one first pixel electrode, and this control end of this first switch is electrically connected to this first sweep trace;
One second switch, have a first end, one second end and a control end, this first end of this second switch is electrically connected to this second data line, and this of this second switch the second end is electrically connected to one second pixel electrode, and this control end of this second switch is electrically connected to this first sweep trace;
One the 3rd switch has a first end, one second end and a control end, and this first end of the 3rd switch is electrically connected to this first data line, and this control end of the 3rd switch is electrically connected to this first sweep trace;
One the 4th switch has a first end, one second end and a control end, and this first end of the 4th switch is electrically connected to this second data line, and this control end of the 4th switch is electrically connected to this first sweep trace;
One first sub-electric capacity is electrically connected between this second end and a reference voltage end of the 3rd switch;
One second sub-electric capacity is electrically connected between this second end and this reference voltage end of the 4th switch;
One the 5th switch has a first end, one second end and a control end, and this first end of the 5th switch is electrically connected to this second end of the 3rd switch, and this control end of the 5th switch is electrically connected to this second sweep trace;
One the 6th switch has a first end, one second end and a control end, and this first end of the 6th switch is electrically connected at this second end of the 4th switch, and this control end of the 6th switch is electrically connected to this second sweep trace;
One first electric capacity is coupled between this second end and this reference voltage end of the 5th switch; And
One second electric capacity is coupled between this second end and this reference voltage end of the 6th switch.
2. pixel-driving circuit as claimed in claim 1 also comprises:
One the 3rd pixel electrode is electrically connected on this second end of the 3rd switch; And
One the 4th pixel electrode is electrically connected on this second end of the 4th switch.
3. pixel-driving circuit as claimed in claim 1 or 2 also comprises:
One the 3rd electric capacity is electrically connected between this second end of this second end of this first switch and the 5th switch; And
One the 4th electric capacity is electrically connected between this second end of this second end of this second switch and the 6th switch.
4. pixel-driving circuit as claimed in claim 1 or 2 also comprises:
One first memory capacitance is electrically connected between this second end and this reference voltage end of this first switch; And
One second memory capacitance is electrically connected between this second end and this reference voltage end of this second switch.
5. a pixel-driving circuit is electrically coupled between one first data line and one second data line, and is electrically coupled between one first sweep trace and one second sweep trace, and this pixel-driving circuit comprises:
One first switch, have a first end, one second end and a control end, this first end of this first switch is electrically connected to this first data line, and this second end of this first switch is electrically connected to one first pixel electrode, and this control end of this first switch is electrically connected to this first sweep trace;
One second switch, have a first end, one second end and a control end, this first end of this second switch is electrically connected to this second data line, and this of this second switch the second end is electrically connected to one second pixel electrode, and this control end of this second switch is electrically connected to this first sweep trace;
One the 3rd switch has a first end, one second end and a control end, and this first end of the 3rd switch is electrically connected to this first data line, and this control end of the 3rd switch is electrically connected to this first sweep trace;
One the 4th switch has a first end, one second end and a control end, and this first end of the 4th switch is electrically connected to this second data line, and this control end of the 4th switch is electrically connected to this first sweep trace;
One first sub-electric capacity is electrically connected between this second end and a reference voltage end of the 3rd switch;
One second sub-electric capacity is electrically connected between this second end and this reference voltage end of the 4th switch;
One the 5th switch has a first end, one second end and a control end, and this first end of the 5th switch is electrically connected to this second end of the 3rd switch, this control end of the 5th switch is electrically connected to this second sweep trace;
One the 6th switch has a first end, one second end and a control end, and this first end of the 6th switch is electrically connected at this second end of the 4th switch, this control end of the 6th switch is electrically connected to this second sweep trace;
One first partial pressure unit is coupled between this second end and this reference voltage end of the 5th switch; And
One second partial pressure unit is coupled between this second end and this reference voltage end of the 6th switch.
6. pixel-driving circuit as claimed in claim 5 also comprises:
One the 3rd pixel electrode is electrically connected on this second end of the 3rd switch; And
One the 4th pixel electrode is electrically connected on this second end of the 4th switch.
7. such as claim 5 or 6 described pixel-driving circuits, wherein this first partial pressure unit comprises:
One first electric capacity is electrically connected between this second end and this reference voltage end of the 5th switch; And
This second partial pressure unit comprises:
One second electric capacity is electrically connected between this second end and this reference voltage end of the 6th switch.
8. pixel-driving circuit as claimed in claim 7, wherein this first partial pressure unit also comprises:
One the 3rd electric capacity is electrically connected between this second end of this second end of this first switch and the 5th switch; And
This second partial pressure unit also comprises:
One the 4th electric capacity is electrically connected between this second end of this second end of this second switch and the 6th switch.
9. such as claim 5 or 6 described pixel-driving circuits, also comprise:
One first memory capacitance is electrically connected between this second end and this reference voltage end of this first switch; And
One second memory capacitance is electrically connected between this second end and this reference voltage end of this second switch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101144046 | 2012-11-23 | ||
| TW101144046 | 2012-11-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103048839A true CN103048839A (en) | 2013-04-17 |
Family
ID=48061534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201310021404 Withdrawn CN103048839A (en) | 2012-11-23 | 2013-01-21 | Pixel driving circuit and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103048839A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104882105A (en) * | 2015-05-28 | 2015-09-02 | 武汉华星光电技术有限公司 | Liquid crystal drive circuit and liquid crystal display device |
| WO2017020334A1 (en) * | 2015-08-04 | 2017-02-09 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device thereof |
| CN106782400A (en) * | 2017-01-17 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method, display device and its driving method |
| CN108492788A (en) * | 2018-03-05 | 2018-09-04 | 业成科技（成都）有限公司 | Liquid crystal display control device |
-
2013
- 2013-01-21 CN CN 201310021404 patent/CN103048839A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104882105A (en) * | 2015-05-28 | 2015-09-02 | 武汉华星光电技术有限公司 | Liquid crystal drive circuit and liquid crystal display device |
| CN104882105B (en) * | 2015-05-28 | 2017-05-17 | 武汉华星光电技术有限公司 | Liquid crystal drive circuit and liquid crystal display device |
| WO2017020334A1 (en) * | 2015-08-04 | 2017-02-09 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device thereof |
| CN106782400A (en) * | 2017-01-17 | 2017-05-31 | 京东方科技集团股份有限公司 | A kind of image element circuit and its driving method, display device and its driving method |
| CN108492788A (en) * | 2018-03-05 | 2018-09-04 | 业成科技（成都）有限公司 | Liquid crystal display control device |
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Application publication date: 20130417 |